pop tone elimination circuit

Abstract

The utility model relates to a kind of POP sound elimination circuit, comprising: audio chip, delay comparator, PMOS tube, capacitor, mainboard end power supply;One way of mainboard end power supply is grounded through capacitor, one way is grounded through second resistance, second voltage dividing resistance, one way is grounded through fourth resistance, fifth resistance;Audio power supply node is connected between mainboard end power supply and capacitor to power supply for audio chip, and the node is grounded through first resistance, first voltage dividing resistance;Between second resistance and second voltage dividing resistance, between first resistance and first voltage dividing resistance respectively connect the noninverting input end and the same phase input end of delay comparator;The positive / negative pole of the power supply of delay comparator is respectively connected mainboard end power supply / ground, and output one way connects the enable pin of audio chip, one way is grounded through third resistance;Between fourth resistance and fifth resistance connect PMOS tube gate, PMOS tube source is grounded, drain connects the enable pin of audio chip.

Description

Technical Field

[0001] This utility model relates to the field of electronic computer technology, and in particular to a pop sound cancellation circuit. Background Technology

[0002] With the rapid development of computer technology, multimedia computers are widely used, and most computers on the market are equipped with audio devices to provide users with audio input and output functions.

[0003] Computer motherboards typically process computer audio signals through an audio chip. The audio chip can be connected to audio devices such as speakers, external multimedia speakers, and headphones via audio slots or pins on the motherboard to achieve audio input and output functions.

[0004] A pop sound, or plosive sound, refers to a brief "peng" sound in audio effects. It is primarily caused by transient shocks in audio devices during power-on and power-off cycles, or during various operations. In computer products, the pop sound is emitted through the computer's speakers, external multimedia speakers, or headphones when the device is powered on, powered off, switching states (such as plugging / unplugging interfaces, adjusting volume, or switching modes), or when the load changes. The presence of pop sounds not only affects the user's audio experience but also the safety of the playback device.

[0005] The root cause of the pop-up sound is primarily an incorrect power-on / power-off timing of the audio chip. If the audio chip's enable pin (AUDIO_EN) is on during power-on / power-off and its mute pin (MUTE) is not in a mute state, a pop-up sound will be generated at the moment of power-on / power-off. Therefore, to eliminate the power-on / power-off pop-up sound, a common method is to use a control chip such as a CPU or EC (Embedded Controller) to monitor the power-on / power-off process and control the audio chip's enable pin (AUDIO_EN) (generally, the audio chip is off when AUDIO_EN is low and on when it is high) or the mute pin (MUTE) (generally, the audio chip is mute when MUTE is low and unmute when it is high), thereby controlling the audio chip's power-on / power-off timing to prevent the pop-up sound. However, this method requires the control chip's resources and necessitates real-time monitoring of the system voltage, increasing the control chip's workload. Summary of the Invention

[0006] Therefore, the purpose of this utility model is to provide a pop sound cancellation circuit that achieves power-on / power-off pop sound cancellation through hardware without occupying the resources of the control chip.

[0007] To achieve the above objectives, this utility model provides a pop noise cancellation circuit, comprising: an audio chip, a delay comparator, a PMOS transistor, a capacitor, and a motherboard power supply. The motherboard power supply has three paths: one connected to a capacitor and then grounded; another path connected to a second resistor and a second voltage divider resistor and then grounded; and yet another path connected to a fourth resistor and a fifth resistor and then grounded. An audio power supply node is connected between the motherboard power supply and the capacitor. This audio power supply node is connected to the audio chip to supply power to it. The audio power supply node is grounded via a first resistor and a first voltage divider resistor. The second resistor and the second voltage divider resistor are connected to the inverting input of the delay comparator, and the first resistor and the first voltage divider resistor are connected to the non-inverting input of the delay comparator. The positive terminal of the delay comparator is connected to the motherboard power supply, the negative terminal is grounded, and one output is connected to the enable pin of the audio chip, while the other is grounded via a third resistor. The fourth and fifth resistors are connected to the gate of the PMOS transistor, the source of the PMOS transistor is grounded, and the drain is connected to the enable pin of the audio chip. The minimum operating voltage of the audio chip, the power supply voltage of the motherboard, the ratio of the resistance of the first resistor to the resistance of the first voltage divider resistor, and the ratio of the resistance of the second resistor to the resistance of the second voltage divider resistor must satisfy the following conditions: Among them, V AUDIO-MIN V is the minimum operating voltage of the audio chip. P3V3 K1 is the voltage of the motherboard power supply, K2 is the ratio of the resistance of the first resistor to the resistance of the first voltage divider resistor, and K2 is the ratio of the resistance of the second resistor to the resistance of the second voltage divider resistor.

[0008] Preferably, the power supply of the motherboard is connected in series with a capacitor after passing through the first ferrite bead, and an audio power supply node is connected between the first ferrite bead and the capacitor.

[0009] Optionally, the audio power supply node is connected to the audio chip via a second ferrite bead.

[0010] Preferably, the motherboard power supply is 3.3V, the audio chip operates at 2.7V~3.6V, the capacitor has a capacitance of 10 µF, the ratio of the first resistor to the first voltage divider resistor is 1:1, and the ratio of the second resistor to the second voltage divider resistor is 4:3.

[0011] Preferably, the resistance values ​​of the first resistor, the second resistor, and the first voltage divider resistor are all 100kΩ, and the resistance value of the second voltage divider resistor is 75kΩ.

[0012] Preferably, the resistance of the third resistor is 10 kΩ, the resistance of the fourth resistor is 1 kΩ, and the resistance of the fifth resistor is 1.1 kΩ.

[0013] Preferably, the impedance of the first magnetic bead is 600 Ω.

[0014] Preferably, the impedance of the second magnetic bead is 600 Ω.

[0015] Preferably, the delay comparator is an SGM8743.

[0016] Preferably, the PMOS transistor is a BSS84.

[0017] The beneficial effects of this invention are as follows: The pop-up noise cancellation circuit of this invention utilizes a rapid power-down shutdown circuit to forcibly pull down the enable pin of the audio chip at the moment of power drop on the motherboard, completely eliminating power-down pop-up noise. A delay comparator ensures that the audio chip's supply voltage rises above its minimum operating voltage before allowing the enable pin to go high, thus eliminating power-on pop-up noise. This invention's pop-up noise cancellation circuit achieves power-on / power-down pop-up noise cancellation through hardware, enabling fast and reliable control without relying on CPU or EC control chips. It does not require real-time voltage monitoring, does not occupy control chip resources, and can reliably operate in any power-down scenario. Attached Figure Description

[0018] The technical solution and other beneficial effects of this utility model will become apparent from the following detailed description of specific embodiments, in conjunction with the accompanying drawings.

[0019] Figure 1 This is a circuit diagram of an embodiment of the pop noise cancellation circuit of this utility model;

[0020] Figure 2-3 for Figure 1 A schematic diagram of the pin wiring of the audio chip section of the pop noise cancellation circuit;

[0021] Figure 4 for Figure 1 The power-on and power-off timing diagram of the pop noise cancellation circuit. Detailed Implementation

[0022] To further illustrate the technical means and effects of this utility model, the following detailed description is provided in conjunction with the preferred embodiments of this utility model and their accompanying drawings.

[0023] See Figure 1-3 This utility model provides a pop sound cancellation circuit, including: an audio chip 1, a delay comparator U41, a PMOS transistor Q59, a capacitor C1, and a motherboard power supply P3V3; The motherboard power supply P3V3 is connected to ground via three paths: one path is connected in series with capacitor C1, another path is connected to ground via the second resistor R21 and the second voltage divider resistor R22, and yet another path is connected to ground via the fourth resistor R4 and the fifth resistor R5. The motherboard power supply P3V3 and capacitor C1 are connected to an audio power supply node (VCC_AUDIO node). This audio power supply node is connected to the audio chip 1 to supply power. The audio power supply node is connected to ground via the first resistor R11 and the first voltage divider resistor R12. The second resistor R21 and the second voltage divider resistor R22 are connected to the inverting input terminal (pin 5 of U41) of the delay comparator U41. The first resistor R11 and the first voltage divider resistor R12 are connected to... The non-inverting input terminal of the delay comparator U41 (pin 4 of U41); the positive power supply terminal of the delay comparator U41 (pin 1 of U41) is connected to the motherboard power supply P3V3, the negative power supply terminal (pin 2 of U41) is grounded, and the output terminal (pin 3 of U41) is connected to the enable pin AUDIO_EN of the audio chip 1 (pin 15 of the audio chip 1) in one path and to grounded through the third resistor R3 in the other path; the fourth resistor R4 and the fifth resistor R5 are connected to the gate of the PMOS transistor Q59 (pin 1 of Q59), the source of the PMOS transistor Q59 is grounded (pin 2 of Q59), and the drain (pin 3 of Q59) is connected to the enable pin AUDIO_EN of the audio chip 1; The minimum operating voltage of audio chip 1, the voltage of power supply P3V3 on the motherboard, the ratio of the resistance values ​​of the first resistor R11 to the first voltage divider resistor R12, and the ratio of the resistance values ​​of the second resistor R21 to the second voltage divider resistor R22 must satisfy the following conditions: Among them, V AUDIO-MIN V is the minimum operating voltage of audio chip 1. P3V3 K1 represents the voltage of the motherboard power supply P3V3, and K1 represents the resistance of the first resistor R11. 11 The resistance R of the first voltage divider resistor R12 12 The ratio, K2 is the resistance value R of the second resistor R21. 21 The resistance R of the second voltage divider resistor R22 22 The ratio.

[0024] According to the circuit structure of this utility model, the non-inverting input terminal of the delay comparator U41 is connected in parallel with the first voltage divider resistor R12, and the inverting input terminal of the delay comparator U41 is connected in parallel with the second voltage divider resistor R22. Therefore, when the motherboard power supply P3V3 is powered, the voltage V at the inverting input terminal of the delay comparator U41 is... U41- =V P3V3 ×R 22 / (R 21 +R 22 )=V P3V3 ×R22 / (K2×R 22 +R 22 )=V P3V3 / (K2+1), the voltage V at the non-inverting input of the delay comparator U41 U41+ =V VCC_AUDIO ×R 12 / (R 11 +R 12 )=V VCC_AUDIO ×R 12 / (K1×R 12 +R 12 )=V VCC_AUDIO / (K1+1), where V VCC_AUDIO The voltage for the audio power supply node. V U41- >V U41+ At this time, the output of the delay comparator U41 outputs a low-level signal to the enable pin AUDIO_EN of audio chip 1, turning audio chip 1 into the off state; V U41- <V U41+ When V..., the output of delay comparator U41 outputs a high-level signal to the enable pin AUDIO_EN of audio chip 1, causing audio chip 1 to start working. That is, when V... U41- =V U41+ At that time, V P3V3 / (K2+1)=V VCC_AUDIO / (K1+1), at this time, the voltage V of the audio power supply node. VCC_AUDIO It should be greater than the minimum operating voltage V of audio chip 1. AUDIO-MIN Furthermore, since the voltage of the audio power supply node is provided by the motherboard power supply P3V3, the voltage V of the audio power supply node... VCC_AUDIO It must be less than the voltage V of the motherboard power supply P3V3. P3V3 Therefore, this invention sets the minimum operating voltage V of the audio chip 1. AUDIO-MIN The voltage of the motherboard power supply P3V3 is V. P3V3 The resistance ratio K1 of the first resistor R11 to the first voltage divider resistor R12, and the resistance ratio K2 of the second resistor R21 to the second voltage divider resistor R22, satisfy the following condition: This ensures that when power is applied, audio chip 1 is powered on first and then enabled.

[0025] Specifically, in the circuit structure of this invention, when the system is powered on, the motherboard power supply P3V3 supplies power, the gate of PMOS transistor Q59 is at a high level, PMOS transistor Q59 is cut off, and delay comparator U41 is powered on. Due to the presence of capacitor C1, the voltage of the audio power supply node slowly rises at a certain slope to the minimum operating voltage of audio chip 1, thus powering on audio chip 1. Up to this point, the voltage at the non-inverting input of delay comparator U41 is lower than the voltage at the inverting input, and the output of delay comparator U41 maintains a low-level signal to the enable pin AUDIO_EN of audio chip 1, keeping audio chip 1 in a turned-off state. Until the voltage of the audio power supply node continues to rise until the voltage at the non-inverting input of delay comparator U41 rises higher than the voltage at the inverting input, the output of delay comparator U41 flips, outputting a high-level signal to the enable pin AUDIO_EN of audio chip 1, and audio chip 1 begins to work. That is, audio chip 1 is powered on first and then enabled, thus avoiding power-on pop-up sounds.

[0026] In this invention, when the system loses power, the motherboard power supply P3V3 stops supplying power, the delay comparator U41 is de-energized, and the gate of PMOS transistor Q59 is quickly pulled low due to the presence of the fourth resistor R4 and the fifth resistor R5, turning on PMOS transistor Q59. This pulls the enable pin AUDIO_EN of audio chip 1 to ground, turning off audio chip 1. Meanwhile, the voltage at the audio power supply node slowly decreases due to the discharge of capacitor C1. Therefore, the power-off of audio chip 1 occurs after the enable pin of the audio chip is turned off, thus preventing power-off pop-up sounds.

[0027] This invention's pop-up noise cancellation circuit utilizes a rapid power-down shutdown circuit to forcibly pull down the enable pin of the audio chip the instant the power supply drops off the motherboard, completely eliminating power-down pop-up noise. A delay comparator ensures that the audio chip's supply voltage rises above its minimum operating voltage before allowing the enable pin to go high, thus eliminating power-on pop-up noise. This invention's pop-up noise cancellation circuit achieves power-on / power-down pop-up noise cancellation through hardware, enabling fast and reliable control without relying on CPU or EC control chips. It does not require real-time voltage monitoring, does not occupy control chip resources, and can reliably operate in any power-down scenario.

[0028] Preferably, the motherboard power supply P3V3 is connected in series with capacitor C1 after passing through the first ferrite bead L1, and the audio power supply node is connected between the first ferrite bead L1 and capacitor C1. The first ferrite bead L1 can provide high impedance isolation between the audio power supply node and the motherboard power supply P3V3, suppress bidirectional coupling of high-frequency noise, and ensure the cleanliness of the audio chip power supply and the system EMC performance.

[0029] Optionally, the audio power supply node is connected to the audio chip 1 via the second ferrite bead L2. The second ferrite bead L2 can act as a high-frequency power filter, and its quality can be selected based on the power supply P3V3 on the motherboard.

[0030] Preferably, in the Figure 1-4 In the illustrated embodiment, the motherboard power supply P3V3 is a 3.3V power supply, the audio chip 1 operates at a voltage of 2.7V~3.6V, the capacitor C1 has a capacitance of 10 µF, the resistance ratio K1 of the first resistor R11 to the first voltage divider resistor R12 is 1:1, and the resistance ratio K2 of the second resistor R21 to the second voltage divider resistor R22 is 4:3. At this time, .

[0031] When the motherboard power supply P3V3 in this embodiment is powered on, the voltage V at the inverting input of the delay comparator U41 is... U41- =V P3V3 / (K2+1)=3.3V×3 / 7≈1.4143V, the voltage V at the non-inverting input of the delay comparator U41 U41+ =V VCC_AUDIO / (K1+1)=V VCC_AUDIO ×1 / 2. Therefore, the voltage V at the audio power supply node... VCC_AUDIO Rise to V U41- Before twice the voltage (approximately 2.8286V, greater than the minimum operating voltage of audio chip 1, 2.7V), the voltage V at the non-inverting input of the delay comparator U41... U41+ Lower than the inverting input voltage V U41- The output of the delay comparator U41 is low, meaning audio chip 1 is off. This ensures that the enable pin AUDIO_EN of audio chip 1 is pulled high only after the voltage of the audio power supply node rises above the minimum operating voltage of the audio chip, thus eliminating the power-on pop sound. Figure 4 As shown, in this embodiment, the power-on timing is such that the enable pin AUDIO_EN is later than the audio chip 1 (VCC_AUDIO), and the audio chip 1 (VCC_AUDIO) is later than the motherboard power supply P3V3.

[0032] When the motherboard power supply P3V3 in this embodiment fails, the delay comparator U41 is de-energized. Due to the presence of the fourth resistor R4 and the fifth resistor R5, the gate of the PMOS transistor Q59 is rapidly pulled low, turning on Q59. The enable pin AUDIO_EN of audio chip 1 is pulled down to ground, and audio chip 1 is turned off. Simultaneously, due to the discharge of capacitor C1, the voltage at the audio power supply node slowly decreases. Therefore, the power-off of audio chip 1 occurs after the enable pin is turned off, thus preventing power-down pop-up sounds. Figure 4As shown, the power-down sequence is that the motherboard power supply P3V3 is earlier than the enable pin AUDIO_EN of audio chip 1, and the enable pin AUDIO_EN of audio chip 1 is earlier than audio chip 1 (VCC_AUDIO).

[0033] Preferably, in the Figure 1-4 In the embodiment shown, the resistance values ​​of the first resistor R11, the second resistor R21, and the first voltage divider resistor R12 are all 100 kΩ, and the resistance value of the second voltage divider resistor R22 is 75 kΩ.

[0034] Preferably, in the Figure 1-4 In the embodiment shown, the resistance of the third resistor R3 is 10kΩ, the resistance of the fourth resistor R4 is 1kΩ, and the resistance of the fifth resistor R5 is 1.1kΩ.

[0035] Preferably, in the Figure 1-4 In the illustrated embodiment, the impedance values ​​of the first magnetic bead L1 and the second magnetic bead L2 are both 600 Ω.

[0036] Preferably, in the Figure 1-4 In the embodiment shown, the delay comparator U41 is model SGM8743.

[0037] Preferably, in the Figure 1-4 In the embodiment shown, the PMOS transistor Q59 is a BSS84.

[0038] It is understood that the specific component models and values ​​in the circuit of this utility model can be selected according to the motherboard type, audio chip, etc. of the specific applicable electronic device or smart device, and will not be elaborated here.

[0039] This invention's pop-up noise cancellation circuit utilizes a rapid power-down shutdown circuit to forcibly pull down the enable pin of the audio chip the instant the power supply drops off the motherboard, completely eliminating power-down pop-up noise. A delay comparator ensures that the audio chip's supply voltage rises above its minimum operating voltage before allowing the enable pin to go high, thus eliminating power-on pop-up noise. This invention's pop-up noise cancellation circuit achieves power-on / power-down pop-up noise cancellation through hardware, enabling fast and reliable control without relying on CPU or EC control chips. It does not require real-time voltage monitoring, does not occupy control chip resources, and can reliably operate in any power-down scenario.

[0040] As described above, those skilled in the art can make various other corresponding changes and modifications based on the technical solution and concept of this utility model, and all such changes and modifications should fall within the protection scope of the appended claims of this utility model.

Claims

1. A pop noise cancellation circuit, characterized in that, include: Audio chip (1), delay comparator (U41), PMOS transistor (Q59), capacitor (C1), motherboard power supply (P3V3); The motherboard power supply (P3V3) has three circuits: one connected to a capacitor (C1) in series and then grounded; another connected to a second resistor (R21) and a second voltage divider resistor (R22) and then grounded; and the third connected to a fourth resistor (R4) and a fifth resistor (R5) and then grounded. An audio power supply node is connected between the motherboard power supply (P3V3) and the capacitor (C1). This audio power supply node is connected to the audio chip (1) to supply power to it. The audio power supply node is grounded via a first resistor (R11) and a first voltage divider resistor (R12). The second resistor (R21) and the second voltage divider resistor (R22) are connected to the inverting input of the delay comparator (U41). At the input end, the first resistor (R11) and the first voltage divider resistor (R12) are connected to the non-inverting input of the delay comparator (U41); the positive power supply of the delay comparator (U41) is connected to the motherboard power supply (P3V3), the negative power supply is grounded, and one output is connected to the enable pin (AUDIO_EN) of the audio chip (1), and the other is grounded through the third resistor (R3); the fourth resistor (R4) and the fifth resistor (R5) are connected to the gate of the PMOS transistor (Q59), the source of the PMOS transistor (Q59) is grounded, and the drain is connected to the enable pin (AUDIO_EN) of the audio chip (1); The minimum operating voltage of the audio chip (1), the voltage of the motherboard power supply (P3V3), the ratio of the resistance of the first resistor (R11) to the resistance of the first voltage divider resistor (R12), and the ratio of the resistance of the second resistor (R21) to the resistance of the second voltage divider resistor (R22) must satisfy the following conditions: , Among them, V AUDIO-MIN V is the minimum operating voltage of the audio chip (1). P3V3 K1 is the voltage of the motherboard power supply (P3V3), K2 is the ratio of the resistance of the first resistor (R11) to the resistance of the first voltage divider resistor (R12), and K2 is the ratio of the resistance of the second resistor (R21) to the resistance of the second voltage divider resistor (R22).

2. The pop noise cancellation circuit as described in claim 1, characterized in that, The motherboard power supply (P3V3) is connected in series with a capacitor (C1) after passing through the first ferrite bead (L1). The audio power supply node is connected between the first ferrite bead (L1) and the capacitor (C1).

3. The pop noise cancellation circuit as described in claim 1, characterized in that, The audio power supply node is connected to the audio chip (1) via the second ferrite bead (L2).

4. The pop noise cancellation circuit as described in claim 1, characterized in that, The motherboard power supply (P3V3) is 3.3V, the audio chip (1) operates at a voltage of 2.7V~3.6V, the capacitor (C1) has a capacitance of 10 µF, the ratio of the resistance of the first resistor (R11) to the resistance of the first voltage divider resistor (R12) is 1:1, and the ratio of the resistance of the second resistor (R21) to the resistance of the second voltage divider resistor (R22) is 4:

3.

5. The pop noise cancellation circuit as described in claim 4, characterized in that, The resistance values ​​of the first resistor (R11), the second resistor (R21), and the first voltage divider resistor (R12) are all 100kΩ, and the resistance value of the second voltage divider resistor (R22) is 75kΩ.

6. The pop noise cancellation circuit as described in claim 1, characterized in that, The third resistor (R3) has a resistance of 10 kΩ, the fourth resistor (R4) has a resistance of 1 kΩ, and the fifth resistor (R5) has a resistance of 1.1 kΩ.

7. The pop noise cancellation circuit as described in claim 2, characterized in that, The impedance of the first magnetic bead (L1) is 600Ω.

8. The pop noise cancellation circuit as described in claim 3, characterized in that, The impedance of the second magnetic bead (L2) is 600Ω.

9. The pop noise cancellation circuit as described in claim 1, characterized in that, The delay comparator (U41) is model SGM8743.

10. The pop noise cancellation circuit as described in claim 1, characterized in that, The PMOS transistor (Q59) is model BSS84.

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