Circuit board, circuit board assembly, and electronic device

Abstract

The application provides a circuit board, a circuit board assembly and an electronic device, and relates to the technical field of electronic products. The circuit board comprises a circuit board body, a pad array and a connection wire group. The circuit board body comprises a first surface, and the pad array is arranged on the first surface. The pad array is used for connecting electronic devices, and comprises a plurality of array-arranged pads. The connection wire group is arranged on the circuit board body, and comprises a plurality of wires. The plurality of wires are respectively connected with the plurality of pads. The plurality of pads comprises a first pad. The connection wire corresponding to the first pad comprises a first branch wire and a second branch wire in parallel. The projection of the first branch wire and the second branch wire on the first surface is a first projection. The projection of the plurality of pads on the first surface is arranged at intervals with the first projection. The first projection surrounds the projection of at least one pad, except the first pad, on the first surface.

Description

Technical Field

[0001] This application relates to the field of electronic product technology, and more particularly to a circuit board, circuit board assembly, and electronic device. Background Technology

[0002] With the improvement of artificial intelligence (AI) computing power, electronic devices have placed higher demands on the density and performance of circuit boards (PCBs), which has led to a corresponding increase in the wiring density on the PCBs. To meet the needs of device interconnection, the wiring on the PCB needs to extend to the pad array area under the chips and other devices.

[0003] However, the spacing between pads in the pad array area is limited, which restricts the trace width within that area, causing a difference in trace width between this area and other areas. This difference in trace width alters the impedance characteristics of the traces, causing impedance abrupt changes, which in turn affects the transmission of high-speed signals. Utility Model Content

[0004] This application provides a circuit board, a circuit board assembly, and an electronic device, aiming to solve the technical problem that impedance abrupt changes can occur due to inconsistent trace widths in different areas of a circuit board.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, this application provides a circuit board, which includes a circuit board body, a pad array, and a connection trace group. The circuit board body includes a first surface, and the pad array is disposed on the first surface. The pad array is used to connect electronic devices, and the pad array includes multiple pads arranged in an array. The connection trace group is disposed on the circuit board body and includes multiple traces, which are respectively connected to multiple pads. The multiple pads include a first pad, and the connection traces corresponding to the first pads include parallel first branch traces and second branch traces. The projections of the first branch traces and second branch traces on the first surface are called first projections. The projections of the multiple pads on the first surface are spaced apart from the first projections, and the first projections are arranged around the projections of at least one pad other than the first pad on the first surface.

[0007] In this application, the traces connected to the same pad (first pad) are split into two parallel branch traces and a second branch trace. The effective cross-sectional area of ​​the branch sections of the traces connected to the pads is increased in the first and second branch traces. The parallel structure reduces the inductance L per unit length, while the change in capacitance C is relatively small, resulting in a lower overall impedance. Therefore, this application solves the problem of excessively high impedance caused by insufficient trace width in the narrow space between pads on the circuit board. Thus, even if each branch trace is relatively thin (meeting the pad gap limit), the target impedance can still be achieved through parallel connection.

[0008] Meanwhile, the first branch trace and the second branch trace in this application are routed around the periphery of other pads. On the one hand, the first branch trace and the second branch trace are not concentrated in the same gap between adjacent pads, avoiding ineffective expansion of branch lines. On the other hand, by routing the first branch trace and the second branch trace along the periphery of other pads, the adjacent spacing space between pads that was originally unused or poorly routed is utilized. Without changing the overall spacing of the pad array or affecting the device soldering and circuit board processing technology, routing space is provided for the first branch trace and the second branch trace, ensuring the rationality of the line width and the structural stability of the first branch trace and the second branch trace.

[0009] In this application, even if a single branch trace is narrower due to the need to adapt to the pad spacing, the equivalent impedance of two branches connected in parallel can still reach the preset target impedance, without having to forcibly widen the single trace to meet the impedance requirements and cause a conflict with the pad spacing limit.

[0010] One possible implementation is that the circuit board includes multiple stacked and alternately arranged insulating dielectric layers and multiple metal layers, including a first metal layer, at least a portion of which forms a first branch trace and a second branch trace. The first and second branch traces are formed by the first metal layer, ensuring that the substrate characteristics (such as conductivity and parasitic parameters) of the first and second branch traces are consistent, avoiding impedance imbalance between branches caused by differences in the materials of different metal layers. Simultaneously, wiring within the same metal layer reduces the use of interlayer vias (vias easily introduce additional parasitic inductance and capacitance), ensuring the stability of the inductance (L) and capacitance (C) parameters of the parallel structure of the first and second branch traces, so that the equivalent impedance can match the target value.

[0011] Another possible implementation involves a circuit board comprising multiple stacked and alternately arranged insulating dielectric layers and multiple metal layers. The metal layers include a first metal layer and a second metal layer. At least a portion of the first metal layer forms a first branch trace, and at least a portion of the second metal layer forms a second branch trace. Adjacent traces within the same metal layer are prone to crosstalk due to electromagnetic field coupling, especially in high-speed signal transmission scenarios, where crosstalk can lead to signal distortion. However, the first and second branch traces belong to different metal layers, isolated by an insulating dielectric layer, reducing signal crosstalk between them. Furthermore, as a parallel structure, the first and second branch traces transmit signals synchronously through both traces. Reduced crosstalk ensures signal consistency between the first and second branch traces, avoiding impedance fluctuations caused by crosstalk and improving overall signal transmission stability.

[0012] Another possible implementation involves a metallized via in the insulating layer between the first and second metal layers. The first pad is connected to the metallized via through the first metal layer, and the first branch trace and the second branch trace are connected in parallel to the metallized via. The metallized via can serve as a "common access point" for the first and second branch traces, allowing the signal current output from the first pad to be evenly distributed to the first and second branch traces through the via. In pad array areas, the pads are small and have narrow spacing. If two metal layers need to be connected in parallel to the pads simultaneously, two metal connection points need to be set within the pad area. This is easily limited by the physical size of the pads, leading to overlapping connection points or insufficient spacing. By indirectly achieving the parallel connection of the first and second branch traces through metallized vias, the pads only need to handle a single-layer connection with the first metal layer, which can match the size and spacing requirements of the pads and reduce the processing difficulty.

[0013] Another possible implementation is that the projection of at least a portion of the first branch trace on the first surface coincides with the projection of at least a portion of the second branch trace on the first surface. Therefore, the first and second branch traces can maintain consistency in length and path shape, and when they belong to different metal layers, the thickness of the interlayer insulating dielectric layer is uniform, resulting in smaller differences in parasitic parameters (such as inductance and capacitance) between the first and second branch traces.

[0014] Another possible implementation is that at least a portion of the first branch trace extends in the same direction as at least a portion of the second branch trace. The first and second branch traces extend in the same direction, and their transmission path lengths in corresponding sections are essentially matched, avoiding signal delay differences caused by variations in their routing. The first and second branch traces are routed in a quasi-differential configuration, exhibiting symmetrical electromagnetic field distribution: when external interference signals are present, the first and second branch traces synchronously induce interference, and the interference signals can cancel each other out in the parallel loop, reducing the impact of external interference on the signals within the first and second branch traces, while also reducing internal crosstalk generated by electromagnetic field coupling within the first and second branch traces themselves.

[0015] In another possible implementation, the circuit board body also includes a wiring area, the projection of the wiring area on the first surface is spaced apart from the projection of the pad array on the first surface, the first pad is connected to the first trace, the first trace includes a connected bus, a first branch trace and a second branch trace, the bus is located in the wiring area, and the impedance value formed by the first branch trace and the second branch trace in parallel is equal to the impedance value formed by the bus, so that the signal can be stably transmitted between different areas.

[0016] Another possible implementation is to have the same trace width for both the first and second branches, which facilitates processing.

[0017] Another possible implementation is that the trace width of the first branch and / or the second branch is less than or equal to 4mil, which can be adapted to the pad gap.

[0018] Another possible implementation is to have an array spacing of less than or equal to 0.8 mm for the pad array to meet the connection requirements between the circuit board and electronic components.

[0019] Secondly, this application provides a circuit board assembly, which includes electronic components and a circuit board in any of the above possible implementations, wherein the electronic components are connected to a pad array on the circuit board.

[0020] Thirdly, this application provides an electronic device, which includes a housing and the circuit board assembly mentioned in the second aspect above, with the circuit board assembly disposed within the housing.

[0021] The technical effects of any of the design methods in the second to third aspects are the same as those of the different design methods in the first aspect. Attached Figure Description

[0022] Figure 1 This application provides schematic diagrams of the circuit board structure for some embodiments.

[0023] Figure 2 According to Figure 1 The diagram shows the structure of the pad array on the circuit board.

[0024] Figure 3 for Figure 2 The diagram shows the first type of trace layout on the pad array.

[0025] Figure 4 for Figure 2 The diagram shows the second routing layout on the pad array.

[0026] Figure 5 for Figure 2 The diagram shows the third routing layout on the pad array.

[0027] Figure 6 for Figure 2 The diagram shows the fourth routing layout on the pad array.

[0028] Figure 7 One of the simulation comparison diagrams of the circuit board provided in some embodiments of this application;

[0029] Figure 8 A second simulation comparison diagram of the circuit board provided in some embodiments of this application;

[0030] Figure 9 This is one of the simulation diagrams of circuit boards in related technologies;

[0031] Figure 10 This is one of the simulation diagrams of the circuit board provided in some embodiments of this application;

[0032] Figure 11 This is the second simulation diagram of a circuit board in related technologies;

[0033] Figure 12 This is the second simulation diagram of a circuit board provided in some embodiments of this application;

[0034] Figure 13 This is the third simulation diagram of a circuit board in related technologies;

[0035] Figure 14 This is the third simulation diagram of a circuit board provided for some embodiments of this application.

[0036] Figure label:

[0037] 100. Circuit board; 101. Pad array; 1011. First pad; 102. First branch trace; 103. Second branch trace; 104. Bus; S1. BGA area; S2. Non-BGA area. Detailed Implementation

[0038] First, this application introduces the relevant technical terms involved:

[0039] Printed Circuit Board (PCB): An important electronic component in electronic devices, serving as the electrical connection carrier for electronic components.

[0040] Pad array: A pad array is a collection of pads arranged in a certain pattern (such as a grid) on a circuit board. These pads are used to achieve electrical connections and mechanical fixation between the circuit board and electronic components (such as chips, connectors, etc.). Components are connected to corresponding pads through pins or solder points, forming current paths.

[0041] Solder pad (English name: Land Pad, abbreviation: pad): A solder pad is a metal area on a circuit board used to achieve electrical connections. Its main function is to connect the internal traces of the circuit board to the pins or solder joints of external electronic devices (such as chips, resistors, connectors, etc.), provide reliable contact points for current transmission, and also play a role in fixing the mechanical support of the device.

[0042] Metal Layer: A metal layer is a conductive layer on a circuit board used for routing traces. It is typically made of copper and formed through etching processes to create traces with specific paths, serving functions such as signal transmission or power / grounding. A circuit board may contain multiple metal layers, separated by insulating media, which can significantly increase wiring density.

[0043] Insulating Layer (English name: Insulating Layer / Dielectric Layer): The insulating layer is a non-conductive material layer that separates different metal layers in a circuit board. It is usually made of composite materials such as resin and glass fiber. Its main function is to prevent short circuits between adjacent metal layers, while also providing mechanical support for the circuit board. Its dielectric constant and other properties also affect the impedance and speed of signal transmission.

[0044] Plated Through Hole (PTH): A plated through hole is a hole in a circuit board that penetrates multiple layers of insulating media. The inner wall of the hole is covered with metal (usually copper) through an electroplating process to achieve electrical connection between different metal layers. It allows current to pass between stacked metal layers and is a key structure for realizing three-dimensional wiring on a circuit board.

[0045] Ball Grid Array (BGA): A ball grid array is a type of electronic device package in which the bottom is covered with metal balls (solder balls) arranged in an array pattern. These solder balls are connected to corresponding pads on the circuit board by soldering. Compared to conventional leaded packages, BGAs can accommodate more pins and offer superior heat dissipation and electrical performance, making them widely used in high-density, high-performance chips (such as processors and memory).

[0046] BGA chips: Chips packaged using a ball grid array (BGA) are collectively referred to as BGA chips. These chips are connected to the PCB via an array of solder balls on the bottom and are suitable for scenarios with a large number of pins and high operating frequencies (such as AI chips and high-performance processors), meeting the requirements of high-speed signal transmission and high-density integration.

[0047] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0048] Hereinafter, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature.

[0049] Furthermore, in the embodiments of this application, directional terms such as "upper," "lower," "horizontal," and "vertical" are defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0050] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, an electrical connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.

[0051] In some embodiments, this application provides an electronic device including a housing and a circuit board assembly disposed within the housing, the housing providing protection for the circuit board assembly.

[0052] Specifically, the electronic device can be a portable electronic device or other suitable electronic device. For example, the electronic device can be a mobile phone, tablet personal computer, laptop computer, in-vehicle equipment, wearable device, augmented reality (AR) glasses, AR headset, virtual reality (VR) glasses, or VR headset, etc.

[0053] It should be noted that this application does not limit the specific functions ultimately achieved by the circuit board assembly, the specific component models integrated, or the application fields.

[0054] For example, the circuit board assembly of this application can be applied to AI computing scenarios, such as carrying AI chips, high-speed storage devices, etc.

[0055] As another example, the circuit board assembly can be used in AI computing power related devices (such as AI servers, computing cards, etc.).

[0056] In some embodiments, see Figure 1 The circuit board assembly in this application includes a circuit board 100 and electronic components. The electronic components are connected to the circuit board 100. The circuit board 100 provides basic wiring and connection carrier. The electronic components (such as chips, resistors, capacitors, etc.) can work together to achieve specific functions (such as data operation, signal processing, and power management in AI computing scenarios) by connecting to the circuit board 100.

[0057] For example, the electronic components are connected to the circuit board 100 by soldering.

[0058] Another example is that electronic components are connected to the circuit board 100 via surface mount technology (SMT).

[0059] In some embodiments, the electronic components in this application are connected to the circuit board 100 via surface mounting. Specifically, the circuit board 100 includes a circuit board 100 body, the circuit board 100 body includes a first surface, the circuit board 100 also includes a pad array 101, the pad array 101 is disposed on the first surface, the pad array 101 is used to connect electronic components, and the pad array 101 includes a plurality of pads arranged in an array.

[0060] For example, pad array 101 is a rectangular array. For yet another example, the pad array is a circular array.

[0061] It should be noted that this application does not limit the shape of a single pad.

[0062] The long leads of electronic components can be directly connected to the pad array 101 on the first surface. The pads can match the pin distribution requirements of surface mount components (such as BGA chips) without the need to reserve additional through-hole space for the component leads.

[0063] For example, the above-mentioned electronic components may be BGA chips, whose bottom solder ball array can match the solder pad array 101 on the first surface of the circuit board 100, and achieve stable connection through surface mount technology, which is suitable for high-density wiring and high-speed signal transmission requirements, especially meeting the requirements for chip integration in scenarios such as AI computing power.

[0064] It should be noted that the selection of electronic components is not limited to BGA chips. Other chips with pins (such as QFP and LGA packages) are also applicable to the technical solution of this application, as long as their pin distribution is compatible with the pad array 101 of the circuit board 100 and can be connected by surface mount technology. This application does not limit the specific packaging form of electronic components.

[0065] For ease of explanation, this application will be further described using BGA chips as electronic components.

[0066] In some embodiments, see Figure 1 and combined Figure 3 The circuit board 100 in this application also includes a connection trace group, a plurality of pads including a first pad 1011, the connection trace group is disposed on the body of the circuit board 100, the connection trace group includes a plurality of traces, the plurality of traces are respectively connected to a plurality of pads, so that the pads are connected to the traces of the circuit board 100 in the non-BGA area S2.

[0067] The connection traces corresponding to the first pad 1011 include a first branch trace 102 and a second branch trace 103 connected in parallel. The projection of the first branch trace 102 and the second branch trace 103 on the first surface is the first projection. The projections of multiple pads on the first surface are spaced apart from the first projection. The first projection surrounds the projection of at least one pad on the first surface other than the first pad 1011.

[0068] In this application, taking the connection between the first pad 1011 and the non-BGA region S2 on the circuit board 100 as an example, after the signal is output from the pin of the first pad 1011, it is first connected to the starting end of the BGA region S1. Within the BGA region S1, the signal is split through the branch structure of the first branch trace 102 and the second branch trace 103. Part of the signal is transmitted through the first branch trace 102, and the other part of the signal is transmitted synchronously through the second branch trace 103. After the signal is transmitted within the BGA region S1 through the dual branches, the first branch trace 102 and the second branch trace 103 converge at the end of the BGA region S1 and finally merge into one trace, which is then connected to the subsequent traces in the non-BGA region S2 of the circuit board 100.

[0069] After the signal is output from the first pad 1011 pin to the BGA area S1, if a single trace is used for transmission, the trace is too wide and may cause spacing conflicts with the surrounding pads. However, after splitting the trace into the first branch trace 102 and the second branch trace 103, the two narrow-width branches can be independently arranged along the pad gaps, avoiding the encroachment on the limited planar space of the BGA area S1, and reducing the problem of uneven trace width caused by space compression of a single trace.

[0070] The array spacing of pad array 101 is smaller than the line width requirement of non-BGA region S2. Therefore, the line width of the trace decreases after entering BGA region S1. In this application, the effective cross-sectional area of ​​the branch sections corresponding to the first branch trace 102 and the second branch trace 103 of the trace connected to the first pad 1011 is increased. The parallel structure reduces the inductance L per unit length, while the change in capacitance C is relatively small, resulting in a lower overall impedance. Even if each branch trace is thin (meeting the pad spacing limit), the target impedance can still be achieved after the first branch trace 102 and the second branch trace 103 are connected in parallel.

[0071] Meanwhile, the first branch trace 102 and the second branch trace 103 in this application are routed around the periphery of other pads. On the one hand, the first branch trace 102 and the second branch trace 103 are not concentrated in the same gap between adjacent pads, thus avoiding ineffective expansion of branch lines. On the other hand, by routing the first branch trace 102 and the second branch trace 103 along the periphery of other pads, the adjacent spacing space between pads that was originally unused or poorly routed is utilized. Without changing the overall spacing of the pad array 101 or affecting the device soldering and circuit board 100 processing technology, the routing space for the first branch trace 102 and the second branch trace 103 is provided, ensuring the rationality of the line width and the structural stability of the first branch trace 102 and the second branch trace 103.

[0072] In this application, even if a single branch trace is narrower due to the need to adapt to the pad spacing, the equivalent impedance of two branches connected in parallel can still reach the preset target impedance, without having to forcibly widen the single trace to meet the impedance requirements and cause a conflict with the pad spacing limit.

[0073] It should be noted that this application does not limit the specific location of the first pad 1011, and similarly does not limit the location of at least one other pad in the pad array 101 besides the first pad 1011.

[0074] For example, the first projection may be disposed around the periphery of a single pad.

[0075] Another example is shown below. Figure 2 and combined Figures 3-6 Along the row or column direction of the pad array 101, the first projection can be arranged around the periphery of a column or row of pad groups—it can be a pad group in the same column or row as the first pad 1011, or it can be a pad group in other columns or rows, and this application does not limit it in this regard.

[0076] In this application, any of the above-mentioned surround methods can also be combined, and this application does not limit this.

[0077] In some embodiments, see Figure 3 The circuit board 100 includes a plurality of insulating dielectric layers and a plurality of metal layers stacked and alternately arranged. The plurality of metal layers include a first metal layer, at least a portion of which forms a first branch trace 102 and a second branch trace 103.

[0078] The first metal layer forms the first branch trace 102 and the second branch trace 103. Both are located in the same metal layer, which makes the substrate characteristics (such as conductivity and parasitic parameters) of the first branch trace 102 and the second branch trace 103 consistent, thus avoiding the impedance imbalance between branches caused by the difference in the materials of different metal layers.

[0079] Meanwhile, wiring within the same metal layer can reduce the use of interlayer vias (vias easily introduce additional parasitic inductance and capacitance), ensuring the stability of the inductance (L) and capacitance (C) parameters of the parallel structure of the first branch trace 102 and the second branch trace 103, so that the equivalent impedance can match the target value.

[0080] In some embodiments, see Figure 3 The circuit board 100 includes a plurality of insulating dielectric layers and a plurality of metal layers stacked and alternately arranged. The plurality of metal layers include a first metal layer and a second metal layer. At least a portion of the first metal layer forms a first branch trace 102, and at least a portion of the second metal layer forms a second branch trace 103.

[0081] In this application, the first branch trace 102 and the second branch trace 103 belong to different metal layers, and the layers are isolated by an insulating dielectric layer, which reduces the signal crosstalk between the first branch trace 102 and the second branch trace 103.

[0082] Meanwhile, the first branch trace 102 and the second branch trace 103 are connected in parallel, and the signal is transmitted synchronously in the two traces. The reduction of crosstalk can ensure the consistency of the signal between the first branch trace 102 and the second branch trace 103, avoid impedance fluctuations caused by crosstalk, and improve the overall signal transmission stability.

[0083] For example, the first metal layer and the second metal layer are two adjacent metal layers.

[0084] As another example, multiple insulating layers and metal layers may be spaced between the first metal layer and the second metal layer.

[0085] In other embodiments, at least a portion of the first metal layer forms a first branch trace 102, and at least a portion of the second metal layer forms a second branch trace 103. When the first branch trace 102 and the second branch trace 103 converge at the end of the BGA region S1, they can be electrically connected by setting a metallized via again.

[0086] In some embodiments, see Figure 3 When the first branch trace 102 and the second branch trace 103 converge at the end of the BGA region S1, they can converge in the third metal layer. That is, the traces in the non-BFA region connected by the first branch trace 102 and the second branch trace 103 can be in different metal layers from the first branch trace 102 and the second branch trace 103.

[0087] At this point, the first branch trace 102 and the second branch trace 103 must satisfy Skew=|(P+Via_P)-(N+Via_N)|≤1ps.

[0088] Where Skew is the total transmission delay difference between the first branch trace 102 and the second branch trace 103, in picoseconds (ps).

[0089] For example, P refers to the first branch trace 102, and Via_P refers to the via delay that the P line passes through. The via will introduce additional delay due to parasitic capacitance and inductance, which needs to be included in the total delay separately.

[0090] As another example, N refers to the second branch trace 103, and Via_N refers to the via delay that the N line passes through. Vias will introduce additional delay due to parasitic capacitance and inductance, which needs to be included in the total delay separately.

[0091] The above requirement means that the absolute difference between the total delay of the P line (path delay + via delay) and the total delay of the N line (path delay + via delay) must be ≤ 1 picosecond (ps) to ensure the reliability of data transmission.

[0092] In some embodiments, see Figure 3 The insulating layer between the first metal layer and the second metal layer is provided with a metallized via. The first pad 1011 is connected to the metallized via through the first metal layer. The first branch trace 102 and the second branch trace 103 are connected in parallel to the metallized via.

[0093] Metallized vias can serve as a "common access point" for the first branch trace 102 and the second branch trace 103, enabling the signal current output from the first pad 1011 to be evenly distributed to the first branch trace 102 and the second branch trace 103 through the vias.

[0094] The pads in the pad array 101 area are small in size and narrow in spacing. If the pads need to be connected to two metal layers in parallel at the same time, two metal connection points need to be set in the pad area. This is easily limited by the physical size of the pads, resulting in overlapping connection points or insufficient spacing. The first branch trace 102 and the second branch trace 103 are indirectly connected in parallel through metallized vias. The pads only need to be connected to a single layer of the first metal layer, which can match the size and spacing requirements of the pads and reduce the processing difficulty.

[0095] In some embodiments, at least a portion of the projection of the first branch trace 102 onto the first surface coincides with at least a portion of the projection of the second branch trace 103 onto the first surface.

[0096] Therefore, the first branch trace 102 and the second branch trace 103 can maintain the same length and path shape, and when they belong to different metal layers, the thickness of the interlayer insulating dielectric layer is uniform, and the parasitic parameters (such as inductance and capacitance) of the first branch trace 102 and the second branch trace 103 are less different.

[0097] For example, the projected overlapping portion is the middle section of the first branch trace 102 and the middle section of the second branch trace 103.

[0098] In some embodiments, see Figure 3 At least a portion of the first branch routing 102 extends in the same direction as at least a portion of the second branch routing 103.

[0099] It should be noted that the above-mentioned extension direction can be either a straight line or a curve: when it is a straight line, the first branch line 102 and the second branch line 103 extend in parallel in the same direction; when it is a curve, the two maintain the same curvature trend in the corresponding sections, and in the area where the two extension directions are consistent, they are arranged at equal intervals.

[0100] Consistent extension direction means that in a certain section of the BGA region S1 (such as a part of the path between the branch point and the convergence point), the overall direction of the first branch trace 102 and the second branch trace 103 is parallel or coincident. For example, the first branch trace 102 and the second branch trace 103 extend in parallel in the horizontal direction in the same plane, or maintain the same direction in the vertical direction (three-dimensional space) in different metal layers.

[0101] The transmission path lengths of the first branch trace 102 and the second branch trace 103 are basically matched in their corresponding sections, avoiding signal delay differences caused by routing differences. In the above-described trace structure, this application replicates the structural features of differential traces, making the first branch trace 102 and the second branch trace 103 traced in a quasi-differential manner, with symmetrical electromagnetic field distribution: when there is external interference signal, the first branch trace 102 and the second branch trace 103 will synchronously induce interference, and the interference signals can cancel each other out in the parallel loop, thereby reducing the impact of external interference on the signals within the first branch trace 102 and the second branch trace 103, while also reducing the internal crosstalk generated by electromagnetic field coupling within the first branch trace 102 and the second branch trace 103 themselves.

[0102] In some embodiments, see Figure 1 and combined Figure 3 The circuit board body also includes a wiring area (i.e., non-BGA area S2). The projection of the wiring area on the first surface is spaced apart from the projection of the pad array 101 on the first surface. The first pad 1011 is connected to the first trace. The first trace includes a connected bus 104, a first branch trace 102, and a second branch trace 103. The bus 104 is located in the wiring area. The impedance value formed by the first branch trace 102 and the second branch trace 103 in parallel is equal to the impedance value formed by the bus.

[0103] The impedance of the first branch trace 102 and the second branch trace 103 connected in parallel is equal to the impedance of the bus 104, which allows the signal to be transmitted stably from the bus to the branch, avoids signal reflection caused by impedance changes, and reduces signal interference.

[0104] In some embodiments, see Figure 3 The line width of the first branch trace 102 is the same as the line width of the second branch trace 103.

[0105] Z0 is the target impedance (i.e., the line width of the non-BGA region S2 trace), Zp and Zn are the impedances of the first branch trace 102 and the second branch trace 103, respectively. Thus, the line width of the first branch trace 102 is the same as the line width of the second branch trace 103, and their impedances are the same. Therefore, Z0 = Zp / 2 = Zn / 2, so that the overall impedance of the signal remains consistent during transmission.

[0106] In addition, through the above settings, this application can suppress the impedance fluctuation deviation to within 10%, and even if there is a slight discontinuity, the reflected energy is small enough, and the consistent line width of both facilitates processing and reduces the production cost of the circuit board 100.

[0107] In some embodiments, see Figure 3 The width of the first branch trace 102 is less than or equal to 4mil, which can be adapted to the pad gap.

[0108] In some embodiments, see Figure 3 The second branch trace 103 has a trace width of less than or equal to 4mil, which can be adapted to the pad gap.

[0109] In some embodiments, see Figure 2 The array spacing of the pad array 101 is less than or equal to 0.8 mm to meet the connection requirements between the circuit board 100 and electronic components.

[0110] In some embodiments, see Figure 7 and Figure 8 , Figure 7 and Figure 8 This paper compares simulation data of the proposed circuit board 100 structure, a conventional circuit board 100 structure, and ideal conditions for insertion loss (IL) and return loss (RL).

[0111] in Figure 7 Simulation diagram (a) and Figure 8 The simulation diagram (a) in the figure shows the simulation diagram of the ideal insertion loss (IL) and return loss (RL). Figure 7 Simulation diagram (b) and Figure 8 Simulation diagram (b) shows the simulation results of insertion loss (IL) and return loss (RL) of a conventional circuit board 100 structure. Figure 7 Simulation diagram (c) and Figure 8 Simulation diagram (c) in the figure shows the simulation results of insertion loss (IL) and return loss (RL) of this application.

[0112] As can be seen, when the circuit board 100 in this application transmits signals, compared with the conventional circuit board 100 structure, the signal can be transmitted almost without loss under ideal conditions.

[0113] In some embodiments, see Figure 9 and Figure 10 , Figure 9 The impedance simulation results are for a standard circuit board 100. Figure 10 The impedance simulation results of the circuit board 100 in this embodiment of the application are shown. Taking a target impedance of 40 ohms as an example, it can be seen that the simulation curve of this application is closer to the target impedance.

[0114] In some embodiments, see Figure 11 and Figure 12 , Figure 11 The graph shows the insertion loss simulation data for a standard 100-type circuit board. Figure 12 This is a simulation data diagram of the insertion loss of the circuit board 100 in the embodiment of this application.

[0115] It can be seen that the insertion loss curve of the circuit board 100 in this application is closer to 0, and the signal transmission loss is low.

[0116] In some embodiments, see Figure 13 and Figure 14 , Figure 13 This is a simulation data graph of the return loss of a conventional 100-type circuit board. Figure 14 This is a simulation data diagram of the return loss of the circuit board 100 in an embodiment of this application.

[0117] It can be seen that the return loss curve of the circuit board 100 in this application is closer to 0, and the signal transmission loss is low.

[0118] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0119] The above embodiments only illustrate several implementation methods of this utility model, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.

Claims

1. A circuit board, characterized in that, include: The circuit board body includes a first surface; A pad array is disposed on the first surface, the pad array being used to connect electronic devices, the pad array comprising a plurality of pads arranged in an array; A connecting trace group is provided on the circuit board body. The connecting trace group includes multiple traces, and the multiple traces are respectively connected to multiple pads. The plurality of pads includes a first pad, and the connection traces corresponding to the first pad include a first branch trace and a second branch trace connected in parallel. The projections of the first branch trace and the second branch trace on the first surface are a first projection. The projections of the plurality of pads on the first surface are spaced apart from the first projection. The first projection is arranged around the projection of at least one of the plurality of pads other than the first pad on the first surface.

2. The circuit board according to claim 1, characterized in that, The circuit board includes multiple insulating dielectric layers and multiple metal layers stacked and alternately arranged, the multiple metal layers including a first metal layer, at least a portion of the first metal layer forming a first branch trace and a second branch trace.

3. The circuit board according to claim 1, characterized in that, The circuit board includes multiple insulating dielectric layers and multiple metal layers stacked and alternately arranged. The multiple metal layers include a first metal layer and a second metal layer. At least a portion of the first metal layer forms a first branch trace, and at least a portion of the second metal layer forms a second branch trace.

4. The circuit board according to claim 3, characterized in that, The insulating layer between the first metal layer and the second metal layer is provided with a metallized via. The first pad is connected to the metallized via through the first metal layer. The first branch trace and the second branch trace are connected in parallel to the metallized via.

5. The circuit board according to claim 3, characterized in that, At least a portion of the first branch trace's projection on the first surface coincides with at least a portion of the second branch trace's projection on the first surface.

6. The circuit board according to claim 1, characterized in that, At least a portion of the first branch trace extends in the same direction as at least a portion of the second branch trace.

7. The circuit board according to any one of claims 1-6, characterized in that, The circuit board body further includes a wiring area, the projection of the wiring area on the first surface is spaced apart from the projection of the pad array on the first surface, the first pad is connected to a first trace, the first trace includes a connected bus, a first branch trace and a second branch trace, and the bus is located in the wiring area; The impedance value formed by the first branch trace and the second branch trace connected in parallel is equal to the impedance value formed by the bus.

8. The circuit board according to claim 7, characterized in that, The first branch trace and the second branch trace have the same width.

9. A circuit board assembly, characterized in that, include: The circuit board as described in any one of claims 1-8; Electronic components connected to the pad array.

10. An electronic device, characterized in that, include: The circuit board assembly as described in claim 9; The housing contains the circuit board assembly.

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