A detection device, a connector module and an electronic device

Abstract

The application discloses a detection device, a connector module and electronic equipment, and relates to the technical field of circuits. The detection device comprises a detection circuit and an interface device. The detection circuit is connected with a target pin and at least one measured pin of the interface device. The detection circuit is used for determining the connection state of the interface device and an external device through the at least one measured pin in response to the target pin being grounded. Compared with the related art, the application can accurately identify the connection state of the interface device and the external device through the target pin and the at least one measured pin, avoid the situation that a user misjudges that the electronic equipment where the detection device is located has a fault, and improve the user experience.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a detection device, connector module and electronic equipment. Background Technology

[0002] In related technologies, electronic devices that do not support 3.5mm analog headphones have a low accuracy rate in recognizing events where analog headphones are connected via an adapter, leading users to misjudge the electronic device as damaged and affecting the user experience. Utility Model Content

[0003] In view of this, this application provides a testing device, a connector module, and an electronic device.

[0004] In a first aspect, this application provides a detection device, including: a detection circuit and an interface device;

[0005] The detection circuit is connected to the target pin and at least one pin under test of the interface device, respectively.

[0006] The detection circuit is used to determine the connection status between the interface device and the external device through the at least one tested pin in response to the target pin being grounded.

[0007] Optionally, a controller may also be included;

[0008] The controller is connected to the at least one tested pin via at least one line;

[0009] The controller is used to output a level signal to the at least one tested pin through the at least one line.

[0010] Optionally, the controller is connected to a first tested pin among the at least one tested pins via a first line;

[0011] The controller is connected to the second test pin of the at least one test pin via a second line.

[0012] Optionally, the controller is configured to alternately output high-level signals and low-level signals to the first tested pin via the first line, and / or alternately output high-level signals and low-level signals to the second tested pin via the second line.

[0013] Optionally, the controller is configured to alternately output high-level signals and low-level signals to the first tested pin via the first line, and alternately output high-level signals and low-level signals to the second tested pin via the second line, wherein the level signals output by the controller to the first line and the second line are different at the same time.

[0014] Optionally, the first detection pin of the detection circuit is connected to the target pin;

[0015] The second detection pin of the detection circuit is connected to the first test pin and the second test pin, respectively.

[0016] Optionally, it also includes: resistors;

[0017] The first end of the resistor is connected to the second detection pin, the first test pin, and the second test pin, respectively, and the second end of the resistor is grounded.

[0018] Optionally, the detection circuit is connected to the at least one tested pin via at least one functional pin; the detection circuit is used to output a level signal to the at least one tested pin via the at least one functional pin.

[0019] Optionally, the detection circuit is used to determine the voltage difference between the first tested pin and the second tested pin based on the resistance, and the voltage difference is used to determine the connection status between the interface device and the external device.

[0020] Optionally, the detection circuit is further configured to generate a first instruction signal when the interface device is connected to the external device, the first instruction signal being used to instruct the generation of display information, the display information being used to indicate that the connection of the external device is not supported.

[0021] Secondly, this application provides a connector module, including the detection device described in the first aspect.

[0022] Thirdly, this application provides an electronic device, including the detection device described in the first aspect, or the connector module described in the second aspect.

[0023] By employing the above technical solutions, this application provides a detection device, connector module, and electronic device. Compared with related technologies, this application sets up a detection circuit and an interface device in the detection device. The detection circuit is connected to the target pin and at least one pin under test of the interface device. The detection circuit is used to determine the connection status between the interface device and the external device through at least one pin under test in response to the target pin being grounded. This allows this application to comprehensively determine whether the interface device is connected to an external device when the target pin is grounded, in combination with at least one pin under test. This enables this application to accurately identify the connection status between the interface device and the external device through the target pin and at least one pin under test, avoiding situations where users mistakenly judge that the electronic device containing the detection device is faulty, and improving the user experience.

[0024] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0026] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This illustration shows a schematic diagram of the structure of a detection device provided in an embodiment of this application;

[0028] Figure 2 This illustration shows a schematic diagram of the structure of a detection device provided in an embodiment of this application;

[0029] Figure 3 A schematic diagram illustrating an example provided in an embodiment of this application is shown;

[0030] exist Figure 1 middle:

[0031] 1-Detection circuit, 11-First detection pin, 12-Second detection pin;

[0032] 2-Interface device, 21-Target pin, 22-First pin under test, 23-Second pin under test;

[0033] exist Figure 2 middle:

[0034] 3-Controller, 31-First line, 32-Second line. Detailed Implementation

[0035] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0036] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0037] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0038] The present application will be described in detail below with reference to the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in the embodiments of the present application can be combined with each other.

[0039] The following is combined with Figure 1 This application describes a detection apparatus according to some embodiments.

[0040] This application provides a detection device, such as Figure 1 As shown, it includes: a detection circuit 1 and an interface device 2; the detection circuit 1 is connected to the target pin 21 and at least one pin under test of the interface device 2 respectively; the detection circuit 1 is used to determine the connection status between the interface device 2 and the external device through at least one pin under test in response to the target pin 21 being grounded.

[0041] In this embodiment of the application, the detection circuit 1 can be a chip with detection function. For example, the detection circuit 1 can be a power management chip, a sensor chip, etc. For example, if the electronic device in which the detection circuit 1 is located is a smart terminal device (e.g., a mobile phone, a tablet computer, etc.), the detection circuit 1 can specifically be a power management chip (PMIC).

[0042] In some examples, interface device 2 can be hardware that connects two or more different systems, devices, components or networks and enables communication, data exchange or signal conversion between them; for example, interface device 2 can be a USB interface chip, a Type-C connector, a network card, a graphics card, etc.

[0043] Alternatively, the target pin 21 can be a pin in the interface device 2 used to detect the access device type of the interface device. The detection circuit 1 can determine the device type of the external device connected to the interface device 2 through the target pin 21.

[0044] For example, when the interface device 2 is a Type-C connector, the target pin 21 can be the Configuration Channel (CC) pin in the Type-C connector. The detection circuit 1 can determine the device type of the external device connected to the Type-C connector (i.e., the interface device 2 in this embodiment) through the CC pin (i.e., the target pin 21 in this embodiment).

[0045] In some examples, at least one pin under test can be a pin in interface device 2 that can carry a specific voltage or signal. Through at least one pin under test, the detection circuit 1 can perform voltage detection on interface device 2. For example, at least one pin under test can include, but is not limited to, at least one SBU pin, D+ or D- pin (USB differential pair), ground pin, etc.

[0046] For example, when the interface device 2 is a Type-C connector, at least one pin under test can be at least one SBU pin. The detection circuit 1 can determine whether the interface device 2 is connected to an external device by the voltage status of at least one SBU pin (i.e., at least one pin under test in the embodiments of this application).

[0047] Compared with related technologies, this embodiment sets up a detection circuit and an interface device in the detection device; the detection circuit is connected to the target pin and at least one pin under test of the interface device respectively; the detection circuit is used to determine the connection status between the interface device and the external device through at least one pin under test in response to the target pin being grounded. This embodiment can determine whether the interface device is connected to an external device by combining at least one pin under test when the target pin is grounded. This allows the embodiment to accurately identify the connection status between the interface device and the external device through the target pin and at least one pin under test, avoiding the situation where the user mistakenly judges that the electronic device where the detection device is located is faulty, thus improving the user experience.

[0048] As an optional approach, such as Figure 2 As shown, the detection device in this embodiment also includes a controller 3; the controller 3 is connected to at least one pin under test via at least one line; the controller 3 is used to output a level signal to at least one pin under test via at least one line.

[0049] In the embodiments of this application, the controller 3 may be a hardware, firmware or software component responsible for managing, coordinating and controlling specific functions, devices or data flows; for example, the controller 3 may be a microcontroller (MCU), a microprocessor, a central processing unit (CPU) or the like.

[0050] In some examples, the controller 3 can be connected to at least one tested pin in the interface device 2 via at least one line, and can output a level signal to at least one tested pin via at least one line.

[0051] For example, if controller 3 is connected to 3 pins under test through 2 lines, controller 3 can output level signals to the 3 pins under test through 2 lines; if controller 3 is connected to 2 pins under test through 4 lines, controller 3 can output level signals to the 2 pins under test through 4 lines, and so on. Examples will not be repeated here.

[0052] In some examples, when controller 3 is a CPU and at least one tested pin is at least one SBU pin in a type-c connector (i.e., the interface device in this embodiment), the CPU (i.e., the controller in this embodiment) can be connected to at least one SBU pin (i.e., at least one tested pin in this embodiment) in a type-c connector (i.e., the interface device in this embodiment) via at least one line.

[0053] Optionally, the controller 3 is connected to the first test pin 22 of at least one test pin via the first line 31; the controller 3 is connected to the second test pin 23 of at least one test pin via the second line 32.

[0054] As an alternative, the controller 3 in this embodiment may specifically include two lines, wherein it can be connected to the first tested pin 22 via the first line 31, and can also be connected to the second tested pin 23 via the second line 32.

[0055] In some examples, the first test pin 22 and the second test pin 23 can be pins that carry specific voltages or signals respectively. Through the first test pin 22 and the second test pin 23, the detection circuit 1 can perform voltage detection on the interface device 2.

[0056] For example, when the interface device 2 is a Type-C connector, the first test pin 22 can be the SBU1 pin and the second test pin 23 can be the SBU2 pin. Through the SBU1 pin and the SBU2 pin, the detection circuit 1 can perform voltage detection on the interface device 2.

[0057] In some examples, when the controller 3 is a CPU and at least one tested pin is at least one SBU pin in a Type-C connector (i.e., the interface device in this embodiment), the CPU (i.e., the controller in this embodiment) can connect to the SBU1 pin (i.e., the first tested pin in this embodiment) in the Type-C connector (i.e., the interface device in this embodiment) via the first line 31 and output a level signal to the SBU1 pin (i.e., the first tested pin in this embodiment); the CPU (i.e., the controller in this embodiment) can also connect to the SBU2 pin (i.e., the second tested pin in this embodiment) in the Type-C connector (i.e., the interface device in this embodiment) via the second line 32 and output a level signal to the SBU2 pin (i.e., the second tested pin in this embodiment).

[0058] Optionally, the controller 3 is used to alternately output high-level signals and low-level signals to the first tested pin 22 via the first line 31, and / or to alternately output high-level signals and low-level signals to the second tested pin 23 via the second line 32.

[0059] In this embodiment of the application, the controller 3 can alternately output high-level signals and low-level signals to the first tested pin 22 through the first line 31. For example, the controller 3 can output a high-level signal to the first tested pin 22 through the first line 31 and switch to a low-level signal after a preset time.

[0060] In some examples, the controller 3 can alternately output high-level signals and low-level signals to the second measured pin 23 via the second line 32. For example, the controller 3 can output a high-level signal to the second measured pin 23 via the second line 32 and switch to a low-level signal after a preset time.

[0061] It should be noted that, in this embodiment of the application, a high-level signal and a low-level signal can be alternately output to the first tested pin 22 via the first line 31 to determine whether the interface device is connected to an external device. A high-level signal and a low-level signal can also be alternately output to the second tested pin 23 via the second line 32 to determine whether the interface device is connected to an external device.

[0062] Optionally, the controller 3 is used to alternately output high-level signals and low-level signals to the first tested pin 22 via the first line 31, and to alternately output high-level signals and low-level signals to the second tested pin 23 via the second line 32, wherein the level signals output by the controller 3 to the first line 31 and the second line 32 are different at the same time.

[0063] For example, the controller 3 can output a high-level signal to the first tested pin 22 through the first line 31, and output a low-level signal to the second tested pin 23 through the second line 32. After a preset time, it can output a low-level signal to the first tested pin 22 through the first line 31 and output a high-level signal to the second tested pin 23 through the second line 32.

[0064] For example, the controller 3 can also output a low-level signal to the first tested pin 22 through the first line 31, output a high-level signal to the second tested pin 23 through the second line 32, and after a preset time, output a high-level signal to the first tested pin 22 through the first line 31 and output a low-level signal to the second tested pin 23 through the second line 32.

[0065] It should be noted that when the controller 3 outputs a high-level signal through the first line 31, the controller 3 needs to output a low-level signal through the second line 32; correspondingly, when the controller 3 outputs a low-level signal through the first line 31, the controller 3 needs to output a high-level signal through the second line 32, so as to ensure that the level signals output by the controller 3 to the first line 31 and the second line 32 are different at the same time.

[0066] Optionally, the detection circuit 1 is connected to at least one pin under test via at least one functional pin; the detection circuit 1 is used to output a level signal to at least one pin under test via at least one functional pin.

[0067] It should be noted that the detection circuit in this embodiment can output a level signal to at least one tested pin through at least one functional pin, and determine the connection status between the interface device 2 and the external device through at least one tested pin.

[0068] For example, when the detection circuit 1 is a PMIC chip, at least one functional pin may include, but is not limited to, VOUTx pin, LDOx pin, VREF pin, REF pin, etc. It should be noted that, in this embodiment of the application, at least one functional pin of the PMIC chip can be used to directly supply power to at least one pin under test, thereby detecting the type of external device connected to the interface device.

[0069] Optionally, the first detection pin 11 of the detection circuit 1 is connected to the target pin 21; the second detection pin 12 of the detection circuit 1 is connected to the first test pin 22 and the second test pin 23 respectively.

[0070] In this embodiment of the application, the first detection pin 11 of the detection circuit 1 can be a pin for detecting the target pin 21. By detecting the target pin 21 through the first detection pin 11, the type of external device connected to the interface device can be detected.

[0071] For example, when the interface device 2 is a Type-C connector, the target pin 21 can be the CC pin in the Type-C connector, and the first detection pin 11 can be the CC detection pin. The detection circuit 1 can determine the device type of the external device connected to the Type-C connector (i.e., the target pin 21 in the interface device 2 ...

[0072] For example, when the detection circuit 1 detects that the CC pin (target pin 21 in the interface device 2 in the present application) in the type-c connector (i.e., the CC detection pin (i.e. the first detection pin 11 in the present application embodiment) is 0 ohms, it can be preliminarily determined that the type-c connector (i.e. the interface device 2 in the present application embodiment) is connected to an external device that is not compatible with the type-c connector (i.e. the interface device 2 in the present application embodiment).

[0073] Optionally, the external device is an analog headset with an adapter.

[0074] As an alternative approach, if the external device is an analog headset connected to an adapter, and the CC pin (target pin 21) in the type-c connector (i.e., interface device 2 in this embodiment) is detected to be 0 ohms via the CC detection pin (i.e., the first detection pin 11 in this embodiment), it can be preliminarily determined that the analog headset connected to the adapter is not compatible with the type-c connector (i.e., interface device 2 in this embodiment).

[0075] It should be noted that even when the adapter is connected to the Type-C connector (i.e., interface device 2 in this embodiment) without inserting an analog headset, there may be a situation where the detection CC pin (i.e., target pin 21 in this embodiment) is 0 ohms, which makes it impossible to accurately detect whether an analog headset is connected. Therefore, this embodiment needs to further detect based on at least one tested pin to accurately detect whether the Type-C connector (i.e., interface device 2 in this embodiment) is connected to an analog headset.

[0076] In some examples, the detection circuit 1 in this application embodiment further includes a second detection pin 12, which can be a pin capable of voltage detection; for example, when the detection circuit 1 is a PMIC chip, the second detection pin 12 may include, but is not limited to, an ADC pin, an FB pin, a VSYS or VBAT or VIN monitoring pin, etc.

[0077] As an alternative, when the second detection pin 12 is an ADC pin, the ADC pin (i.e., the second detection pin 12 in this embodiment) can be connected to at least one pin under test respectively; for example, the ADC pin (i.e., the second detection pin 12 in this embodiment) can be connected to the SBU1 pin (i.e., the first pin under test in this embodiment) and the SBU2 pin (i.e., the second pin under test in this embodiment) respectively.

[0078] In this embodiment, the detection circuit 1 can detect the voltage difference between the SBU1 pin (i.e., the first pin under test in this embodiment) and the SBU2 pin (i.e., the second pin under test in this embodiment) through the second detection pin 12.

[0079] Optionally, the first end of resistor R is connected to the second detection pin 12, the first measured pin 22, and the second measured pin 23, respectively, and the second end of resistor R is grounded.

[0080] In this embodiment, the resistor R can be connected to the ADC pin (i.e., the second detection pin 12 in this embodiment), the SBU1 pin (i.e., the first test pin in this embodiment), and the SBU2 pin (i.e., the second test pin in this embodiment), respectively, and the other end of the resistor R can be grounded.

[0081] Optionally, the detection circuit 1 is used to determine the voltage difference between the first tested pin 22 and the second tested pin 23 based on the resistor R. The voltage difference is used to determine the connection status between the interface device 2 and the external device.

[0082] In some examples, the detection circuit 1 can detect the voltage difference between the SBU1 pin (i.e., the first pin under test in this embodiment) and the SBU2 pin (i.e., the second pin under test in this embodiment) through the second detection pin 12, and determine the connection status between the interface device 2 and the external device through the resistor R, the voltage value of the SBU1 pin (i.e., the first pin under test in this embodiment), and the voltage value of the SBU2 pin (i.e., the second pin under test in this embodiment).

[0083] Optionally, the external device is an analog headset with an adapter.

[0084] For example, such as Figure 3 The diagram shown illustrates the connection between the detection device and external equipment. Figure 3 In this circuit, PMIC can be a detection circuit 1, a type-c connector can be an interface device 2, a CPU can be a controller 3, an analog headset with an adapter can be an external device, a CC detection pin can be a first detection pin 11, an ADC can be a second detection pin 12, a CC pin can be a target pin 21, an SBU1 pin can be the voltage value of the first measured pin 22, and an SBU2 pin can be the second measured pin 23.

[0085] For example, based on Figure 3 The content shown (the microphone and adapter 4 are connected in a positive orientation, i.e., the ground wire 43 of adapter 4 is connected to the ground wire 53 of the analog headphones, and the microphone 44 of the adapter is connected to the microphone 54 of the analog headphones) can detect 0 ohms through the CC detection pin (i.e., the first detection pin 11 in this embodiment of the application), and may include, but is not limited to, the following detection scenarios:

[0086] Detection Scenario 1: The CPU (i.e., the controller in this embodiment) outputs a high level to SBU1 (i.e., the first tested pin in this embodiment) through the first line, and outputs a low level to SBU2 (i.e., the second tested pin in this embodiment) through the second line.

[0087] If the Type-C connector (i.e., the interface device 2 in this application embodiment) is connected to an analog headset (i.e., the external device in this application embodiment) with an adapter, the voltage difference between the SBU1 pin (i.e., the first measured pin in this application embodiment) and the SBU2 pin (i.e., the second measured pin in this application embodiment) can be detected by the ADC as being within a first range, for example, 0.4V-0.5V.

[0088] If the Type-C connector (i.e., interface device 2 in this embodiment) is not connected to the analog headphones (i.e., external device in this embodiment) with the adapter, the voltage difference between the SBU1 pin (i.e., the first tested pin in this embodiment) and the SBU2 pin (i.e., the second tested pin in this embodiment) can be detected by the ADC as 0V.

[0089] Detection Scenario 2: The CPU (i.e., the controller in this embodiment) outputs a low level to SBU1 (i.e., the first tested pin in this embodiment) through the first line, and outputs a high level to SBU2 (i.e., the second tested pin in this embodiment) through the second line.

[0090] If the Type-C connector (i.e., the interface device 2 in this application embodiment) is connected to an analog headset (i.e., the external device in this application embodiment) with an adapter, the voltage difference between the SBU1 pin (i.e., the first measured pin in this application embodiment) and the SBU2 pin (i.e., the second measured pin in this application embodiment) can be detected by the ADC as being in the second range, for example, 0.8V-1V.

[0091] If the Type-C connector (i.e., interface device 2 in this embodiment) is not connected to the analog headphones (i.e., external device in this embodiment) with the adapter, the voltage difference between the SBU1 pin (i.e., the first tested pin in this embodiment) and the SBU2 pin (i.e., the second tested pin in this embodiment) can be detected by the ADC as 0V.

[0092] For example, based on Figure 3 The content shown (the microphone and adapter are connected in reverse, i.e., the ground wire of the adapter is connected to the microphone of the analog headphones, and the microphone of the adapter is connected to the ground wire of the analog headphones) can detect 0 ohms through the CC detection pin (i.e., the first detection pin 11 in this embodiment of the application), and may include, but is not limited to, the following detection scenarios:

[0093] Detection Scenario 3: The CPU (i.e., the controller in this embodiment) outputs a high level to SBU1 (i.e., the first tested pin in this embodiment) through the first line, and outputs a low level to SBU2 (i.e., the second tested pin in this embodiment) through the second line.

[0094] If the Type-C connector (i.e., the interface device 2 in this application embodiment) is connected to an analog headset (i.e., the external device in this application embodiment) with an adapter, the voltage difference between the SBU1 pin (i.e., the first measured pin in this application embodiment) and the SBU2 pin (i.e., the second measured pin in this application embodiment) can be detected by the ADC as being in the second range, for example, 0.8V-1V.

[0095] If the Type-C connector (i.e., interface device 2 in this embodiment) is not connected to the analog headphones (i.e., external device in this embodiment) with the adapter, the voltage difference between the SBU1 pin (i.e., the first tested pin in this embodiment) and the SBU2 pin (i.e., the second tested pin in this embodiment) can be detected by the ADC as 0V.

[0096] Detection Scenario 4: The CPU (i.e., the controller in this embodiment) outputs a low level to SBU1 (i.e., the first tested pin in this embodiment) through the first line, and outputs a high level to SBU2 (i.e., the second tested pin in this embodiment) through the second line.

[0097] If the Type-C connector (i.e., the interface device 2 in this application embodiment) is connected to an analog headset (i.e., the external device in this application embodiment) with an adapter, the voltage difference between the SBU1 pin (i.e., the first measured pin in this application embodiment) and the SBU2 pin (i.e., the second measured pin in this application embodiment) can be detected by the ADC as being within a first range, for example, 0.4V-0.5V.

[0098] If the Type-C connector (i.e., interface device 2 in this embodiment) is not connected to the analog headphones (i.e., external device in this embodiment) with the adapter, the voltage difference between the SBU1 pin (i.e., the first tested pin in this embodiment) and the SBU2 pin (i.e., the second tested pin in this embodiment) can be detected by the ADC as 0V.

[0099] It should be noted that, Figure 3 In this context, 41 can be the left channel of adapter 4, 42 can be the right channel of adapter 4, 51 can be the left channel of the analog headphones, and 52 can be the right channel of the analog headphones. Figure 3 41 can also be the right channel of adapter 4, 42 can be the left channel of adapter 4, 51 can be the right channel of analog headphones, and 52 can be the left channel of analog headphones. No specific limitation is made here.

[0100] Optionally, the detection circuit 1 is also used to generate a first instruction signal when the interface device 2 is connected to an external device. The first instruction signal is used to instruct the generation of display information, which is used to indicate that the connection of the external device is not supported.

[0101] In this embodiment, when the detection circuit detects that the interface device 2 is connected to an external device, it sends a first instruction signal to the controller 3. Upon receiving the first instruction signal, the controller 3 can control the generation of display information. The display information can show the user that the current device does not support connection with the current external device, thus avoiding the user's mistaken judgment that the electronic device where the detection device is located is faulty and improving the user experience.

[0102] In related technologies, a typical device that supports 3.5mm headphones can consist of the following components: CPU, PMIC, Codec, Audio switch, and Type-C to 3.5mm adapter. The PMIC detects the type of device using the CC pin, while the Codec and Audio switch identify 3.5mm headphones. A device that does not support 3.5mm analog headphones can consist of the following components: CPU, PMIC, and Type-C connector. The PMIC detects the CC pin; if the resistance is 0, it is considered to be a 3.5mm analog headphone. However, this method may result in false positives.

[0103] Compared with related technologies, this embodiment sets up a detection circuit and an interface device in the detection device; the detection circuit is connected to the target pin and at least one pin under test of the interface device respectively; the detection circuit is used to determine the connection status between the interface device and the external device through at least one pin under test in response to the target pin being grounded. This embodiment can determine whether the interface device is connected to an external device by combining at least one pin under test when the target pin is grounded. This allows the embodiment to accurately identify the connection status between the interface device and the external device through the target pin and at least one pin under test, avoiding the situation where the user mistakenly judges that the electronic device where the detection device is located is faulty, thus improving the user experience.

[0104] Based on the above-mentioned testing device, this application embodiment also provides a connector module, which includes the above-mentioned testing device.

[0105] Based on the above-described testing device, this application embodiment also provides an electronic device, which includes the above-described testing device or the above-described connector module.

[0106] Optionally, the aforementioned physical devices may also include a user interface, a network interface, a camera, radio frequency (RF) circuitry, sensors, audio circuitry, a Wi-Fi module, etc. The user interface may include a display screen, input units such as a keyboard, etc., and optional user interfaces may also include USB interfaces, card reader interfaces, etc. The network interface may optionally include standard wired interfaces, wireless interfaces (such as Wi-Fi interfaces), etc.

[0107] Those skilled in the art will understand that the physical device structure provided in this embodiment does not constitute a limitation on the physical device, and may include more or fewer components, or combine certain components, or have different component arrangements.

[0108] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platform, or it can be implemented by hardware. By applying the solution of this embodiment, compared with related technologies, this embodiment sets up a detection circuit and an interface device in the detection device; the detection circuit is connected to the target pin and at least one tested pin of the interface device respectively; the detection circuit is used to determine the connection status between the interface device and the external device through at least one tested pin in response to the target pin being grounded. This allows this embodiment to determine whether the interface device is connected to an external device by combining at least one tested pin when the target pin is grounded. This enables this embodiment to accurately identify the connection status between the interface device and the external device through the target pin and at least one tested pin, avoiding the situation where the user mistakenly judges that the electronic device where the detection device is located is faulty, and improving the user experience.

[0109] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0110] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A detection device, characterized in that, include: Detection circuits and interface devices; The detection circuit is connected to the target pin and at least one pin under test of the interface device, respectively. The detection circuit is used to determine the connection status between the interface device and the external device through the at least one tested pin in response to the target pin being grounded.

2. The apparatus according to claim 1, characterized in that, It also includes the controller; The controller is connected to the at least one tested pin via at least one line; The controller is used to output a level signal to the at least one tested pin through the at least one line.

3. The apparatus according to claim 2, characterized in that, The controller is connected to the first tested pin of the at least one tested pin via a first line; The controller is connected to the second test pin of the at least one test pin via a second line.

4. The apparatus according to claim 3, characterized in that, The controller is configured to alternately output high-level signals and low-level signals to the first tested pin via the first line, and / or alternately output high-level signals and low-level signals to the second tested pin via the second line.

5. The apparatus according to claim 4, characterized in that, The controller is configured to alternately output high-level signals and low-level signals to the first tested pin via the first line, and to alternately output high-level signals and low-level signals to the second tested pin via the second line, wherein the level signals output by the controller to the first line and the second line are different at the same time.

6. The apparatus according to claim 3, characterized in that, The first detection pin of the detection circuit is connected to the target pin; The second detection pin of the detection circuit is connected to the first test pin and the second test pin, respectively.

7. The apparatus according to claim 6, characterized in that, Also includes: resistance; The first end of the resistor is connected to the second detection pin, the first test pin, and the second test pin, respectively, and the second end of the resistor is grounded.

8. The apparatus according to claim 7, characterized in that, The detection circuit is used to determine the voltage difference between the first tested pin and the second tested pin based on the resistor, and the voltage difference is used to determine the connection status between the interface device and the external device.

9. The apparatus according to claim 1, characterized in that, The detection circuit is connected to the at least one tested pin via at least one functional pin. The detection circuit is used to output a level signal to the at least one tested pin through the at least one functional pin.

10. The apparatus according to claim 1, characterized in that, The detection circuit is also configured to generate a first instruction signal when the interface device is connected to the external device, the first instruction signal being used to instruct the generation of display information, the display information being used to indicate that the connection of the external device is not supported.

11. A connector module, characterized in that, The detection device includes any one of claims 1 to 10.

12. An electronic device, characterized in that, It includes the detection device according to any one of claims 1 to 10, or the connector module according to claim 11.

Images