A semiconductor structure

Abstract

The application provides a semiconductor structure applied to the technical field of semiconductors. The semiconductor structure comprises a substrate, a support layer structure located on the substrate and comprising a first support layer and a second support layer from bottom to top, and a lower electrode structure located in the support layer structure, wherein the lower electrode structure comprises a plurality of first lower electrodes and a second lower electrode, and the second lower electrode is located on the outer side of the plurality of first lower electrodes; wherein the top surface of the first lower electrode is higher than the bottom surface of the second support layer, and the top surface of the second lower electrode is lower than the bottom surface of the second support layer. The semiconductor structure provided by the application reduces the height of the capacitor structure in the edge area, so that the semiconductor structure is not prone to collapse, thereby improving the reliability of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure. Background Technology

[0002] With the continuous development of semiconductor technology, Dynamic Random Access Memory (DRAM), as a core component, is increasing in integration at an unprecedented rate. In order to integrate more memory cells within a limited chip area, the size of a single DRAM cell must be continuously miniaturized.

[0003] A typical DRAM memory cell usually contains a select transistor and a capacitor. The capacitor stores the charge representing data "0" or "1". To ensure that the capacitor still has sufficient capacitance for reliable data reading, writing, and storage even as cell sizes continue to shrink, modern DRAMs commonly employ a three-dimensional stacked cylindrical capacitor structure. This means that to obtain sufficient capacitor surface area, the height of the capacitor needs to be continuously increased, resulting in a significant increase in its aspect ratio.

[0004] However, this high aspect ratio columnar structure presents significant challenges. During DRAM manufacturing, especially in steps such as deep etching, wet cleaning, or material deposition after capacitor formation, the high aspect ratio capacitor structure is subjected to enormous mechanical stress. This stress can easily cause adjacent capacitors to tilt, bend, or even collapse, making contact and forming a so-called "bridge" defect. This results in electrical short circuits, ultimately leading to memory cell failure and severely impacting product yield.

[0005] This problem is particularly pronounced in the edge region of memory arrays. Compared to capacitors located in the core region of the array, capacitors in the edge region are more prone to structural collapse during manufacturing due to their uneven physical environment and stress distribution, and the lack of symmetrical support from adjacent external structures.

[0006] Therefore, the industry urgently needs a new technical solution to improve the structural stability of capacitors in the edge region of DRAM memory arrays, reduce defects caused by capacitor collapse, and thus improve the overall manufacturing yield and reliability of high-density DRAM products. Utility Model Content

[0007] The purpose of this application is to provide a semiconductor structure to improve the performance and reliability of semiconductor structures and capacitor structures.

[0008] To address the aforementioned technical problems, this application provides a semiconductor structure comprising: a substrate; a support layer structure located on the substrate, comprising, from bottom to top, a first support layer and a second support layer; and a lower electrode structure located within the support layer structure, the lower electrode structure comprising a plurality of first lower electrodes and a second lower electrode, the second lower electrode being located outside the plurality of first lower electrodes; wherein the top surface of the first lower electrode is higher than the bottom surface of the second support layer, and the top surface of the second lower electrode is lower than the bottom surface of the second support layer.

[0009] Optionally, the top surface of the first lower electrode is located between the top surface and the bottom surface of the second support layer.

[0010] Optionally, the top surface of the second lower electrode is located between the top surface and the bottom surface of the first support layer.

[0011] Optionally, in a direction perpendicular to the substrate, the endpoint of the second support layer falls within the first support layer.

[0012] Optionally, it also includes: a capacitor dielectric layer located on the lower electrode structure; and an upper electrode layer located on the capacitor dielectric layer.

[0013] Optionally, the upper electrode layer includes at least one protrusion in a direction parallel to the substrate, the at least one protrusion corresponding to the support layer structure.

[0014] Optionally, it may also include: a contact pad structure located within the substrate and corresponding to the lower electrode structure; and an etch stop layer located on the contact pad structure.

[0015] Optionally, the first lower electrode and the second lower electrode penetrate the etch stop layer and physically contact the contact pad.

[0016] Optionally, the contact pad that physically contacts the second lower electrode has a width in the first direction that is greater than the width of the other contact pads, and the contact pad that physically contacts the second lower electrode also physically contacts the first lower electrode that is closest to the second lower electrode.

[0017] Optionally, the bottom surface of the second lower electrode is higher than the top surface of the etch stop layer.

[0018] Optionally, the first lower electrode closest to the second lower electrode includes a lower half and an upper half that are separated from each other, wherein the bottom surface of the upper half is higher than the top surface of the first support layer.

[0019] Optionally, at least one of the lower electrode structures includes a curved side surface.

[0020] Optionally, a third support layer may be located between the first support layer and the second support layer.

[0021] This application also provides a semiconductor structure, comprising: a substrate; a lower electrode structure located on the substrate, the lower electrode structure including a plurality of first lower electrodes and a second lower electrode, the second lower electrode being located outside the plurality of first lower electrodes; and a support layer structure located between the lower electrode structures, comprising a first support layer and a second support layer from bottom to top; wherein the top surface of the first lower electrode is higher than the bottom surface of the second support layer, and the top surface of the second lower electrode is lower than the bottom surface of the second support layer.

[0022] Optionally, the top surface of the first lower electrode is located between the top surface and the bottom surface of the second support layer.

[0023] Optionally, the top surface of the second lower electrode is located between the top surface and the bottom surface of the first support layer.

[0024] Optionally, in a direction perpendicular to the substrate, the endpoint of the second support layer falls within the first support layer.

[0025] Optionally, it also includes: a capacitor dielectric layer located on the lower electrode structure; and an upper electrode layer located on the capacitor dielectric layer.

[0026] Optionally, the upper electrode layer includes at least one protrusion in a direction parallel to the substrate, the at least one protrusion corresponding to the support layer structure.

[0027] Optionally, at least one of the lower electrode structures includes a curved side surface.

[0028] The semiconductor structure provided in this application improves the reliability of the semiconductor structure by setting a capacitor structure with a height lower than that of the upper support layer in the edge region, making the capacitor height in the edge region lower than that in the storage region. This prevents defects caused by capacitor collapse in the edge region. Attached Figure Description

[0029] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:

[0030] Figures 1 to 10 This is a cross-sectional view of the first embodiment of this application and the corresponding formation method.

[0031] Figure 11 This is a schematic diagram of the semiconductor structure in the second embodiment of this application.

[0032] Figure 12 This is a schematic diagram of the semiconductor structure in the third embodiment of this application.

[0033] Figure 13 This is a schematic diagram of the semiconductor structure in the fourth embodiment of this application.

[0034] Figure 14 As in the first embodiment of this application Figure 10 The black dashed box shown corresponds to an enlarged schematic diagram of the semiconductor structure.

[0035] The attached figures are labeled as follows:

[0036] 100 - Substrate, 101 - Contact pad, 111 - Etch stop layer, 111T - Top surface of etch stop layer, 113 - First support material layer, 113a - First support layer, 113T - Top surface of first support layer, 113B - Bottom surface of first support layer, 115 - Third support material layer, 115a - Third support layer, 117 - Second support material layer, 117a - Second support layer, 117T - Top surface of second support layer, 117B - Bottom surface of second support layer, 117E - End point of second support layer, 121 - First sacrificial layer, 123 - Second sacrificial layer, 125 - Third sacrificial layer, 130 - First lower electrode, 130T - Top surface of first lower electrode, 131 - First lower electrode material layer, 133 - Second Lower electrode material layer, 140-capacitor dielectric layer, 150-upper electrode layer, 151-protrusion, 153-protrusion, 155-protrusion, 170-capacitor structure, 180-second lower electrode, 180T-top surface of second lower electrode, 202-contact pad, 251-protrusion, 255-protrusion, 380-second lower electrode, 380B-bottom surface of second lower electrode, 392-lower half of first lower electrode, 394-upper half of first lower electrode, 394B-bottom surface of upper half of first lower electrode, 480-second lower electrode, 490-upper half of first lower electrode, OP1-first through hole, OP2-second through hole, PR-photoresist layer, SP-support structure, D1-first direction, D2-second direction.

[0037] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0038] To make the technical solutions and advantages of the embodiments of this application clearer, the technical solutions of this application will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this application are shown in the accompanying drawings, it should be understood that this application can be implemented in various forms and should not be limited to the implementation methods described herein. Rather, these implementation methods are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0039] The present application is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present application will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, intended only to facilitate and clarify the illustration of the embodiments of the present application. It is understood that the terms "on," "above," and "over" in this application should be interpreted in the broadest sense, such that "on" means not only "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer.

[0040] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0041] In the embodiments of this application, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of this application can be arbitrarily combined without conflict.

[0042] Those skilled in the art to which this application pertains will readily understand that, to meet actual product requirements, the semiconductor structure of this application may have other forms and is not limited to those described above. Further embodiments or variations of the semiconductor structure of this application will be described below. For the sake of simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical components in the various embodiments of this application are designated with the same reference numerals to facilitate comparison between the embodiments.

[0043] It should be understood that "common type" in this application refers to constructing a continuous structural shape by utilizing the morphological similarity and correlation between two or more types.

[0044] Please refer to Figures 1 to 10 The diagram shown is a cross-sectional view of a method for fabricating a semiconductor structure according to the first embodiment of this application. Figure 1 As shown, a substrate 100 is provided, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe, etc.), or a silicon-on-insulator (SOI) substrate, or other suitable material layers. At least one shallow trench isolation (STI, not shown) is formed within the substrate 100, and multiple active areas (AA, not shown) are defined within the substrate 100. Furthermore, multiple gates, such as buried gates, can be formed within the substrate 100, where the buried gates can serve as buried word lines (BWL, not shown) in a semiconductor structure. Additionally, multiple bit lines (not shown, BL) and multiple storage node pads 101 are formed on the substrate 100. Although the bit lines are not specifically depicted in the accompanying drawings of this embodiment, those skilled in the art will readily understand that each bit line extends parallel to each other and is electrically isolated from the buried gate located within the substrate 100 by an insulating layer (not shown, for example, comprising a silicon oxide-silicon nitride-silicon oxide structure) covering the top surface of the substrate 100. The bit line contacts (not shown, bit line contacts, abbreviated as BLC) formed below each bit line extend into the active region to electrically connect to the substrate 100. Adjacent contact pads 101 are isolated from each other by storage nodepad isolation (SNPISO, abbreviated as SNPISO, not shown) disposed directly above each buried gate. Thus, the contact pads 101 can be electrically connected to the substrate 100 to receive and transmit voltage signals from the substrate 100 (such as transistor components within the substrate 100). In one embodiment, the contact pad 101 may be made of a low-resistivity metal such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W), but is not limited thereto. Since these structures for forming active regions, shallow trench isolation, buried gates, bit lines, and contact pad isolation are well-known in the art, they will not be described again here. Figure 1 In this context, substrate 100 represents the structural layer containing the aforementioned elements.

[0045] For example Figure 1As shown, a support stack layer continues to be formed on the substrate 100. Specifically, the support stack layer may include, for example, alternating layers of multiple material layers. In this embodiment, the support stack layer may include, for example, an etch stop layer 111 (e.g., silicon nitride or silicon carbonitride), a first sacrificial layer 121 (e.g., borosilicate glass (BPSG)), and a first support material layer 113 (e.g., silicon nitride or silicon carbonitride) stacked sequentially from bottom to top, but is not limited thereto. Preferably, the first sacrificial layer 121 may have a relatively large thickness, but is not limited thereto. Those skilled in the art will understand that the specific number of the aforementioned oxide layers and nitride layers stacked is not limited to... Figure 1 The number of layers shown is for reference only and can be adjusted to other numbers based on actual needs.

[0046] like Figure 2 As shown, a bottom anti-reflective coating (not shown) and a photoresist layer (not shown) are formed on the first support material layer 113. A photolithography process is then performed to pattern the photoresist layer, followed by an etching step to transfer the patterned photoresist layer to the underlying support stack layer. Specifically, for example, a dry etching process is used to sequentially penetrate the first support material layer 113, the first sacrificial layer 121, and the etch stop layer 111, forming multiple first vias OP1 within the support stack layer. The bottom of each first via OP1 exposes a contact pad 101 underneath, and excess bottom anti-reflective coating and photoresist layer are removed.

[0047] like Figure 3 As shown, a deposition and etch-back process is performed to form multiple first lower electrode material layers 131 within the first via OP1. In one embodiment, the fabrication process of the first lower electrode material layer 131 includes, but is not limited to, the following steps: First, an electrode material layer is formed in the first via OP1, such as a low-resistivity metal material including titanium nitride, aluminum, titanium, copper, or tungsten, preferably including titanium nitride. The electrode material layer can fill each first via OP1 and cover the upper surface of the first support material layer 113. Then, the excess electrode material layer outside the first via OP1 is removed, and a first lower electrode material layer 131 is formed within the first via OP1, with each first lower electrode material layer 131 covering and contacting the contact pad 101.

[0048] like Figure 4As shown, a support stack layer is formed on the first lower electrode material layer 131 and the first support material layer 113. Specifically, the support stack layer may include, for example, alternating layers of multiple material layers. In this embodiment, the support stack layer may include, for example, a second sacrificial layer 123 (e.g., borosilicate glass (BPSG)), a third support material layer 115 (e.g., silicon nitride or silicon carbonitride), a third sacrificial layer 125 (e.g., borosilicate glass (BPSG)), and a second support material layer 117 (e.g., silicon nitride or silicon carbonitride), etc., stacked sequentially from bottom to top, but is not limited thereto. Preferably, the second sacrificial layer 123 and the third sacrificial layer 125 may have a relatively large thickness, but is not limited thereto. Those skilled in the art will understand that the specific number of stacked oxide layers and nitride layers is not limited to... Figure 4 The number of layers shown is for reference only and can be adjusted to other numbers based on actual needs.

[0049] like Figure 5 As shown, a bottom anti-reflective coating (not shown) and a photoresist layer (not shown) are formed on the second support material layer 117. A photolithography process is then performed to pattern the photoresist layer, followed by an etching step to transfer the patterned photoresist layer to the underlying support stack layer. Specifically, for example, a dry etching process is used to sequentially penetrate the second support material layer 117, the third sacrificial layer 125, the third support material layer 115, and the second sacrificial layer 123, forming multiple second vias OP2 within the support stack layer. The bottom of each second via OP2 exposes a first lower electrode material layer 131 below, and excess bottom anti-reflective coating and photoresist layer are removed. The second vias OP2 have a higher aspect ratio than the first vias OP1, and no second vias OP2 are formed on the outermost first lower electrode material layer 131, thus they are not exposed by the second vias OP2. (Refer to...) Figure 5 In the outermost first lower electrode material layer 131, no second through-hole OP2 is formed. In other embodiments (not shown), none of the outermost first lower electrode material layers 131 may have a second through-hole OP2 formed.

[0050] like Figure 6As shown, a deposition and etch-back process is performed to form multiple second lower electrode material layers 133 within the second via OP2. In one embodiment, the fabrication process of the second lower electrode material layer 133 includes, but is not limited to, the following steps: First, an electrode material layer is formed in the second via OP2, such as a low-resistivity metal material including titanium nitride, aluminum, titanium, copper, or tungsten, preferably including titanium nitride. The electrode material layer can fill each second via OP2 and cover the upper surface of the second support material layer 117. Then, the excess electrode material layer outside the second via OP2 is removed, and a second lower electrode material layer 133 is formed within the second via OP2, with each second lower electrode material layer 133 covering and contacting the first lower electrode material layer 131. Since no second via OP2 is formed on the outermost first lower electrode material layer 131, no second lower electrode material layer 133 is formed on the outermost first lower electrode material layer 131. (Refer to...) Figure 6 In some embodiments (not shown), no second lower electrode material layer 133 is formed on the outermost first lower electrode material layer 131. In other embodiments, the second lower electrode material layer 133 may not be formed on any of the outermost first lower electrode material layers 131.

[0051] like Figure 7 As shown, a bottom anti-reflective coating (not shown) and a photoresist layer PR are formed on the second lower electrode material layer 133 and the second support material layer 117. Then, a photolithography process is performed to pattern the photoresist layer, exposing the second support material layer 117 located between the second lower electrode material layers 133 and the second support material layer 117 located at the edge.

[0052] like Figure 8As shown, the etching process continues, using the patterned photoresist layer PR to form a support opening in the remaining support material layers of the aforementioned support stack. This support opening penetrates the second support material layer 117, the third sacrificial layer 125, the second sacrificial layer 123, the first support material layer 113, and the first sacrificial layer 121. The support opening is located between adjacent first lower electrode material layers 131 and 133, exposing their sidewalls. A wet etching process can then be performed, for example, by introducing an etchant such as tetramethylammonium hydroxide (TMAH) to remove the remaining portions of the first sacrificial layer 121, the second sacrificial layer 123, and the third sacrificial layer 125. At this point, the remaining material layers supporting the stacked layers, including the first support material layer 113, the third support material layer 115, and the second support material layer 117, are located between each of the first lower electrode material layers 131 or adjacent second lower electrode material layers 133, and can serve as the first support layer 113a, the third support layer 115a, and the second support layer 117a. However, since the second lower electrode material layer 133 is not formed on the outermost first lower electrode material layer 131, the third support layer 115a and the second support layer 117a may be over-etched relative to the first support layer 113a.

[0053] like Figure 9 and Figure 10 As shown, at least one deposition process is performed to sequentially form a capacitor dielectric layer 140 and an upper electrode layer 150. The capacitor dielectric layer 140 conformally covers the exposed surfaces of the first lower electrode material layer 131, the second lower electrode material layer 133, the first support layer 113a, the third support layer 115a, and the second support layer 117a, while the upper electrode layer 150 covers the capacitor dielectric layer 140 and fills the remaining space between the first lower electrode material layer 131 and the second lower electrode material layer 133. In one embodiment, the capacitor dielectric layer 140 includes, for example, a high dielectric material, preferably zirconium oxide-aluminum oxide-zirconia (ZAZ), and the upper electrode layer 150 includes, for example, a low-resistivity metal material such as titanium nitride, aluminum, titanium, copper, or tungsten, a semiconductor material such as SiGe, or a combination of the above materials, preferably including a multilayer structure of titanium nitride and SiGe, but not limited thereto.

[0054] At this point, the semiconductor structure in the first embodiment of this application has been formed. Figure 10 This is the semiconductor structure in the first embodiment of this application. Figure 14 As in the first embodiment of this application Figure 10 The black dashed box shown corresponds to an enlarged schematic diagram of the semiconductor structure, where the first direction D1 is parallel to the substrate, and the second direction D2 is perpendicular to the substrate. Figure 10 and Figure 14 As shown, the semiconductor structure in the first embodiment of this application includes a substrate 100, in which a plurality of contact pads 101 are disposed, and an etch stop layer 111 covers the plurality of contact pads 101. A lower electrode structure is disposed thereon, arranged along a first direction, including a plurality of first lower electrodes 130 and a second lower electrode 180 located outside all the first lower electrodes 130 in the first direction D1. Each first lower electrode 130 includes a first lower electrode material layer 131 and a second lower electrode material layer 133 from bottom to top. The first lower electrode material layer 131 and the second lower electrode 180 of the first lower electrode 130 respectively penetrate the etch stop layer 111 and physically contact the corresponding contact pads 101. More specifically, the first lower electrode material layer 131 and the second lower electrode material layer 133 of the first lower electrode 130 can be columnar or cylindrical structures. Their width in the first direction D1 can gradually narrow as the depth in the second direction D2 increases. The bottom width of the second lower electrode material layer 133 is smaller than the top width of the first lower electrode material layer 131, but it is not limited to this.

[0055] Please continue to refer to this. Figure 10 A support structure SP is also provided between the first lower electrode 130 and the second lower electrode 180. More specifically, the support structure SP is provided from bottom to top with a first support layer 113a, a third support layer 115a, and a second support layer 117a. The first support layer 113a is disposed between the first lower electrode material layers 131, between the first lower electrode material layer 131 and the second lower electrode 180, or on one side of the second lower electrode 180. The third support layer 115a and the second support layer 117a are disposed only between the second lower electrode material layers 133 or on one side of the second lower electrode material layers 133. The capacitor dielectric layer 140 conformally covers the exposed surfaces of the first lower electrode material layers 131, the second lower electrode material layers 133, the first support layer 113a, the third support layer 115a, and the second support layer 117a, while the upper electrode layer 150 covers the capacitor dielectric layer 140 and fills the remaining space between the first lower electrode material layers 131 and the second lower electrode material layers 133. The upper electrode layer 150 includes protrusions 151, 153, and 155 in the first direction D1, corresponding to the first support layer 113a, the third support layer 115a, and the second support layer 117a, respectively. In other embodiments (not shown), the support structure SP may include a structure with three or more layers or fewer layers. In this case, the number of protrusions in the upper electrode layer 150 may also be increased or decreased accordingly, but is not limited thereto.

[0056] Please continue to refer to this. Figure 14The top surface 130T of the first lower electrode 130 is higher than the bottom surface 117B of the second support layer 117a, while the top surface 180T of the second lower electrode 180 is lower than the bottom surface 117B of the second support layer 117a. Specifically, the top surface 130T of the first lower electrode 130 is located between the top surface 117T and the bottom surface 117B of the second support layer 117a, while the top surface 180T of the second lower electrode 180 is located between the top surface 113T and the bottom surface 113B of the first support layer 113a. Since the first lower electrode 130 includes a lower first lower electrode material layer 131 and an upper second lower electrode material layer 133, while the second lower electrode 180 only includes the lower first lower electrode material layer 131, the top surface 180T of the second lower electrode 180 is lower than the top surface 130T of the first lower electrode 130 and is approximately flush with the top surface of the first lower electrode material layer 131 of the first lower electrode 130. That is, the top surface of the first lower electrode material layer 131 is located between the top surface 113T and the bottom surface 113B of the first support layer 113a, while the top surface 130T of the second lower electrode material layer 133 is located between the top surface 117T and the bottom surface 117B of the second support layer 117a. The bottom surface of the second lower electrode material layer 133 is lower than the top surface 113T of the first support layer 113a, but this is not the only case. Furthermore, the distance that the first support layer 113a, which connects to the second lower electrode 180, extends in the first direction is longer than that of the third support layer 115a and the second support layer 117a. That is, the end face 117E of the third support layer 115a and the second support layer 117a will fall within the first support layer 113a in the second direction, but this is not the only case.

[0057] Figure 11 , Figure 12 , Figure 13 Cross-sectional structural schematic diagrams of semiconductor structures according to the second, third, and fourth embodiments of this application are shown respectively. These diagrams can be used to illustrate the semiconductor structures. Figure 11 , Figure 12 , Figure 13 Each with the above Figure 10 The semiconductor structures of the first embodiment shown are compared to highlight the differences between the embodiments. For simplicity, the following description focuses primarily on the differences between the embodiments, without repeating the similarities. Furthermore, identical elements in the embodiments of this application are designated with the same reference numerals to facilitate comparison between the embodiments.

[0058] like Figure 11The second embodiment of this application is shown, wherein the contact pad 202 that physically contacts the second lower electrode 180 has a width in the first direction greater than the width of the other contact pads 101, and the contact pad 202 also physically contacts the first lower electrode 130 that is closest to the second lower electrode 180. The length of the contact pad 202 and the actual number of lower electrodes connected can be adjusted according to actual needs, and the present invention is not limited thereto. In addition, the support structure SP is provided with only a first support layer 113a and a second support layer 117a from bottom to top. Therefore, the upper electrode layer 150 includes a protrusion 251 and a protrusion 255 in the first direction D1, which correspond to the first support layer 113a and the second support layer 117a, respectively, but is not limited thereto.

[0059] like Figure 12 The third embodiment of this application is shown. The first lower electrode 130, closest to the second lower electrode 180, includes a lower half 392 and an upper half 394 separated from each other. The bottom surface 394B of the upper half 394 is higher than the top surface 113T of the first support layer 113a. Furthermore, the second lower electrode 380 does not penetrate the etch stop layer 111, meaning the bottom surface 380B of the second lower electrode 380 is higher than the top surface 111T of the etch stop layer 111. In other embodiments (not shown), the first lower electrode material layer 131 of the first lower electrode 130 may also have a surface higher than the top surface of the etch stop layer 111. The specific number can be adjusted according to actual needs, and the present invention is not limited thereto but is not restricted thereto.

[0060] like Figure 13 The fourth embodiment of this application is shown. In this embodiment, the second lower electrode material layer 490 and the second lower electrode 480 of the first lower electrode 130 located at the edge portion each have a curved side surface. In other embodiments (not shown), the first lower electrode material layer 131 of the first lower electrode 130 may also have a curved side surface; the number and shape of the curves can be adjusted according to actual needs, and this invention is not limited thereto.

[0061] In summary, this application provides a semiconductor structure including a multilayer capacitor, characterized in that each first lower electrode 130 comprises, from bottom to top, a first lower electrode material layer 131 and a second lower electrode material layer 133, while the second lower electrode 180 comprises only the first lower electrode material layer 131, such that the top surface 130T of the first lower electrode 130 is higher than the bottom surface 117B of the second support layer 117a, while the top surface 180T of the second lower electrode 180 is lower than the bottom surface 117B of the second support layer 117a. By reducing the number of electrode layers of the second lower electrode 180 in the edge region, the height of the second lower electrode 180 is reduced, making the second lower electrode 180 in the edge region less prone to collapse, thereby improving the reliability of the semiconductor structure.

[0062] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A support layer structure is located on the substrate and includes a first support layer and a second support layer from bottom to top; The lower electrode structure is located within the support layer structure. The lower electrode structure includes a plurality of first lower electrodes and a second lower electrode, with the second lower electrode located outside the plurality of first lower electrodes. The top surface of the first lower electrode is higher than the bottom surface of the second support layer, and the top surface of the second lower electrode is lower than the bottom surface of the second support layer.

2. The semiconductor structure according to claim 1, characterized in that, The top surface of the first lower electrode is located between the top surface and the bottom surface of the second support layer.

3. The semiconductor structure according to claim 1, characterized in that, The top surface of the second lower electrode is located between the top surface and the bottom surface of the first support layer.

4. The semiconductor structure according to claim 1, characterized in that, In a direction perpendicular to the substrate, the endpoint of the second support layer falls within the first support layer.

5. The semiconductor structure according to claim 1, characterized in that, Also includes: A capacitor dielectric layer is located on the lower electrode structure; The upper electrode layer is located on the capacitor dielectric layer.

6. The semiconductor structure according to claim 5, characterized in that, The upper electrode layer includes at least one protrusion in a direction parallel to the substrate, the at least one protrusion corresponding to the support layer structure.

7. The semiconductor structure according to claim 1, characterized in that, Also includes: A contact pad structure is located within the substrate and corresponds to the lower electrode structure; An etch stop layer is located on the contact pad structure.

8. The semiconductor structure according to claim 7, characterized in that, The first lower electrode and the second lower electrode penetrate the etch stop layer and physically contact the contact pad.

9. The semiconductor structure according to claim 8, characterized in that, The contact pad that is in physical contact with the second lower electrode has a width in a first direction that is greater than the width of the other contact pads, and the contact pad that is in physical contact with the second lower electrode also has physical contact with the first lower electrode that is closest to the second lower electrode.

10. The semiconductor structure according to claim 7, characterized in that, The bottom surface of the second lower electrode is higher than the top surface of the etch stop layer.

11. The semiconductor structure according to claim 10, characterized in that, The first lower electrode, which is closest to the second lower electrode, includes a lower half and an upper half that are separated from each other, wherein the bottom surface of the upper half is higher than the top surface of the first support layer.

12. The semiconductor structure according to claim 1, characterized in that, At least one of the lower electrode structures includes a curved side surface.

13. The semiconductor structure according to claim 1, characterized in that, It also includes a third support layer located between the first support layer and the second support layer.

14. A semiconductor structure, characterized in that, include: Substrate; A lower electrode structure is located on the substrate, the lower electrode structure includes a plurality of first lower electrodes and a second lower electrode, the second lower electrode being located outside the plurality of first lower electrodes; A support layer structure, located between the lower electrode structures, includes a first support layer and a second support layer from bottom to top; The top surface of the first lower electrode is higher than the bottom surface of the second support layer, and the top surface of the second lower electrode is lower than the bottom surface of the second support layer.

15. The semiconductor structure according to claim 14, characterized in that, The top surface of the first lower electrode is located between the top surface and the bottom surface of the second support layer.

16. The semiconductor structure according to claim 14, characterized in that, The top surface of the second lower electrode is located between the top surface and the bottom surface of the first support layer.

17. The semiconductor structure according to claim 14, characterized in that, In a direction perpendicular to the substrate, the endpoint of the second support layer falls within the first support layer.

18. The semiconductor structure according to claim 14, characterized in that, Also includes: A capacitor dielectric layer is located on the lower electrode structure; The upper electrode layer is located on the capacitor dielectric layer.

19. The semiconductor structure according to claim 18, characterized in that, The upper electrode layer includes at least one protrusion in a direction parallel to the substrate, the at least one protrusion corresponding to the support layer structure.

20. The semiconductor structure according to claim 14, characterized in that, At least one of the lower electrode structures includes a curved side surface.

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