Semiconductor device

Abstract

The utility model discloses a semiconductor device, contain epitaxial layer of first conductive type setting on the base of first conductive type, the groove is set in epitaxial layer, gate electrode and shielding electrode longitudinal separation and all set up in the groove, wherein the lowest bottom surface of gate electrode is higher than the highest top surface of shielding electrode. The base area of second conductive type is set in epitaxial layer, and the side of adjoining groove, wherein the lowest bottom surface of base area is flush or lower than the highest top surface of shielding electrode. The source area of first conductive type is set in the base area, is located the top surface of base area, is adjacent to the side of groove, and the drain electrode is set below the base.

Description

Technical Field

[0001] This invention relates to semiconductor technology, and in particular to a semiconductor device having a trench gate. Background Technology

[0002] Trench-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) are common power devices in power electronic systems. They employ a vertical structure with the gate located within a trench. Compared to planar-gate MOSFETs, trench-gate MOSFETs can integrate a greater number of active cells into the same wafer area, thereby improving power device performance. They are widely used in various power conversion and control systems, including microprocessor power supplies, display drivers, automotive electronics, and consumer electronics. Trench-gate MOSFETs offer advantages such as low on-resistance (Ron), fast switching speed, and high power density. However, these performance parameters are competitive; for example, reducing on-resistance can lead to increased switching losses. Therefore, ensuring that trench-gate MOSFETs meet the operating frequency and power requirements of specific applications remains a challenge. Utility Model Content

[0003] In view of this, the purpose of this utility model is to provide a semiconductor device that, by adjusting the structural relationship between the trench gate and the substrate region, enables the semiconductor device to simultaneously meet the requirements of low on-resistance and low switching loss.

[0004] To achieve the above objectives, one embodiment of the present invention provides a semiconductor device, including a substrate, an epitaxial layer, a trench, a gate electrode, a shielding electrode, a substrate region, a source region, and a drain electrode. The substrate has a first conductivity type, and the epitaxial layer is disposed on the substrate and also has the first conductivity type. A trench is disposed in the epitaxial layer, and the gate electrode and the shielding electrode are longitudinally separated and both disposed within the trench, wherein the lowest bottom surface of the gate electrode is higher than the highest top surface of the shielding electrode. A substrate region is disposed in the epitaxial layer, adjacent to the side surface of the trench, and has a second conductivity type, wherein the lowest bottom surface of the substrate region is flush with or lower than the highest top surface of the shielding electrode. A source region is disposed within the substrate region, located on the top surface of the substrate region, adjacent to the side surface of the trench, and has the first conductivity type. The drain electrode is disposed below the substrate.

[0005] The bottom of the gate electrode includes a flat bottom surface, a circular arc bottom surface, or a bottom surface with two undulating troughs.

[0006] The shielding electrode is located directly below the protrusion on the arc-shaped bottom surface, or directly below a region between the two troughs of the undulating bottom surface.

[0007] The gate electrode includes a first gate and a second gate that are laterally separated. The shielding electrode is located directly below a region between the first gate and the second gate. An inner side of the first gate is close to the second gate. In the vertical projection direction, a side of the shielding electrode is flush with the inner side of the first gate, or a portion of the first gate overlaps with the shielding electrode, and the overlapping portion is greater than 0% to 50% of the area of ​​the first gate.

[0008] The invention further includes: a contact plug that penetrates the source region and extends downward into the substrate region; and a heavily doped region disposed directly below the contact plug, having the second conductivity type and embedded in the substrate region, wherein the bottom of the substrate region includes a undulating bottom surface, the undulating bottom surface including a middle portion, a first side portion and a second side portion, the middle portion being higher than the first side portion and the second side portion, and the middle portion being located directly below the heavily doped region, and the lowest bottom surface of the substrate region being located at the first side portion and the second side portion of the undulating bottom surface.

[0009] Both the contact plug and the shielding electrode are electrically coupled to a source voltage.

[0010] It also includes: a contact plug that penetrates the source region and the substrate region and extends into the epitaxial layer; and a heavily doped region disposed directly below the contact plug, having the second conductivity type, and embedded in the epitaxial layer.

[0011] It also includes: a gate dielectric layer disposed in the trench and surrounding the side of the gate electrode; an insulating layer disposed in the trench and surrounding the side and bottom of the shielding electrode; and a dielectric layer disposed between the gate electrode and the shielding electrode.

[0012] The thickness of the insulating layer surrounding the side of the shielding electrode is greater than the thickness of the gate dielectric layer.

[0013] The ratio of a maximum length of the gate electrode to a maximum depth of the substrate region is 2 / 3 to 4 / 5. Attached Figure Description

[0014] To facilitate understanding, the accompanying drawings and detailed textual descriptions can be consulted while reading this utility model. Specific embodiments of this utility model are explained in detail with reference to the corresponding drawings, which also illustrate the working principle of these embodiments. Furthermore, for clarity, the features in the drawings may not be drawn to scale; therefore, the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0015] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 This is a cross-sectional schematic diagram of a semiconductor device according to some embodiments of the present invention.

[0016] Figure 7 , Figure 8 and Figure 9 This is a cross-sectional schematic diagram of some stages of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0017] Figure 10 This is a cross-sectional schematic diagram of an intermediate stage in a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0018] Explanation of reference numerals in the attached figures: 100 ~ Semiconductor device; 101 ~ Substrate; 103 ~ Epitaxial layer; 105 ~ Trench; 107 ~ Shielding electrode; 107S1, 107S2 ~ Side surface; 107T ~ Top surface; 109 ~ Gate electrode; 109B ~ Bottom surface; 109B1, 109B2 ~ Valley; 109-1 ~ First gate; 109-2 ~ Second gate; 109-1S, 109-2S ~ Inner surface; 111 ~ Insulating layer; 112 ~ Dielectric layer; 113 ~ Gate dielectric layer; 114 ~ Oxide layer; 115 ~ Substrate region; 115B ~ Bottom surface; 115C ~ Middle portion; 115B1 ~ First side portion; 115B2 ~ Second side portion; 115-1 ~ First well region; 115-2 ~ Second well region; 115-3 ~ Third well region; 115-4 ~ Fourth well region; 117 ~ Source region; 119 ~ Heavily doped region; 120 ~ Dielectric layer; 121 ~ Contact hole; 122 ~ Contact plug; 122B ~ Bottom surface; 124 ~ Drain electrode; 131 ~ First stage ion implantation; 132 ~ Second stage ion implantation; 133 ~ Vertical ion implantation; 134 ~ Tilted ion implantation; D ~ Maximum depth; L ~ Maximum length; T1, T2, T3 ~ Thickness; S101, S103, S105, S107A, S107B, S108A, S108B, S109A, S109B, S111, S113, S115 ~ Steps. Detailed Implementation

[0019] This utility model provides several different embodiments that can be used to implement different features of the utility model. For the sake of simplicity, examples of specific components and arrangements are also described. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following description of "a first feature forming on or above a second feature" can mean "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature," so that the first feature and the second feature are not in direct contact. Furthermore, various embodiments of this utility model may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and is not intended to indicate the relationship between different embodiments and / or configurations.

[0020] Furthermore, regarding spatially related descriptive terms mentioned in this utility model, such as "below," "low," "high," "below," "above," "above," "top," "bottom," and similar terms, for ease of description, their usage is to describe the relative relationship between one element or feature and another (or more) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientation of the semiconductor device during use and operation. As the orientation of the semiconductor device varies (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

[0021] Although this utility model uses terms such as "first," "second," and "third" to describe various elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of this utility model, the first element, component, region, layer, or section discussed below may also be referred to as a second element, component, region, layer, or section.

[0022] The terms "about" or "generally" used in this invention typically mean within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, even without a specific mention of "about" or "generally," the meaning of "about" or "substantially" may be implied.

[0023] Although the present invention is described below by way of specific embodiments, the principles of the present invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the present invention, certain details have been omitted; these omitted details fall within the scope of knowledge of one skilled in the art.

[0024] This invention relates to a semiconductor device including a trench gate and a method for manufacturing the same. In embodiments of this invention, a gate electrode and a shield electrode are longitudinally separated within the trench, wherein the lowest bottom surface of the gate electrode is higher than the highest top surface of the shield electrode, and the lowest bottom surface of the body region is flush with or slightly lower than the highest top surface of the shield electrode, thereby enabling the semiconductor device to simultaneously meet the requirements of low on-resistance and low switching loss.

[0025] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a substrate 101, an epitaxial layer 103, a trench 105, a gate electrode 109, a shielded electrode 107, a substrate region 115, a source region 117, and a drain electrode 124. The substrate 101 has a first conductivity type, for example, heavily doped N-type (N... +The substrate 101 serves as a drain region, with a drain electrode 124 disposed below the bottom surface of the substrate 101. An epitaxial layer 103 is disposed on the substrate 101 and has a first conductivity type, such as an N-type epitaxial layer. The doping concentration of the epitaxial layer 103 is lower than that of the substrate 101. In some embodiments, the substrate 101 and the epitaxial layer 103 may each be composed of silicon, silicon carbide, or other suitable semiconductor materials. A trench 105 is disposed in the epitaxial layer 103, and both the gate electrode 109 and the shielding electrode 107 are disposed within the trench 105, longitudinally separated from each other. The shielding electrode 107 has the function of shielding the electric field and can also be called a field plate. The lowest bottom surface 109B of the gate electrode 109 is higher than the highest top surface 107T of the shielding electrode 107. In addition, an insulating layer 111, a dielectric layer 112, and a gate dielectric layer 113 are provided within the trench 105. The gate dielectric layer 113 surrounds the side of the gate electrode 109, the insulating layer 111 surrounds the side and bottom of the shielding electrode 107, and the dielectric layer 112 is disposed between the gate electrode 109 and the shielding electrode 107, electrically isolating the gate electrode 109 and the shielding electrode 107. The thickness T1 of the insulating layer 111 surrounding the side of the shielding electrode 107 and the thickness T2 of the dielectric layer 112 are both greater than the thickness T3 of the gate dielectric layer 113, and the thickness T2 of the dielectric layer 112 may be less than, equal to, or greater than the thickness T1 of the insulating layer 111. In some embodiments, the gate electrode 109 and the shielding electrode 107 may be composed of amorphous silicon or polycrystalline silicon, the dielectric layer 112 and the gate dielectric layer 113 may be composed of silicon dioxide, and the insulating layer 111 may be composed of silicon oxynitride, silicon dioxide, silicon nitride, or a combination thereof. Furthermore, the top surface of the gate electrode 109 is typically slightly lower than the top surface of the trench 105, and the oxide layer 114 may fill the depression above the top surface of the gate electrode 109. The oxide layer 114 may also cover the top surface of the epitaxial layer 103, the gate dielectric layer 113 within the trench 105, and the source region 117. In some embodiments, the oxide layer 114 may be composed of silicon dioxide, borosilicate glass (BPSG), silicon phosphosilicate glass (PSG), or undoped silicon glass (USG), etc.

[0026] A substrate region 115 is disposed in the epitaxial layer 103, located between two trenches 105, adjacent to the side surface of the trenches 105. The substrate region 115 has a second conductivity type, such as a P-type substrate region. In some embodiments of this invention, the first conductivity type may be N-type and the second conductivity type may be P-type, but it is not limited thereto. In other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type. A source region 117 is disposed within the substrate region 115, located on the top surface of the substrate region 115, adjacent to the side surface of the trenches 105. The source region 117 has a first conductivity type, such as an N-type heavily doped region (N... +In a comparative example semiconductor device, when the lowest bottom surface 115B of the substrate region 115 is higher than the lowest bottom surface 109B of the gate electrode 109 (e.g., at half the length of the gate electrode 109), the on-resistance can be reduced, but the switching loss will also increase. In the semiconductor device 100 of this invention, the lowest bottom surface 115B of the substrate region 115 is flush with (e.g., at half the length of the gate electrode 109), the on-resistance can be reduced, but the switching loss will also increase. Figure 1 (As shown by the dashed line in the figure) or slightly below the highest top surface 107T of the shielding electrode 107, thereby maintaining low on-resistance (Ron) while reducing switching loss, achieving a balance between low on-resistance and low switching loss.

[0027] In some embodiments, the ratio of the maximum length L of the gate electrode 109 to the maximum depth D of the substrate region 115 can be approximately 2 / 3 to 4 / 5. When the ratio of the maximum length L to the maximum depth D is less than 2 / 3, although switching losses can be reduced, low on-resistance cannot be achieved. When the ratio of the maximum length L to the maximum depth D is greater than 4 / 5, although on-resistance can be reduced, switching losses will increase. According to embodiments of the present invention, by making the lowest bottom surface 115B of the substrate region 115 flush with or slightly lower than the highest top surface 107T of the shielding electrode 107, and controlling the ratio of the maximum length L of the gate electrode 109 to the maximum depth D of the substrate region 115 to be approximately 2 / 3 to 4 / 5, a balance can be achieved between low on-resistance and low switching losses to meet various electrical performance requirements of the semiconductor device 100 in applications. In addition, the vertical distance between the lowest bottom surface 109B of the gate electrode 109 and the lowest bottom surface 115B of the substrate region 115 is about 1 / 4 to 1 / 5 of the maximum depth D of the substrate region 115, and this vertical distance is generally no more than about 0.2 micrometers (µm) to ensure the electrical performance of the semiconductor device 100. For example, if this vertical distance exceeds 0.2 µm by too much, it will lead to a higher on-resistance, which is not conducive to the turn-on of the semiconductor device 100. Therefore, if this vertical distance does not exceed 0.2 µm, the semiconductor device 100 can have the advantages of both low on-resistance and low switching loss.

[0028] See also Figure 1 The semiconductor device 100 further includes a dielectric layer 120 disposed on the top surface of the epitaxial layer 103 and the oxide layer 114. A contact plug 122 passes through the dielectric layer 120 and the oxide layer 114, penetrates the source region 117, and extends downward into the substrate region 115. The composition of the contact plug 122 is, for example, tungsten (W) or other conductive metal. The heavily doped region 119 has a second conductivity type, for example, a P-type heavily doped region (P... +The contact plug 122 is positioned directly below the bottom of the contact plug 122. The vertical projected area of ​​the heavily doped region 119 can be approximately equal to or slightly smaller than the bottom surface area of ​​the contact plug 122. For example, the maximum width of the heavily doped region 119 can be less than or equal to the bottom surface width of the contact plug 122. Both the bottom surface of the contact plug 122 and the heavily doped region 119 are embedded in the substrate region 115. Furthermore, both the contact plug 122 and the shielding electrode 107 can be electrically coupled to the source voltage (e.g., ground voltage) through an interconnect layer (not shown) above the dielectric layer 120. Additionally, in... Figure 1 In the semiconductor device 100, the bottom of the gate electrode 109 may have a flat bottom surface, and the lowest bottom surface 109B of the gate electrode 109 is such a flat bottom surface. The bottom of the substrate region 115 also has a flat bottom surface, and the lowest bottom surface 115B of the substrate region 115 is such a flat bottom surface.

[0029] Figure 2 This is a cross-sectional schematic diagram of a semiconductor device 100 according to another embodiment of the present invention. In this embodiment, the bottom of the gate electrode 109 may have an arc-shaped bottom surface, the lowest bottom surface 109B is at the top of the protrusion of the arc-shaped bottom surface, and the shielding electrode 107 is located directly below the protrusion of this arc-shaped bottom surface. Furthermore, the bottom of the substrate region 115 has a flat bottom surface, the lowest bottom surface 115B is this flat bottom surface, and the lowest bottom surface 115B of the substrate region 115 may be flush with (e.g.) Figure 2 (As shown by the dashed line in the figure) or slightly below the highest top surface 107T of the shielding electrode 107.

[0030] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device 100 according to another embodiment of the present invention. In this embodiment, the bottom of the gate electrode 109 has an undulating bottom surface including two troughs 109B1 and 109B2, and the lowest bottom surface of the gate electrode 109 is at the lowest point of these two troughs 109B1 and 109B2. The shielding electrode 107 is located directly below the region between the two troughs 109B1 and 109B2 of this undulating bottom surface. Compared to Figure 1 A gate electrode 109 with a flat bottom surface is fabricated on a shielding electrode 107 as shown in the image. Figure 3 The gate electrode 109 shown, with its undulating bottom surface, is simpler, eliminating the need for additional process steps to form a flat dielectric layer 112 on the shielding electrode 107. Furthermore, the bottom of the substrate region 115 has a flat bottom surface, with the lowest bottom surface 115B of the substrate region 115 being this flat bottom surface, and the lowest bottom surface 115B of the substrate region 115 is flush with it (e.g., ...). Figure 3 (As shown by the dashed line in the figure) or slightly below the highest top surface 107T of the shielding electrode 107.

[0031] Figure 4This is a cross-sectional schematic diagram of a semiconductor device 100 according to another embodiment of the present invention. In this embodiment, the gate electrode 109 includes a laterally separated first gate 109-1 and a second gate 109-2. A gate dielectric layer 113 surrounds the sides of the first gate 109-1 and the second gate 109-2 and is disposed between the first gate 109-1 and the second gate 109-2, electrically isolating the first gate 109-1 and the second gate 109-2. A shielding electrode 107 is located directly below the region between the first gate 109-1 and the second gate 109-2. The bottoms of both the first gate 109-1 and the second gate 109-2 have flat bottom surfaces, and the lowest bottom surface 109B of the gate electrode 109 is this flat bottom surface. In some embodiments, a portion of the first gate 109-1 may overlap with the shielding electrode 107, and the area of ​​the overlapping portion is greater than 0% to about 50% of the total area of ​​the first gate 109-1. Furthermore, a portion of the second gate 109-2 may overlap with the shielding electrode 107, and the area of ​​the overlapping portion is greater than 0% to approximately 50% of the total area of ​​the second gate 109-2. Additionally, the bottom of the substrate region 115 has a flat bottom surface, and the lowest bottom surface 115B of the substrate region 115 is this flat bottom surface, and the lowest bottom surface 115B of the substrate region 115 is flush with it (e.g., Figure 4 (As shown by the dashed line in the diagram) or slightly below the highest top surface 107T of the shielding electrode 107. Compared to Figure 1 The gate electrode 109 has a flat bottom surface and a large area, and is fabricated as follows: Figure 4 The two laterally separated first gates 109-1 and second gates 109-2 shown do not require a planarization process; the relatively small area of ​​the first gates 109-1 and second gates 109-2 can be achieved using etch-back. Furthermore, the first gates 109-1 and second gates 109-2 can provide more channels and reduce gate impedance, thus making it easier to control the gate length. Figure 4 The semiconductor device 100 achieves better component characteristics.

[0032] In some embodiments, at least one of the first gate 109-1 and the second gate 109-2 does not overlap with the shielding electrode 107. The inner side 109-1S of the first gate 109-1 is close to the second gate 109-2, and the inner side 109-2S of the second gate 109-2 is close to the first gate 109-1. When the first gate 109-1 does not overlap with the shielding electrode 107, in the vertical projection direction (e.g., the XY plane), one side 107S1 of the shielding electrode 107 is aligned with the inner side 109-1S of the first gate 109-1. Furthermore, when the second gate 109-2 does not overlap with the shielding electrode 107, in the vertical projection direction, the other side 107S2 of the shielding electrode 107 may be aligned with the inner side 109-2S of the second gate 109-2.

[0033] Figure 5 This is a cross-sectional schematic diagram of a semiconductor device 100 according to another embodiment of the present invention. In this embodiment, the bottom of the substrate region 115 has an undulating bottom surface, which includes a middle portion 115C, a first side portion 115B1, and a second side portion 115B2. Horizontally, the middle portion 115C is higher than the first side portion 115B1 and the second side portion 115B2. Furthermore, the middle portion 115C is located directly below the heavily doped region 119, and the lowest bottom surface of the substrate region 115 is located at the lowest point of the first side portion 115B1 and the second side portion 115B2, and the lowest bottom surface of the substrate region 115 is flush with (e.g., ...). Figure 5 (As shown by the dashed line in the figure) or slightly below the highest top surface 107T of the shielding electrode 107. Figure 5 The undulating bottom surface of the substrate region 115 includes a deeper first side portion 115B1 and a second side portion 115B2, which can reduce switching losses. Moreover, the shallower middle portion 115C included in the undulating bottom surface of the substrate region 115 is closer to the heavily doped region 119 and the contact plug 122, which can maintain a high breakdown voltage.

[0034] Figure 6 This is a cross-sectional schematic diagram of a semiconductor device 100 according to another embodiment of the present invention. In this embodiment, the contact plug 122 penetrates the source region 117 and the substrate region 115, and extends downward into the epitaxial layer 103, such that the lowest bottom surface 115B of the substrate region 115 is higher than the bottom surface 122B of the contact plug 122. A heavily doped region 119 is disposed directly below the contact plug 122, contacting the bottom of the contact plug 122, and both the heavily doped region 119 and the bottom of the contact plug 122 are embedded in the epitaxial layer 103. Furthermore, the lowest bottom surface 115B of the substrate region 115 can be flush with (e.g., ...). Figure 6 (As shown by the dashed line in the figure) or slightly below the highest top surface 107T of the shielding electrode 107. Figure 6 The deeper contact plugs 122 and the heavily doped regions 119 can increase the avalanche capability of the semiconductor device 100 while still meeting the requirement of reducing switching losses.

[0035] in addition, Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 Details of other features of the semiconductor device 100 can be found in the foregoing. Figure 1 The relevant explanations will not be repeated here. Figure 6In the semiconductor device 100, the drain potential of the substrate 101, which serves as the drain region, and the source potential of the source region 117 are at the same potential. Most of the current flows upward from the substrate 101 through the epitaxial layer 103 and into the heavily doped region 119 and the contact plug 122. The bottom of the contact plug 122 and the heavily doped region 119 are both buried in the epitaxial layer 103, so the current can be guided into the heavily doped region 119 and the contact plug 122 more effectively, thereby increasing the avalanche capability.

[0036] Figure 7 , Figure 8 and Figure 9 This is a cross-sectional schematic diagram of some stages of a method for manufacturing a semiconductor device 100 according to an embodiment of the present invention. Figure 1 The semiconductor device 100 is used as an example for illustration. (See also...) Figure 7 In step S101, a substrate 101 is provided, such as an N-type heavily doped silicon or silicon carbide substrate, and an epitaxial layer 103, such as an N-type silicon or silicon carbide epitaxial layer, is formed on the substrate 101 using an epitaxial growth process. In step S103, a trench 105 is etched in the epitaxial layer 103, extending downward from the top surface of the epitaxial layer 103. In step S105, an insulating layer 111, a shielding electrode 107, a dielectric layer 112, a gate dielectric layer 113, and a gate electrode 109 are formed within the trench 105 using a multi-pass deposition, etching, and planarization process, wherein the gate electrode 109 and the shielding electrode 107 are longitudinally separated via the dielectric layer 112, and the lowest bottom surface 109B of the gate electrode 109 is higher than the highest top surface 107T of the shielding electrode 107. In this embodiment, the gate electrode 109 has a flat bottom surface. In other embodiments, gate electrodes 109 of different shapes can be formed by adjusting the deposition and etching processes. In addition, the top surface of the gate electrode 109 is typically slightly lower than the top surface of the trench 105, and an oxide layer 114 may be deposited to fill the depression on the top surface of the gate electrode 109, while the oxide layer 114 may also cover the top surface of the epitaxial layer 103 and the gate dielectric layer 113 in the trench 105.

[0037] See Figure 8In step S107A, using a first-stage ion implantation 131, a dopant of a second conductivity type (e.g., P-type) is vertically implanted into the epitaxial layer 103, forming a first well region 115-1 at a first depth. The bottom surface of the first well region 115-1 may be flush with or slightly lower than the lowest bottom surface of the gate electrode 109. Next, in step S108A, using a second-stage ion implantation 132, a dopant of a second conductivity type (e.g., P-type) is vertically implanted into the epitaxial layer 103, forming a second well region 115-2 at a second depth. The first depth is greater than the second depth, and the second-stage ion implantation 132 allows the bottom surface of the first well region 115-1 to diffuse downwards to a depth greater than the first depth. Furthermore, the energy of the first-stage ion implantation 131 is greater than that of the second-stage ion implantation 132, and the dose of the second-stage ion implantation 132 can be equal to or less than the dose of the first-stage ion implantation 131. For example, the energy of the first-stage ion implantation 131 can be greater than or equal to approximately 100 keV, and the dose of the first-stage ion implantation 131 can be greater than approximately 1e12 ions / cm². 2 The energy of the second-stage ion implantation of 132 can be greater than or equal to about 30 keV, and the dose of the second-stage ion implantation of 132 can be greater than about 1e11 ions / cm. 2 However, this is not the only possibility. Then, in step S109A, a dopant-driven heat treatment is used to allow the dopants in the first well region 115-1 and the second well region 115-2 to diffuse downwards, forming a substrate region 115 (e.g., a P-type substrate region) adjacent to two adjacent sides of the two trenches 105, and the lowest bottom surface of the substrate region 115 may be flush with or slightly lower than the highest top surface 107T of the shielding electrode 107. The temperature of this heat treatment is, for example, greater than or equal to about 1000°C, and the time is, for example, greater than or equal to 20 minutes, but not limited to these. In this embodiment, a progressive implantation condition and a dopant-driven heat treatment are used to allow the lowest bottom surface of the substrate region 115 to reach the required depth. Furthermore, after the dopant-driven heat treatment, the substrate region 115 may have a substantially uniform or gradually varying doping concentration, wherein the doping concentration at the bottom of the substrate region 115 may be lighter or substantially the same as the doping concentration in other parts. Although this embodiment illustrates a two-stage ion implantation, it is not limited to this. In other embodiments, three or more stages of ion implantation may be performed, followed by a heat treatment to drive in the dopant, thereby allowing the formed substrate region 115 to have the desired depth and doping concentration distribution.

[0038] See Figure 9In step S111, a first conductivity type (e.g., N-type) dopant is implanted into the substrate region 115 using ion implantation, forming a source region 117 (e.g., a heavily doped N-type region) located on the top surface of the substrate region 115 and adjacent to the two adjacent side surfaces of the two trenches 105. In step S113, a dielectric layer 120 is deposited on the epitaxial layer 103, and then contact holes 121 are etched, extending downward into the substrate region 115 through the dielectric layer 120 and the source region 117. Next, a second conductivity type (e.g., P-type) dopant is implanted into the substrate region 115 directly below the bottom of the contact holes 121 using ion implantation, forming a heavily doped region 119 (e.g., a heavily doped P-type region). In step S115, using a deposition and planarization process, conductive metal is filled into the contact hole 121 to form a contact plug 122, which penetrates the source region 117 and extends downward into the substrate region 115, contacting the heavily doped region 119. Then, a backside metal layer is deposited below the bottom surface of the substrate 101 to form the drain electrode 124, completing the process. Figure 1 Semiconductor device 100.

[0039] in addition, Figure 7 , Figure 8 and Figure 9 The above-mentioned process steps can also be used to manufacture Figure 2 , Figure 3 , Figure 4 and Figure 6 Semiconductor device 100.

[0040] Figure 10 This is a cross-sectional schematic diagram of an intermediate stage in the manufacturing method of a semiconductor device 100 according to another embodiment of the present invention, which is based on... Figure 5 The semiconductor device 100 will be used as an example for illustration. (Continued) Figure 7 For step S105, please refer to Figure 10 In step S107B, using vertical ion implantation 133, a dopant of a second conductivity type (e.g., P-type) is implanted into the epitaxial layer 103 to form a third well region 115-3, extending downward from the top surface of the epitaxial layer 103 to a point slightly above the lowest bottom surface of the gate electrode 109. In step S108B, using tilted ion implantation 134, a dopant of a second conductivity type (e.g., P-type) is implanted into the epitaxial layer 103 to form a fourth well region 115-4, adjacent to two adjacent side surfaces of the two trenches 105, and the depth of the fourth well region 115-4 is greater than the depth of the third well region 115-3. Then, in step S109B, a dopant-driven heat treatment is used to allow the dopants in the third well region 115-3 and the fourth well region 115-4 to diffuse downwards, forming a substrate region 115 (e.g., a P-type substrate region). This substrate region 115 has an undulating bottom surface with the middle portion higher than the two side portions, and the lowest bottom surface of the two side portions of the substrate region 115 can be flush with or slightly lower than the highest top surface 107T of the shielding electrode 107. Afterwards, the process can continue. Figure 9 Steps S111, S113, and S115 are completed. Figure 5 The semiconductor device 100, wherein a heavily doped region 119 is formed directly above the middle portion of the substrate region 115.

Claims

1. A semiconductor device, characterized in that, include: A substrate having a first conductivity type; An epitaxial layer is disposed on the substrate and has the first conductivity type; A trench is formed in the epitaxial layer; A gate electrode and a shielding electrode are longitudinally separated and both are disposed in the trench, wherein a lowest bottom surface of the gate electrode is higher than a highest top surface of the shielding electrode. A substrate region is disposed in the epitaxial layer, adjacent to one side of the trench, and has a second conductivity type, wherein a lowest bottom surface of the substrate region is flush with or lower than the highest top surface of the shielding electrode. A source electrode region is disposed within the substrate region, located on the top surface of the substrate region, adjacent to the side surface of the trench, and has the first conductivity type; and A drain electrode is disposed below the substrate.

2. The semiconductor device as claimed in claim 1, characterized in that, The bottom of the gate electrode includes a flat bottom surface, a circular bottom surface, or a bottom surface with two undulating troughs.

3. The semiconductor device as claimed in claim 2, characterized in that, The shielding electrode is located directly below the protrusion on the arc-shaped bottom surface, or directly below a region between the two troughs of the undulating bottom surface.

4. The semiconductor device as claimed in claim 1, characterized in that, The gate electrode includes a first gate and a second gate that are laterally separated. The shielding electrode is located directly below a region between the first gate and the second gate. An inner side of the first gate is close to the second gate. In the vertical projection direction, a side of the shielding electrode is flush with the inner side of the first gate, or a portion of the first gate overlaps with the shielding electrode, and the overlapping portion is greater than 0% to 50% of the area of ​​the first gate.

5. The semiconductor device as claimed in claim 1, characterized in that, Also includes: Upon contact with the plug, it penetrates the source region and extends downwards into the substrate region; as well as A doped region is located directly below the contact plug, has the second conductivity type, and is embedded in the substrate region. The bottom of the substrate region includes a undulating bottom surface, which includes a middle portion, a first side portion and a second side portion. The middle portion is higher than the first side portion and the second side portion, and the middle portion is located directly below the heavily doped region. The lowest bottom surface of the substrate region is located between the first side portion and the second side portion of the undulating bottom surface.

6. The semiconductor device as claimed in claim 5, characterized in that, Both the contact plug and the shielding electrode are electrically coupled to a source voltage.

7. The semiconductor device as claimed in claim 1, characterized in that, Also includes: Upon contact with the plug, it penetrates the source region and the substrate region, and extends into the epitaxial layer; as well as A doped region is located directly below the contact plug, has the second conductivity type, and is embedded in the epitaxial layer.

8. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A gate dielectric layer is disposed within the trench, surrounding the side of the gate electrode; An insulating layer is disposed within the trench, surrounding the sides and bottom of the shielding electrode; as well as A dielectric layer is disposed between the gate electrode and the shielding electrode.

9. The semiconductor device as claimed in claim 8, characterized in that, The thickness of the insulating layer surrounding the side of the shielding electrode is greater than the thickness of the gate dielectric layer.

10. The semiconductor device as claimed in claim 1, characterized in that, The ratio of a maximum length of the gate electrode to a maximum depth of the substrate region is 2 / 3 to 4 / 5.

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