A silicon carbide power module and power electronic device

Abstract

This utility model relates to the field of silicon carbide power module technology, and discloses a silicon carbide power module and power electronic device. The silicon carbide power module includes multiple sets of power semiconductor chips and an insulating substrate, with multiple first chip placement areas and multiple second chip placement areas symmetrically arranged. Each first chip placement area mounts a set of power semiconductor chips. The source of the power semiconductor chip in the first chip placement area is connected to the drain pattern of the lower bridge arm through an upper bridge source connection line, and the gate is connected to the gate pattern of the upper bridge arm through an upper bridge gate connection line. Each second chip placement area also mounts a set of power semiconductor chips. The source of the power semiconductor chip in the second chip placement area is connected to the source pattern of the lower bridge arm through a lower bridge source connection line, and the gate is connected to the gate pattern of the lower bridge arm through a lower bridge gate connection line. This utility model can increase the chip spacing while maintaining the same common source inductance, thereby enhancing heat dissipation.

Description

Technical Field

[0001] This utility model relates to the field of silicon carbide power module technology, specifically to a silicon carbide power module and power electronic device. Background Technology

[0002] Silicon carbide (SiC) power modules are widely used in automotive, industrial, and power grid fields due to their low switching losses, high switching speeds, and high-temperature resistance, contributing to the miniaturization and weight reduction of electronic systems. However, the current-carrying capacity of a single SiC chip is limited. To achieve high integration and high-power applications, power modules typically employ multiple power semiconductor chips in parallel packaging. The parallel arrangement of multiple power semiconductor chips places higher demands on current sharing and heat dissipation, making the layout design of high-parallel power modules crucial.

[0003] Currently, the internal layout design of most high-parallel power modules typically falls into two categories. One involves placing power semiconductor chips in a single row, resulting in an asymmetrical internal chip layout and significant differences in commutation loop paths. This leads to uneven current distribution among the parallel chips, causing the module to operate at a derating rate. Furthermore, using a highly symmetrical, compact, and flat arrangement of power semiconductor chips can easily cause the temperature of the central thermal coupling area to be higher than that of the peripheral parallel chips, thus affecting the power module's lifespan. Additionally, it increases the design complexity of the power module and reduces its power density. Utility Model Content

[0004] In view of this, the present invention provides a silicon carbide power module and power electronic device to improve the problem of difficulty in heat dissipation while ensuring current sharing of parallel chips.

[0005] In a first aspect, this utility model provides a silicon carbide power module, which includes multiple sets of power semiconductor chips and an insulating substrate. Each set of power semiconductor chips includes at least one power semiconductor chip. The insulating substrate includes an upper bridge arm drain pattern, an upper bridge arm gate pattern, an upper bridge arm gate terminal pattern, a lower bridge arm drain pattern, a lower bridge arm source pattern, and a lower bridge arm gate pattern. The upper bridge arm drain pattern includes multiple first chip placement areas, and the lower bridge arm drain pattern includes multiple second chip placement areas. The multiple first chip placement areas and the multiple second chip placement areas are symmetrically arranged. Each first chip placement area is fitted with a set of power semiconductor chips, and the source of the power semiconductor chip located in the first chip placement area is connected to the lower bridge arm drain through an upper bridge source connection line. In the pattern, the gate of the power semiconductor chip located in the first chip placement area is connected to the upper bridge arm gate pattern through the upper bridge gate connection line. The upper bridge arm gate pattern and the upper bridge arm gate terminal pattern are connected by bonding wires. The lower bridge arm drain pattern is provided with the upper bridge arm source terminal, and the upper bridge arm gate terminal pattern is provided with the upper bridge arm gate signal terminal. Each second chip placement area is also equipped with a set of power semiconductor chips. The source of the power semiconductor chip located in the second chip placement area is connected to the lower bridge arm source pattern through the lower bridge source connection line. The gate of the power semiconductor chip located in the second chip placement area is connected to the lower bridge arm gate pattern through the lower bridge gate connection line. The lower bridge arm source pattern is provided with the lower bridge arm source terminal, and the lower bridge arm gate pattern is provided with the lower bridge arm gate signal terminal.

[0006] In this embodiment, the parallel connection of multiple chips with high symmetry satisfies the requirements of consistent current paths and short loops, which is beneficial to improving the current sharing characteristics of the power module. Simultaneously, by optimizing the layout of the metallization patterns on the insulating substrate, the chip mounting area can be increased. This allows for a layout design with increased chip spacing while maintaining high integration, alleviating the thermal coupling problem caused by the parallel connection of multiple chips and achieving thermal decoupling, thereby enhancing the module's heat dissipation. In other words, the silicon carbide power module provided in this embodiment can increase chip spacing while maintaining the same common-source inductance, thus achieving enhanced heat dissipation.

[0007] In one alternative implementation, multiple power semiconductor chips are spaced apart, with the sources of two adjacent power semiconductor chips in the horizontal direction in each group of power semiconductor chips being close to each other, and the gates of two adjacent power semiconductor chips in the horizontal direction in each group being far apart.

[0008] In one alternative implementation, the horizontal spacing between two adjacent power semiconductor chips in each group of power semiconductor chips is greater than or equal to 3 mm.

[0009] In one optional embodiment, the upper bridge source connection line of the first power semiconductor chip is inclined towards the second power semiconductor chip on the lower bridge arm drain pattern, and the upper bridge gate connection line of the first power semiconductor chip is inclined towards the second power semiconductor chip on the upper bridge arm gate pattern. The first power semiconductor chip and the second power semiconductor chip are two power semiconductor chips located in the first chip placement area and arranged opposite to each other. The lower bridge source connection line of the third power semiconductor chip is inclined towards the fourth power semiconductor chip on the lower bridge arm source pattern, and the lower bridge gate connection line of the third power semiconductor chip is inclined towards the fourth power semiconductor chip on the lower bridge arm gate pattern. The third power semiconductor chip and the fourth power semiconductor chip are two power semiconductor chips located in the second chip placement area and arranged opposite to each other.

[0010] In this embodiment, based on the symmetrical wide-spacing distribution layout of the chips, a special bonding wire arc torsion design is adopted. By adjusting the bonding wire length on the source side of the parallel chips and the current flow path on the source side of the parallel chips, the consistency of the common source inductance of the parallel chips can be guaranteed, and the current sharing of the parallel chips can be achieved. This solves the problems of uneven current distribution and high design complexity of silicon carbide power modules.

[0011] In one optional embodiment, the difference between the first spacing and the second spacing is less than a preset spacing, and the difference between the third spacing and the fourth spacing is less than the preset spacing; wherein, the first spacing is the horizontal distance between the connection point of the upper bridge arm source terminal and the upper bridge source connection line and the lower bridge drain pattern of the first power semiconductor chip, the second spacing is the horizontal distance between the connection point of the upper bridge arm source terminal and the upper bridge source connection line and the lower bridge drain pattern of the second power semiconductor chip, the third spacing is the horizontal distance between the lower bridge arm source terminal and the lower bridge source connection line and the lower bridge source pattern of the third power semiconductor chip, and the fourth spacing is the horizontal distance between the lower bridge arm source terminal and the lower bridge source connection line and the lower bridge source pattern of the fourth power semiconductor chip.

[0012] In one alternative implementation, the power semiconductor chip is an insulated gate bipolar transistor or a metal-oxide-semiconductor field-effect transistor.

[0013] In one optional embodiment, the silicon carbide power module further includes a thermistor, and the insulating substrate further includes a thermistor pattern. The thermistor pattern is provided with two thermistor test terminals. The thermistor is mounted on the thermistor pattern, and its two ends are respectively connected to the two thermistor test terminals.

[0014] In one optional embodiment, there are multiple insulating substrates, and the silicon carbide power module also includes a housing and a metal heat sink base plate; the multiple insulating substrates are fixedly disposed on the metal heat sink base plate at intervals, and the metal heat sink base plate, the insulating substrates and multiple sets of power semiconductor chips are all located inside the housing.

[0015] In one optional implementation, the upper bridge source connection line, the upper bridge gate connection line, the lower bridge source connection line, and the lower bridge gate connection line are all aluminum wires or copper wires.

[0016] Secondly, the present invention provides a power electronic device, including at least one silicon carbide power module according to the first aspect above or any corresponding embodiment thereof. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this utility model, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a silicon carbide power module according to an embodiment of the present utility model; Figure 2 This is a schematic diagram of the structure of an insulating substrate according to an embodiment of the present utility model; Figure 3 This is a schematic diagram of a structure in which eight parallel power semiconductor chips are disposed on an insulating substrate according to an embodiment of the present invention; Figure 4 This is a schematic diagram of a structure in which six parallel power semiconductor chips are disposed on an insulating substrate according to an embodiment of the present invention; Figure 5a This is a schematic diagram of a structure in which four parallel power semiconductor chips are disposed on an insulating substrate according to an embodiment of the present invention; Figure 5b This is a schematic diagram of a structure in which four parallel power semiconductor chips are disposed on an insulating substrate according to another embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of a power semiconductor chip according to an embodiment of the present utility model; Figure 7 This is a schematic diagram of the equivalent circuit corresponding to a power semiconductor chip according to an embodiment of the present utility model; Figure 8 This is a schematic diagram illustrating the effect of chip spacing on the thermal resistance of a silicon carbide power module according to an embodiment of the present invention. Figure 9 This is a schematic diagram of the electrical connections of a power semiconductor chip according to an embodiment of the present invention; Figure 10 This is a schematic diagram of the parasitic inductance of an equivalent model of a power semiconductor single transistor according to an embodiment of the present invention; Figure 11 This is a schematic diagram of the structure of another insulating substrate according to an embodiment of the present utility model; Figure 12 This is a schematic diagram of a power semiconductor chip disposed on an insulating substrate according to another embodiment of the present invention; Figure 13 This is a schematic diagram of the overall planar structure of a silicon carbide power module according to an embodiment of the present utility model.

[0019] Reference numerals: 100, Insulating substrate; 101, Intermediate insulating layer; 102, Upper bridge arm drain pattern; 1021, First chip placement area; 103, Lower bridge arm drain terminal pattern; 104, Lower bridge arm source pattern; 105, Lower bridge arm gate pattern; 106, Lower bridge arm drain pattern; 1061, Second chip placement area; 107, Thermistor pattern; 108, Upper bridge arm gate pattern; 109, Upper bridge arm gate terminal pattern; 110, Upper bridge arm drain terminal pattern; 111, Lower bridge arm drain terminal; 112, Lower bridge arm source terminal; 113, Lower bridge arm gate terminal; 114, Upper bridge arm drain terminal; 115, Upper bridge arm gate terminal; 116, Upper bridge arm source terminal; 117 1. Thermistor test terminal; 200. Power semiconductor chip; 201. Source; 202. Gate; 203. Drain; 300. Upper bridge source connection line; 301. First upper bridge source connection line; 302. Second upper bridge source connection line; 400. Upper bridge gate connection line; 401. First upper bridge gate connection line; 402. Second upper bridge gate connection line; 500. Bonding wire; 600. Lower bridge source connection line; 601. First lower bridge source connection line; 602. Second lower bridge source connection line; 700. Lower bridge gate connection line; 701. First lower bridge gate connection line; 702. Second lower bridge gate connection line; 800. Thermistor; 901. Housing; 902. Metal heat sink base plate. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the protection scope of this utility model.

[0021] Power semiconductor devices are the foundation of power electronics and the core components of various converters, widely used in inverter systems, power conversion systems, and frequency conversion and voltage transformation systems. Power modules assemble multiple or groups of power semiconductor chips into a single package, forming a circuit topology that meets requirements. They offer excellent heat dissipation and electrical characteristics, while also improving system integration and reducing subsequent assembly complexity.

[0022] Among them, the power semiconductor chip can be an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET), etc.

[0023] Power modules are a type of power semiconductor product commonly used in high-power power electronic systems. They generally consist of power semiconductor chips, insulating substrates, support base plates, housings, connection terminals, bonding wires, and potting materials. Power modules can form different circuit topologies through different metallization patterns, bonding wires, and connection terminals on the insulating substrate to achieve specific functions (such as conversion between different types of power supplies, power amplification, etc.).

[0024] With advancements in the automotive, industrial, and power grid sectors, higher performance requirements are being placed on power modules used in these applications. Power modules are increasingly evolving towards higher power density and higher reliability. Traditional silicon-based power modules are gradually failing to meet the high power density demands of high-power applications. In contrast, wide-bandgap semiconductor devices, such as silicon carbide power modules, offer more advantages and are attracting increasing attention due to their superior high-frequency, high-voltage, and high-temperature performance.

[0025] However, most silicon carbide power modules still use the packaging technology of traditional silicon-based modules, thus failing to fully utilize the superior characteristics of silicon carbide power devices.

[0026] Among these, the most critical issue is parasitic inductance. The faster switching frequency of silicon carbide can easily cause higher voltage / current waveform oscillations in the power module, resulting in higher voltage spikes. This not only increases the losses of power semiconductor devices but also increases the voltage stress on the devices, accelerates degradation, and increases the risk of failure.

[0027] Furthermore, silicon carbide power modules also suffer from parallel current sharing issues. Specifically, the current carrying capacity of a single silicon carbide chip is limited. To achieve the goals of high integration and high-power applications, power modules typically employ a parallel package of multiple power semiconductor chips. The parallel connection of multiple power semiconductor chips places higher demands on current sharing and heat dissipation, making the layout design of high-parallel power modules crucial.

[0028] Parallel circuits inevitably encounter the problem of uneven distribution of parasitic inductance parameters. Silicon carbide has a higher switching frequency, which, under the same layout conditions, will cause more severe imbalance between dynamic and static currents, resulting in unequal losses and voltage and current stresses, forcing the power module to operate at a derating rate and reducing reliability. Therefore, it is urgent to improve the current uniformity among parallel chips in power modules.

[0029] The high parallel silicon carbide power module layout also leads to certain heat dissipation issues. The high switching frequency of silicon carbide and the small size of silicon carbide chips result in a higher power loss density, making heat dissipation more challenging. To improve current sharing, power semiconductor chips are typically placed in a highly symmetrical and compact manner in the chip mounting area. The temperature in the central thermal coupling area is prone to being higher than that of the peripheral parallel chips, and the large temperature difference will affect the operating efficiency and lifespan of the power module.

[0030] To fully leverage the advantages of silicon carbide power devices, it is urgent to develop packaging and integration technologies with low parasitic inductance, high power density, and enhanced heat dissipation, while also addressing the issue of parallel current sharing, in order to better adapt to the performance of silicon carbide power devices and meet the practical application requirements of high current, high switching speed, high power density, high reliability, and high efficiency.

[0031] Currently, to address the thermal coupling problem of high parallel power modules, the layout design typically employs a single-row arrangement of chips, either horizontally or vertically. This can enhance heat dissipation to some extent, but single-row placement can lead to poor switching symmetry and significant differences in commutation circuit paths, resulting in a deterioration in the overall electrical performance of the high parallel power module.

[0032] Traditional power modules primarily achieve high-current conduction at the chip source through bonding wires. The longer the metal wire, the greater the parasitic inductance. In parallel multi-chip configurations, differences in parasitic inductance across different chip locations can lead to current sharing issues in power semiconductors. Current solutions to mitigate current distribution imbalances caused by asymmetrical parasitic inductance primarily include coupling inductors, source inductance compensation, and control drive turn-on / turn-off delays. However, these methods require additional components to be added to the existing system, increasing complexity and implementation difficulty. Alternatively, some designers have proposed a symmetrical circular copper-clad ceramic substrate layout to ensure consistent parasitic parameters in parallel circuits, thereby achieving current sharing among chips. However, this method lacks general applicability and is unsuitable for large-scale applications.

[0033] Therefore, silicon carbide power modules have the problem of difficulty in ensuring current sharing among parallel chips while also addressing heat dissipation.

[0034] In view of this, the present invention provides a silicon carbide power module that, through the parallel connection of multiple highly symmetrical chips, can meet the requirements of consistent current paths and short loops, which is beneficial to improving the current sharing characteristics of the silicon carbide power module. At the same time, by optimizing the layout of the metallization pattern on the insulating substrate, the chips can be placed separately with a certain distance between them, which can alleviate the thermal coupling problem caused by the parallel connection of multiple chips and achieve thermal decoupling.

[0035] The silicon carbide power module provided by this utility model will be described in detail below with reference to the accompanying drawings.

[0036] like Figure 1 , Figure 2 and Figure 3 As shown, the silicon carbide power module includes multiple sets of power semiconductor chips and an insulating substrate 100.

[0037] Each group of power semiconductor chips includes at least one power semiconductor chip 200. Figure 1 and Figure 3 Taking a group of power semiconductor chips consisting of four power semiconductor chips 200 as an example, but not limited to this. For example, the number of power semiconductor chips 200 in each group of power semiconductor chips can also be 1, 2 or 3, etc. Figures 1 to 3 Taking a silicon carbide power module comprising four groups of power semiconductor chips as an example, but not limited to this, a silicon carbide power module may include two groups of power semiconductor chips or six groups of power semiconductor chips, etc.

[0038] For example, the insulating substrate can be a double-sided copper-clad ceramic substrate (Direct Bond Copper, DBC), such as... Figure 2 As shown, the insulating substrate includes an intermediate insulating layer 101 and a copper foil layer bonded to the surface of the intermediate insulating layer 101 by a special process (such as high-temperature co-firing).

[0039] like Figure 2 As shown, the copper foil layer of the insulating substrate 100 can be divided into multiple metallized patterns. The multiple metallized patterns include an upper bridge arm drain pattern 102, an upper bridge arm gate pattern 108, an upper bridge arm gate terminal pattern 109, a lower bridge arm drain pattern 106, a lower bridge arm source pattern 104, and a lower bridge arm gate pattern 105. The upper bridge arm drain pattern 102 includes multiple first chip placement areas 1021, and the lower bridge arm drain pattern 106 includes multiple second chip placement areas 1061. The multiple first chip placement areas 1021 and the multiple second chip placement areas 1061 correspond one-to-one and are symmetrically arranged.

[0040] The total number of the first chip placement area 1021 and the second chip placement area 1061 is the same as the number of groups of power semiconductor chips, so as to Figure 1 For example, there are 2 first chip placement areas and 2 second chip placement areas. The two first chip placement areas are arranged symmetrically vertically, and the two second chip placement areas are also arranged symmetrically vertically. The first chip placement areas and the corresponding second chip placement areas are arranged symmetrically horizontally.

[0041] Specifically, the insulating substrate 100 also includes a lower bridge arm drain terminal pattern 103 and an upper bridge arm drain terminal pattern 110. For example... Figure 3 As shown, a lower bridge arm drain terminal 111 is provided on the lower bridge arm drain terminal pattern 103, a lower bridge arm source terminal 112 is provided on the lower bridge arm source terminal pattern 104, a lower bridge arm gate terminal 113 is provided on the lower bridge arm gate terminal pattern 105, an upper bridge arm drain terminal 114 is provided on the upper bridge arm drain terminal pattern 102 and the upper bridge arm drain terminal pattern 110, an upper bridge arm gate terminal 115 is provided on the upper bridge arm gate terminal pattern 109, and an upper bridge arm source terminal 116 is provided on the lower bridge arm drain terminal pattern 106.

[0042] For example, the power semiconductor chip can be an IGBT or a MOSFET (Metal-Oxide-Semiconductor). In this embodiment, a MOSFET is used as an example to illustrate the configuration of the power semiconductor chip.

[0043] The structure of a power semiconductor chip can be as follows: Figure 6 As shown, the equivalent circuit corresponding to the power semiconductor chip is as follows: Figure 7 As shown, the power semiconductor chip 200 includes a source (S) 201, a gate (G) 202, and a drain (D) 203. The source 201 and gate 202 are located on the surface of the power semiconductor chip 200, and the drain 203 is located on the bottom of the power semiconductor chip. When the power semiconductor chip 200 is an IGBT, the source 201 is equivalent to the emitter of the IGBT, and the drain 203 is equivalent to the collector of the IGBT.

[0044] like Figure 1 and Figure 3 As shown, each first chip placement area 1021 mounts a group of power semiconductor chips. The source of the power semiconductor chip 200 located in the first chip placement area 1021 is connected to the drain pattern 106 of the lower bridge arm via an upper bridge source connection line 300. The gate of the power semiconductor chip 200 located in the first chip placement area 1021 is connected to the gate pattern 108 of the upper bridge arm via an upper bridge gate connection line 400. The gate pattern 108 of the upper bridge arm and the gate terminal pattern 109 of the upper bridge arm are connected via bonding wires 500 to complete the transmission of gate signals. The power semiconductor chip located in the first chip placement area 1021 can be referred to as the upper bridge arm power semiconductor chip.

[0045] Each second chip placement area 1061 also mounts a set of power semiconductor chips. The source of the power semiconductor chip located in the second chip placement area 1061 is connected to the lower bridge arm source pattern 104 through the lower bridge source connection line 600, and the gate of the power semiconductor chip located in the second chip placement area 1061 is connected to the lower bridge arm gate pattern 105 through the lower bridge gate connection line 700 to complete the transmission of gate signals. Among them, the power semiconductor chip located in the second chip placement area 1061 can be referred to as the lower bridge arm power semiconductor chip.

[0046] At the same time, such as Figure 1 As shown, the external upper bridge arm drain (DC+) power terminal is connected to the upper bridge arm drain pattern 102, the external lower bridge arm source (DC-) power terminal is connected to the lower bridge arm source pattern 104, and the external lower bridge arm drain (AC+) power terminal is connected to the lower bridge arm drain pattern 106, thus bringing out the signal from the power semiconductor chip.

[0047] In this embodiment, the parallel connection of multiple chips with high symmetry satisfies the requirements of consistent current paths and short loops, which is beneficial to improving the current sharing characteristics of the power module. Simultaneously, by optimizing the layout of the metallization patterns on the insulating substrate, the chip mounting area can be increased. This allows for a layout design with increased chip spacing while maintaining high integration, alleviating the thermal coupling problem caused by the parallel connection of multiple chips and achieving thermal decoupling, thereby enhancing the module's heat dissipation. In other words, the silicon carbide power module provided in this embodiment can increase chip spacing while maintaining the same common-source inductance, thus achieving enhanced heat dissipation.

[0048] Specifically, thermal simulation results show that under the chip layout design of this utility model, thermal coupling is significantly reduced, thermal resistance is significantly reduced, heat dissipation is enhanced, which is conducive to improving the uniformity of chip temperature distribution and ensuring that the power chip operates stably at the required junction temperature.

[0049] In a silicon carbide power module, each half-bridge arm (upper or lower arm) contains an even number of power semiconductor chips, such as 200. Figure 3 As shown, each half-bridge arm can contain 8 power semiconductor chips 200, such as Figure 4 As shown, each half-bridge arm can also contain 6 power semiconductor chips 200, such as Figure 5a and Figure 5b As shown, each half-bridge arm can also contain four power semiconductor chips 200.

[0050] In each group of power semiconductor chips, the sources of two adjacent power semiconductor chips in the horizontal direction are close to each other, while the gates of two adjacent power semiconductor chips in the horizontal direction are far apart from each other.

[0051] Specifically, such as Figure 3 As shown, each power semiconductor chip in each group maintains a certain spacing and is placed in a vertical double-row layout. The sources of two adjacent power semiconductor chips in the horizontal direction are close to the inner side of the metallization pattern, and the gates of two adjacent power semiconductor chips in the horizontal direction are close to the outer side of the metallization pattern, ensuring that all power semiconductor chips in each group present a highly symmetrical layout during mounting.

[0052] It should be understood that the larger the spacing between two adjacent power semiconductor chips, the better the heat dissipation. To ensure heat dissipation, the minimum spacing between two adjacent power semiconductor chips can be determined by the designer based on the electrical characteristics of the power module (inductance, current sharing, etc.).

[0053] For example, the effect of chip spacing on the thermal resistance of a silicon carbide power module can be as follows: Figure 8 As shown, from Figure 8 It can be seen that in the range of 0mm to 6mm, the thermal resistance of the power module decreases rapidly as the spacing between parallel chips increases. After the spacing is greater than 6mm, the effect of reducing the thermal resistance of the power module gradually weakens as the spacing between parallel chips increases. When the spacing is greater than or equal to 30mm, the thermal coupling between parallel chips basically disappears, and the thermal resistance of two parallel chips is the same as that of a single chip.

[0054] In this embodiment, while ensuring that the overall size of the silicon carbide power module is consistent with that of commercially available modules, the chip spacing is increased as much as possible.

[0055] In one example, the horizontal spacing between two adjacent power semiconductor chips in each group is greater than or equal to 3 mm to ensure increased heat dissipation.

[0056] In some optional implementations, both the source and gate interconnects adopt a twisted arc layout, the connection between chip sources is perpendicular to the horizontal direction, the connection between chip gates is perpendicular to the horizontal direction, and the connection points of the bond lines between the chip sources, chip gates and the metallization pattern of the insulating substrate are twisted at a certain angle to ensure that the bond line connection points on the metallization pattern are as close as possible.

[0057] Specifically, the upper bridge source connection line of the first power semiconductor chip is inclined towards the second power semiconductor chip on the lower bridge arm drain pattern 106, and the upper bridge gate connection line of the first power semiconductor chip is inclined towards the second power semiconductor chip on the upper bridge arm gate pattern 108. The first power semiconductor chip and the second power semiconductor chip are two power semiconductor chips located in the first chip placement area and arranged opposite to each other.

[0058] Furthermore, the upper bridge source connection line of the second power semiconductor chip is inclined towards the first power semiconductor chip on the lower bridge arm drain pattern 106, and the upper bridge gate connection line of the second power semiconductor chip is inclined towards the first power semiconductor chip on the upper bridge arm gate pattern 108.

[0059] In other words, such as Figure 1 and Figure 9 As shown, the connection point of the first upper bridge source connection line 301 and the lower bridge arm drain pattern 106 is close to the connection point of the second upper bridge source connection line 302 and the lower bridge arm drain pattern 106. The connection point of the first upper bridge gate connection line 401 and the lower bridge arm gate pattern 105 is close to the connection point of the second upper bridge gate connection line 402 and the lower bridge arm gate pattern 105.

[0060] Specifically, the upper-bridge source connection line of the first power semiconductor chip is the first upper-bridge source connection line 301, the upper-bridge source connection line of the second power semiconductor chip is the second upper-bridge source connection line 302, the upper-bridge gate connection line of the first power semiconductor chip is the first upper-bridge gate connection line 401, and the upper-bridge gate connection line of the second power semiconductor chip is the second upper-bridge gate connection line 402. Figure 9 Taking the first power semiconductor chip as the power semiconductor chip located to the left of the first chip placement area 1021 and the second power semiconductor chip as the power semiconductor chip located to the right of the first chip placement area 1021 as an example.

[0061] Meanwhile, the lower bridge source connection line of the third power semiconductor chip is inclined towards the fourth power semiconductor chip on the lower bridge arm source pattern 104, and the lower bridge gate connection line of the third power semiconductor chip is inclined towards the fourth power semiconductor chip on the lower bridge arm gate pattern 105. The third power semiconductor chip and the fourth power semiconductor chip are two power semiconductor chips located in the second chip placement area and arranged opposite to each other.

[0062] Furthermore, the lower bridge source connection line of the fourth power semiconductor chip is inclined towards the direction of the third power semiconductor chip on the lower bridge arm source pattern 104, and the lower bridge gate connection line of the fourth power semiconductor chip is inclined towards the direction of the third power semiconductor chip on the lower bridge arm gate pattern 105.

[0063] In other words, such as Figure 1 and Figure 9 As shown, the connection point of the first lower bridge source connection line 601 and the lower bridge arm source pattern 104 is close to the connection point of the second lower bridge source connection line 602 and the lower bridge arm source pattern 104. The connection point of the first lower bridge gate connection line 701 and the lower bridge arm gate pattern 105 is close to the connection point of the second lower bridge gate connection line 702 and the lower bridge arm gate pattern 105.

[0064] Specifically, the lower-bridge source connection line of the third power semiconductor chip is the first lower-bridge source connection line 601, the lower-bridge source connection line of the fourth power semiconductor chip is the second lower-bridge source connection line 602, the lower-bridge gate connection line of the third power semiconductor chip is the first lower-bridge gate connection line 701, and the lower-bridge gate connection line of the fourth power semiconductor chip is the second lower-bridge gate connection line 702. Figure 9 Taking the third power semiconductor chip as the power semiconductor chip located to the left of the second chip placement area 1061 and the fourth power semiconductor chip as the power semiconductor chip located to the right of the second chip placement area 1061 as an example.

[0065] For example, the difference between the first spacing L1 and the second spacing L2 is less than the preset spacing, and the difference between the third spacing L3 and the fourth spacing L4 is less than the preset spacing. The preset spacing can be determined by the designer based on requirements; for example, the preset spacing can be 0.5mm, 0.2mm, or 0.1mm, etc.

[0066] Wherein, the first spacing L1 is the horizontal distance between the connection point of the upper bridge arm source terminal and the upper bridge source connection line of the first power semiconductor chip and the lower bridge arm drain pattern; the second spacing L2 is the horizontal distance between the connection point of the upper bridge arm source terminal and the upper bridge source connection line of the second power semiconductor chip and the lower bridge arm drain pattern; the third spacing L3 is the horizontal distance between the lower bridge arm source terminal and the lower bridge source connection line of the third power semiconductor chip and the lower bridge arm source pattern; and the fourth spacing L4 is the horizontal distance between the lower bridge arm source terminal and the lower bridge source connection line of the fourth power semiconductor chip and the lower bridge arm source pattern.

[0067] In this embodiment, the source and gate connection lines inside the silicon carbide module adopt a twisted arc layout of the bonding wires, which can achieve the consistency of the parasitic inductance parameters of the power source of the parallel silicon carbide chips, mainly the consistency of the common source inductance, thereby realizing the parallel current sharing of the upper bridge arm and the parallel current sharing of the lower bridge arm.

[0068] The packaging process of power modules introduces a certain amount of parasitic inductance. Taking the equivalent model of a single transistor as an example, for instance... Figure 10 As shown, the key parasitic inductance parameters mainly include the equivalent gate loop inductance L. G Drain inductance L D Source inductor L S and common source inductor L CS Among them, the common-source inductor, which is present in both the main power circuit and the gate drive circuit, has the most significant impact on the electrical characteristics of the silicon carbide power module.

[0069] Common-source inductance is considered to be the main cause of increased switching losses and damage to the switching characteristics of power devices. Common-source inductance mainly comes from the internal bonding wires of power semiconductor chips and is closely related to the length of the chip source terminal package connection line and the current flow path. The deviation of the common-source inductance of parallel chips is mainly caused by the different distances between the chip and the source terminal.

[0070] Specifically, there is a common-source parasitic inductance L between the upper bridge arm source terminal 116 and the first upper bridge source connection line 301. CS4 There is a common-source parasitic inductance L between the upper bridge arm source terminal 116 and the second upper bridge source terminal connection line 302. CS3 There is a common-source parasitic inductance L between the lower bridge arm source terminal 112 and the first lower bridge source terminal connection line 601. CS1 There is a common-source parasitic inductance L between the lower bridge arm source terminal 112 and the second lower bridge source terminal connection line 602. CS2 The bonding wires (source connection wires) employ a twisted arc design to ensure close proximity of the copper connection points. This helps maintain consistent current path lengths between the two connections and reduces parasitic inductance L shared by both sources. CS1 and L CS2 Differences and L CS3 and L CS4 The difference eliminates the influence of inductive coupling between the source power circuit and the common branch of the drive circuit of the parallel chips, thus achieving current sharing among the parallel chips. In other words, this embodiment can improve the uneven current problem caused by the difference in parasitic inductance of the common source of the parallel chips due to the increased chip spacing.

[0071] In this embodiment, based on the symmetrical wide-spacing distribution layout of the chips, a special bonding wire arc torsion design is adopted. By adjusting the bonding wire length on the source side of the parallel chips and the current flow path on the source side of the parallel chips, the consistency of the common source inductance of the parallel chips can be guaranteed, and the current sharing of the parallel chips can be achieved. This solves the problems of uneven current distribution and high design complexity of silicon carbide power modules.

[0072] For example, the silicon carbide power module also includes a thermistor 800, such as Figure 11 and Figure 12 As shown, the insulating substrate 100 also includes a thermistor pattern 107, which has two thermistor test terminals 117. A thermistor 800 is mounted on the thermistor pattern 107, and the two ends of the thermistor 800 are respectively connected to the two thermistor test terminals 117.

[0073] In this embodiment, the thermistor 800 is used to detect the temperature of the power semiconductor chip so that the external device (control device) can confirm the temperature of the power semiconductor chip and take corresponding measures to prevent the power semiconductor chip from overheating if the temperature exceeds the preset temperature.

[0074] like Figure 13 As shown, there are multiple insulating substrates 100, and the silicon carbide power module also includes a housing 901 and a metal heat sink base 902.

[0075] Specifically, multiple insulating substrates 100 are fixedly arranged at intervals on a metal heat sink base plate 902, and the metal heat sink base plate 902, the insulating substrates 100 and multiple sets of power semiconductor chips are all located inside the housing 901.

[0076] For example, the upper bridge source connection line 300, the upper bridge gate connection line 400, the lower bridge source connection line 600, and the lower bridge gate connection line 700 can all be aluminum wires or copper wires.

[0077] Specifically, the connection methods between power semiconductor chips, passive devices and metallized patterns can be silver paste bonding, solder paste reflow soldering, silver sintering and other mounting processes; the connection methods between the upper surface of the power semiconductor chip and the metallized pattern can be wire bonding (aluminum wire, copper wire, aluminum strip) and copper sheet welding and other processes, without increasing the complexity of the module assembly process.

[0078] This utility model also provides a power electronic device, which includes the silicon carbide power module provided in any of the above embodiments.

[0079] Specifically, power electronic devices can be inverter systems, power conversion systems, or frequency conversion and voltage transformation systems, etc.

[0080] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicate the orientation or positional relationship according to the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0081] In this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0082] In the description of this specification, the terms "this embodiment," "an embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0083] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this utility model, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0084] Although embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the present invention.

Claims

1. A silicon carbide power module, characterized in that, The silicon carbide power module includes multiple sets of power semiconductor chips and an insulating substrate. Each set of power semiconductor chips includes at least one power semiconductor chip. The insulating substrate includes an upper bridge arm drain pattern, an upper bridge arm gate pattern, an upper bridge arm gate terminal pattern, a lower bridge arm drain pattern, a lower bridge arm source pattern, and a lower bridge arm gate pattern. The upper bridge arm drain pattern includes multiple first chip placement areas, and the lower bridge arm drain pattern includes multiple second chip placement areas. The multiple first chip placement areas and the multiple second chip placement areas are symmetrically arranged. Each of the first chip placement areas is equipped with a set of power semiconductor chips. The source of the power semiconductor chip located in the first chip placement area is connected to the drain pattern of the lower bridge arm through an upper bridge source connection line. The gate of the power semiconductor chip located in the first chip placement area is connected to the upper bridge arm gate pattern through an upper bridge gate connection line. The upper bridge arm gate pattern and the upper bridge arm gate terminal pattern are connected by bonding wires. The drain pattern of the lower bridge arm is provided with an upper bridge arm source terminal. The upper bridge arm gate terminal pattern is provided with an upper bridge arm gate signal terminal. Each of the second chip placement areas is also equipped with a set of power semiconductor chips. The source of the power semiconductor chip located in the second chip placement area is connected to the lower bridge arm source pattern through the lower bridge source connection line. The gate of the power semiconductor chip located in the second chip placement area is connected to the lower bridge arm gate pattern through the lower bridge gate connection line. The lower bridge arm source pattern is provided with a lower bridge arm source terminal, and the lower bridge arm gate pattern is provided with a lower bridge arm gate signal terminal.

2. The silicon carbide power module according to claim 1, characterized in that, The power semiconductor chips are spaced apart, with the sources of two adjacent power semiconductor chips in the horizontal direction in each group of power semiconductor chips being close to each other, and the gates of two adjacent power semiconductor chips in the horizontal direction being far apart.

3. The silicon carbide power module according to claim 2, characterized in that, In each group of power semiconductor chips, the horizontal spacing between two adjacent power semiconductor chips is greater than or equal to 3 mm.

4. The silicon carbide power module according to any one of claims 2 or 3, characterized in that, The upper bridge source connection line of the first power semiconductor chip is inclined towards the direction of the second power semiconductor chip on the lower bridge arm drain pattern, and the upper bridge gate connection line of the first power semiconductor chip is inclined towards the direction of the second power semiconductor chip on the upper bridge arm gate pattern. The first power semiconductor chip and the second power semiconductor chip are two power semiconductor chips located in the first chip placement area and arranged opposite to each other. The lower bridge source connection line of the third power semiconductor chip is inclined towards the fourth power semiconductor chip on the lower bridge arm source pattern, and the lower bridge gate connection line of the third power semiconductor chip is inclined towards the fourth power semiconductor chip on the lower bridge arm gate pattern. The third power semiconductor chip and the fourth power semiconductor chip are two power semiconductor chips located in the second chip placement area and arranged opposite each other.

5. The silicon carbide power module according to claim 4, characterized in that, The difference between the first spacing and the second spacing is less than the preset spacing, and the difference between the third spacing and the fourth spacing is less than the preset spacing; Wherein, the first spacing is the horizontal distance between the connection point of the upper bridge arm source terminal and the upper bridge source connection line and the lower bridge drain pattern of the first power semiconductor chip; the second spacing is the horizontal distance between the connection point of the upper bridge arm source terminal and the upper bridge source connection line and the lower bridge drain pattern of the second power semiconductor chip; the third spacing is the horizontal distance between the lower bridge arm source terminal and the lower bridge source connection line and the lower bridge source pattern of the third power semiconductor chip; and the fourth spacing is the horizontal distance between the lower bridge arm source terminal and the lower bridge source connection line and the lower bridge source pattern of the fourth power semiconductor chip.

6. The silicon carbide power module according to any one of claims 1 to 3, characterized in that, The power semiconductor chip is an insulated gate bipolar transistor or a metal-oxide-semiconductor field-effect transistor.

7. The silicon carbide power module according to any one of claims 1 to 3, characterized in that, The silicon carbide power module also includes a thermistor, and the insulating substrate also includes a thermistor pattern. The thermistor pattern has two thermistor test terminals. The thermistor is mounted on the thermistor pattern, and its two ends are respectively connected to the two thermistor test terminals.

8. The silicon carbide power module according to any one of claims 1 to 3, characterized in that, The number of insulating substrates is multiple, and the silicon carbide power module also includes a housing and a metal heat sink base plate; Multiple insulating substrates are spaced apart on the metal heat sink base plate, and the metal heat sink base plate, insulating substrates and multiple sets of power semiconductor chips are all located inside the housing.

9. The silicon carbide power module according to any one of claims 1 to 3, characterized in that, The upper bridge source connection line, upper bridge gate connection line, lower bridge source connection line, and lower bridge gate connection line are all made of aluminum or copper wire.

10. A power electronic device, characterized in that, It includes at least one silicon carbide power module as claimed in any one of claims 1 to 9.

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