Array substrate and display panel

Abstract

The application provides an array substrate and a display panel. The array substrate comprises an active layer and a source-drain layer. The active layer comprises an active part, and the active part comprises a channel part and a doped part connected to the channel part. The source-drain layer is arranged on the active layer, and the source-drain layer comprises a conductive part. A plurality of first holes are arranged in the doped part, and the conductive part is arranged in the plurality of first holes, so that the conductive part is in contact with the surface of the doped part close to the source-drain layer and the sidewall of the first hole. In this way, the contact area of the conductive part and the doped part can be increased, the contact impedance of the conductive part and the doped part can be reduced, and the stability of the array substrate can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] Flat panel displays, such as liquid crystal displays (LCDs), are widely used in various consumer electronics products, including mobile phones, televisions, personal digital assistants (PDAs), digital cameras, laptops, and desktop computers, due to their advantages such as high image quality, energy saving, thin body, and wide range of applications. They have become the mainstream display panels.

[0003] To achieve the requirements of reduced metal impedance and narrow bezels without adding additional photomasks, the outer metal traces are typically placed in the bottom light-shielding layer. Deep vias are then created in the insulating layer above the light-shielding layer to connect the outer metal traces to signal lines in other conductive layers. To allow the deep and shallow vias to share a single photomask, the doped portion of the active layer is usually penetrated through the vias. The source and drain electrodes form a ring contact with the doped portion through the vias, reducing the contact area between the source / drain electrodes and the doped portion, increasing the contact impedance, and consequently decreasing the stability of the array substrate.

[0004] Therefore, it is necessary to provide an array substrate and a display panel to improve this defect. Utility Model Content

[0005] This application provides an array substrate and a display panel, which can improve the stability of the array substrate. To achieve the above objective, according to a first aspect of this application, an array substrate is provided, comprising:

[0006] An active layer includes an active portion, the active portion including a channel portion and a doped portion connected to the channel portion; and

[0007] A source / drain layer is disposed on the active layer, and the source / drain layer includes conductive portions;

[0008] The doped portion is provided with a plurality of first holes, and the conductive portion is disposed in the plurality of first holes, such that the conductive portion contacts the surface of the doped portion near the source and drain layers and the sidewall of the first holes.

[0009] Optionally, the sidewall of the first hole is a continuously arranged inclined sidewall;

[0010] Wherein, the angle between the tangent at any point on the inclined sidewall and the reference plane is greater than or equal to 10 degrees and less than or equal to 80 degrees, and the reference plane is parallel to the light-emitting surface of the array substrate.

[0011] Optionally, the first hole includes:

[0012] First subsection; and

[0013] The second sub-part is disposed on the first sub-part;

[0014] In the direction from the active layer to the source / drain layer, the dimensions of the first sub-section and the second sub-section gradually increase, with the top dimension of the first sub-section being larger than the bottom dimension of the second sub-section.

[0015] Optionally, the first sub-part has a first inclined sidewall, wherein the angle between the tangent at any point on the first inclined sidewall and the reference plane is greater than or equal to 10 degrees and less than or equal to 80 degrees.

[0016] And / or, the second sub-part has a second inclined sidewall, the angle between the tangent at any point on the second inclined sidewall and the reference plane is greater than or equal to 10 degrees and less than or equal to 80 degrees, the reference plane being parallel to the light-emitting surface of the array substrate.

[0017] Optionally, the plurality of the first holes are arranged in a grid pattern.

[0018] Optionally, the doped portion includes:

[0019] Heavily doped regions; and

[0020] A lightly doped portion is connected between the heavily doped portion and the channel portion;

[0021] The heavily doped portion is provided with a plurality of the first holes.

[0022] Optionally, it also includes:

[0023] A gate insulating layer is disposed on the active layer;

[0024] A gate layer is disposed on the gate insulating layer; and

[0025] An interlayer dielectric layer is disposed on the gate layer and the gate insulating layer, and the source and drain layers are disposed on the interlayer dielectric layer;

[0026] The interlayer dielectric layer is provided with a second hole, which penetrates the interlayer dielectric layer and the gate insulating layer in the thickness direction of the array substrate. The size of the second hole is larger than the size of the first hole, and the conductive part contacts the doped part through the second hole.

[0027] Optionally, the orthographic projections of multiple first holes on the same doped portion onto a reference plane are located within the orthographic projections of the corresponding second hole on the reference plane, wherein the reference plane is parallel to the light-emitting surface of the array substrate.

[0028] Optionally, the shape of the first hole includes at least one of strip, circle and ellipse.

[0029] According to a second aspect of this application, a display panel is provided, comprising an array substrate as described above.

[0030] In the display panel of this application embodiment, by providing a plurality of first holes in the doped portion of the active portion and placing the conductive portion in the plurality of first holes, the conductive portion contacts the surface of the doped portion near the source and drain layers and the sidewall of the first hole. This increases the contact area between the conductive portion and the doped portion and reduces the contact impedance between the conductive portion and the doped portion, thereby improving the stability of the array substrate.

[0031] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0034] Figure 1 A schematic diagram of the film layer structure of the array substrate provided for an embodiment of this application;

[0035] Figure 2 A schematic diagram of the structure of the active layer in the array substrate provided for an embodiment of this application;

[0036] Figure 3 The active portion of the first array substrate provided in the embodiments of this application is along Figure 2 The cross-sectional view along the A-A' direction shown;

[0037] Figure 4 The active portion of the second array substrate provided in the embodiments of this application is along Figure 2 The cross-sectional view along the A-A' direction shown;

[0038] Figure 5 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0040] Embodiments of this application provide an array substrate including an active layer and a source-drain layer. The active layer includes an active portion, the active portion includes a channel portion and a doped portion connected to the channel portion. The source-drain layer is disposed on the active layer and includes a conductive portion. The doped portion has a plurality of first holes, and the conductive portion is disposed in the plurality of first holes, such that the conductive portion contacts the surface of the doped portion near the source-drain layer and the sidewall of the first hole.

[0041] In the embodiments of this application, by providing a plurality of first holes in the doped portion of the active portion and placing the conductive portion in the plurality of first holes, the conductive portion contacts the surface of the doped portion near the source and drain layers and the sidewall of the first hole. This increases the contact area between the conductive portion and the doped portion and reduces the contact impedance between the conductive portion and the doped portion, thereby improving the stability of the array substrate.

[0042] Combination Figure 1 and Figure 2 As shown, Figure 1 A schematic diagram of the film layer structure of the array substrate provided for an embodiment of this application. Figure 2 This is a schematic diagram of the active layer structure provided in an embodiment of this application. The display panel includes an active layer 13 and a source / drain layer 17. The active layer 13 includes an active portion 130, which includes a channel portion 131 and a doped portion 132 connected to the channel portion 131. The doped portion 132 has a plurality of first holes H1. The source / drain layer 17 is disposed on the active layer 13 and includes a conductive portion 171. The conductive portion 171 is disposed within the plurality of first holes H1, such that the conductive portion 171 contacts the surface of the doped portion 132 near the source / drain layer 17 and the sidewall of the first hole H1.

[0043] In this embodiment, by providing a plurality of first holes H1 in the doped portion 132 and placing the conductive portion 171 in the plurality of first holes H1, the conductive portion 171 is made to contact the surface of the doped portion 132 near the source-drain layer 17 and the sidewall of the first hole H1. This increases the contact area between the conductive portion 171 and the doped portion 132 and reduces the contact resistance between the conductive portion 171 and the doped portion 132.

[0044] In some embodiments, combined with Figure 1 and Figure 2As shown, the active layer 13 includes a plurality of patterned active portions 130. Each active portion 130 includes a channel portion 131 and two doped portions 132. The two doped portions 132 are respectively disposed on both sides of the channel portion 131 and are connected to the channel portion 131 to form an integral structure. The channel portion 131 and the doped portions 132 are different parts of the same active portion 130.

[0045] In some embodiments, at least one doped portion 132 in the active portion 130 is provided with a plurality of first holes H1. For example, the active portion 130 has two doped portions 132, wherein one doped portion 132 is provided with a plurality of first holes H1, and the source-drain layer 17 includes a plurality of patterned conductive portions 171, each conductive portion 171 being disposed within the corresponding plurality of first holes H1, wherein a portion of one conductive portion 171 contacts the surface of the doped portion 132 near the source-drain layer 17, and another portion of the conductive portion 171 extends into the plurality of first holes H1 and contacts the sidewall of the first hole H1, thereby increasing the contact area between the conductive portion 171 and the doped portion 132; the other doped portion 132 is not provided with openings, and the other conductive portion 171 only contacts the surface of the doped portion 132 near the source-drain layer 17.

[0046] In some embodiments, combined with Figure 1 and Figure 2 As shown, the doped portions 132 on both sides of the channel portion 131 are provided with a plurality of first holes H1. The first holes H1 penetrate the doped portion 132 in the thickness direction of the display panel. Taking any one of the doped portions 132 as an example, a part of the conductive portion 171 is disposed on the surface of the doped portion 132 near the source-drain layer 17 to form a surface contact with the doped portion 132. The other part of the conductive portion 171 extends into the plurality of first holes H1 and forms a ring contact with the sidewall of the first hole H1. In this way, the contact area between the conductive portion 171 and the doped portion 132 can be increased, and the contact resistance between the conductive portion 171 and the doped portion 132 can be reduced.

[0047] In some embodiments, the source-drain layer 17 includes a plurality of patterned conductive portions 171, the plurality of conductive portions 171 including a first conductive portion 1711 and a second conductive portion 1712. The first conductive portion 1711 is electrically connected to one of the doped portions 132 of the active portion 130, and the second conductive portion 1712 is electrically connected to another doped portion 132 of the same active portion 130. The first conductive portion 1711 and the second conductive portion 1712 can be regarded as the source and drain of a thin film transistor.

[0048] In some embodiments, the doped portion 132 is provided with three or more first holes H1, for example, the doped portion 132 may be provided with three, four or five or more first holes H1. By providing three or more first holes H1, the annular contact area between the conductive portion 171 and the side of the doped portion 132 can be increased, thereby reducing the contact resistance between the conductive portion 171 and the doped portion 132.

[0049] In some embodiments, such as Figure 2 As shown, multiple first holes H1 are arranged in a grid pattern.

[0050] In some embodiments, such as Figure 2 As shown, the shape of the first hole H1 includes at least one of strip shape, circle shape and ellipse shape. The shapes of multiple first holes H1 on the same doped part 132 can be the same. For example, the shapes of multiple first holes H1 on the same doped part 132 can all be circle shape. The shapes of multiple first holes H1 on the same doped part 132 can also be different. For example, some of the first holes H1 on the same doped part 132 are circle shape, some of the first holes H1 are ellipse shape, and the remaining first holes H1 are strip shape.

[0051] In some embodiments, combined with Figure 1 and Figure 2 As shown, the doped portion 132 includes a lightly doped portion 1321 and a heavily doped portion 1322. The lightly doped portion 1321 is connected between the heavily doped portion 1322 and the channel portion 131. The ion doping concentration of the heavily doped portion 1322 is greater than that of the lightly doped portion 1321. The heavily doped portion 1322 has a plurality of first holes H1, while the lightly doped portion 1321 does not have any openings. A portion of the conductive portion 171 is disposed on the surface of the heavily doped portion 1322 near the source-drain layer 17 and is in contact with the surface of the heavily doped portion 1322 near the source-drain layer 17. A portion of the conductive portion 171 is disposed within the plurality of first holes H1 and is in contact with the sidewall of the first hole H1, which is formed by the heavily doped portion 1322.

[0052] In some embodiments, combined with Figure 1 and Figure 2 As shown, the interlayer dielectric layer 16 is provided with a plurality of second holes H2. The second holes H2 penetrate the interlayer dielectric layer 16 and the gate insulating layer 14 in the thickness direction of the array substrate. The size of the second holes H2 is larger than the size of the first holes H1, so that the plurality of first holes H1 are exposed by opening the second holes H2. The conductive part 171 contacts the surface of the doped part 132 near the source and drain layer 17 through the second holes H2, and extends into the first holes H1 through the second holes H2, so as to contact the side of the doped part 132 exposed by the first holes H1.

[0053] It should be noted that the size of the first hole H1 refers to the diameter of the first hole H1, and the diameter of the second hole H2 refers to the diameter of the second hole H2.

[0054] In some embodiments, combined with Figure 1 and Figure 2 As shown, the orthographic projections of multiple first holes H1 on the same doped portion 132 onto the reference plane are located within the orthographic projections of the corresponding second holes H2 onto the reference plane, and the reference plane is parallel to the light-emitting surface of the display panel.

[0055] In some embodiments, such as Figure 3 As shown, Figure 3 The active portion of the first array substrate provided in the embodiments of this application is along Figure 2 The cross-sectional view along the A-A' direction shown shows that the sidewall of the first hole H1 is a continuously arranged inclined sidewall 132a, which can be an inclined plane or an arc surface.

[0056] In some embodiments, the tangent at any point on the inclined sidewall 132a has a first included angle α1 with the reference plane, the first included angle α1 being greater than or equal to 10 degrees and less than or equal to 80 degrees. For example, the first included angle α1 can be 10 degrees, 30 degrees, 45 degrees, 50 degrees, 70 degrees, or 80 degrees, etc.

[0057] It should be noted that if the first included angle a1 is too large, the slope of the inclined sidewall 132a will be too large, which is not conducive to the deposition of the conductive part 171 on the inclined sidewall 132a. The conductive part 171 is prone to poor coverage on the inclined sidewall 132a, resulting in thinning or even breakage, leading to poor contact performance between the conductive part 171 and the doped part 132. If the first included angle a1 is too small, not only will the process be difficult to achieve, but it will also increase the aperture of the first hole H1, reducing the contact area between the upper surfaces of the conductive part 171 and the doped part 132, resulting in increased contact resistance between the conductive part 171 and the doped part 132.

[0058] In this embodiment, by limiting the first included angle α1 between the tangent at any point on the inclined sidewall 132a of the first hole H1 and the reference plane to between 10 degrees and 80 degrees, it can not only ensure the film formation effect of the conductive part 171 on the inclined sidewall 132a and prevent the conductive part 171 from breaking, but also ensure that the contact area between the conductive part 171 and the upper surface of the doped part 132 is large enough to reduce the contact resistance between the conductive part 171 and the doped part 132.

[0059] In some embodiments, such as Figure 1As shown, the array substrate includes a substrate 10 and a light-shielding layer 11, a blocking layer 12, an active layer 13, a gate insulating layer 14, a gate layer 15, an interlayer dielectric layer 16, a source-drain layer 17, a planarization layer 18, a common electrode layer 19, a passivation layer 20, and a pixel electrode layer 21, which are sequentially stacked on the substrate 10.

[0060] In some embodiments, such as Figure 1 As shown, the light-shielding layer 11 is provided with a plurality of light-shielding portions 111. The orthogonal projection of the light-shielding portions 111 on the substrate 10 covers the orthogonal projection of the channel portion 131 of the active layer 13 on the substrate 10, so as to prevent light from shining on the channel portion 131 and causing the leakage current of the thin film transistor to increase, thereby improving the stability of the electrical performance of the thin film transistor.

[0061] In some embodiments, such as Figure 1 As shown, the light-shielding layer 11 includes multiple peripheral traces 112, which are located in the non-display area. The multiple peripheral traces 112 may include, but are not limited to, at least one of data lines, power lines, touch signal lines, and scan lines.

[0062] In some embodiments, the material of the light-shielding layer 11 includes at least one or more materials such as aluminum, copper, molybdenum and titanium, which are stacked together. Metal materials such as aluminum, copper, molybdenum and titanium have low impedance, which can reduce the resistance of the peripheral traces 112.

[0063] In some embodiments, the thickness of the light-shielding layer 11 is greater than or equal to 1000 angstroms. For example, the thickness of the light-shielding layer 11 can be 1000 angstroms, 1200 angstroms, 1400 angstroms, 1600 angstroms, 1800 angstroms, or 2000 angstroms. In this embodiment, by increasing the thickness of the light-shielding layer 11, the impedance of the peripheral trace 112 can be reduced, thereby improving the signal transmission capability of the peripheral trace 112.

[0064] In some embodiments, such as Figure 1 As shown, the gate layer 15 includes a plurality of patterned gates 151 and a plurality of first signal lines 152. The first signal lines 152 can be scan lines. The orthographic projection of the gates 151 on the substrate 10 overlaps with the orthographic projection of the channel portion 131 on the substrate 10.

[0065] In some embodiments, such as Figure 1 As shown, the source-drain layer 17 includes a touch signal line 172 and an auxiliary electrode 173, and the common electrode layer 19 includes a common electrode 191 and a touch electrode 192. The touch electrode 192 is electrically connected to the touch signal line 172 through a via on the planarization layer 18.

[0066] like Figure 1As shown, the auxiliary electrode 173 is electrically connected to the first signal line 152 in the gate layer 15 through the third hole H3. The third hole H3 is a shallow hole that penetrates the interlayer dielectric layer 16 in the thickness direction. The auxiliary electrode 173 is also electrically connected to the peripheral trace 112 in the light-shielding layer 11 through the fourth hole H4. The fourth hole H4 is a deep hole that penetrates the interlayer dielectric layer 16, the gate insulating layer 14, and the barrier layer 12 in the thickness direction. The third hole H3 and the fourth hole H4 can be fabricated simultaneously using the same photomask and the same patterning process.

[0067] In some embodiments, such as Figure 1 As shown, the first hole H1 penetrates the doped portion 132 and the barrier layer 12 located below the doped portion 132 in the thickness direction. In the actual process, a two-step gas etching method can be used for the dry etching process of the inorganic insulating layer. The etching endpoint interface between the first and second steps is selected as the interface between the active layer 13 and the gate insulating layer 14. The etching gas for the second step is selected as a gas with a low etching rate for the active layer 13, such as pentafluoroethane. The first step etching of the active layer 13 leaves micro-residues, and some areas of the active layer 13 are penetrated. Due to the small number of etched particles and the high selectivity in the second step, multiple first holes H1 are finally formed in a grid-like arrangement in the active layer 13.

[0068] In the embodiments of this application, by providing a plurality of first holes H1 in the doped portion 132 and placing the conductive portion 171 in the plurality of first holes H1, the contact area between the conductive portion 171 and the doped portion 132 can be increased, thereby reducing the contact resistance between the conductive portion 171 and the doped portion 132, so as to facilitate the simultaneous etching of deep holes and shallow holes using a single photomask.

[0069] In some embodiments, such as Figure 4 As shown, Figure 4 The active portion of the second array substrate provided in the embodiments of this application is along Figure 2 The cross-sectional view along the A-A' direction shown has a structure similar to... Figure 3The structure of the first array substrate shown is roughly the same, except that: the first hole H1 includes a first sub-part H11 and a second sub-part H12 disposed on the first sub-part H11. The first sub-part H11 and the second sub-part H12 are connected, and the centers of the first sub-part H11 and the second sub-part H12 coincide. In the direction from the active layer 13 to the source / drain layer 17, the dimensions of the first sub-part H11 and the second sub-part H12 gradually increase. The dimension of the first sub-part H11 refers to the aperture of the first sub-part H11, and the dimension of the second sub-part H12 refers to the aperture of the second sub-part H12. By gradually increasing the dimensions of the first sub-part H11 and the second sub-part H12, the cross-sectional shape of the first sub-part H11 and the second sub-part H12 in the cross-sectional view along the A-A' direction is an inverted trapezoid, so that the conductive part 171 can be formed on the sidewalls of the first sub-part H11 and the second sub-part H12, preventing cracks from forming in the conductive part 171.

[0070] In some embodiments, the top dimension of the first sub-part H11 is larger than the bottom dimension of the second sub-part (H12), and the sidewall of the first sub-part H11 is recessed inward relative to the sidewall of the second sub-part H12 to form a stepped portion at the top of the first sub-part H11 and the top of the second sub-part H12. This facilitates the deposition of the conductive portion 171 on the sidewalls of the first hole H11 and the second hole H12, prevents the conductive portion 171 from breaking, and ensures that the contact area between the conductive portion 171 and the upper surface and side surface of the doped portion 132 is large enough to reduce the contact resistance between the conductive portion 171 and the doped portion 132.

[0071] In some embodiments, such as Figure 4 As shown, the first sub-part H11 has a first inclined sidewall 132a1. The tangent at any point on the first inclined sidewall 132a1 forms a second angle a2 with the reference plane. The second angle a2 is greater than or equal to 10 degrees and less than or equal to 80 degrees. For example, the second angle a2 can be 10 degrees, 30 degrees, 45 degrees, 50 degrees, 70 degrees, or 80 degrees, etc.

[0072] In some embodiments, such as Figure 4 As shown, the second sub-part H12 has a second inclined sidewall 132a2. The tangent at any point on the second inclined sidewall 132a2 forms a third angle a3 with the reference plane. The third angle a3 is greater than or equal to 10 degrees and less than or equal to 80 degrees. For example, the third angle a3 can be 10 degrees, 30 degrees, 45 degrees, 50 degrees, 70 degrees, or 80 degrees, etc.

[0073] By limiting the second included angle a2 and the third included angle a3 to between 10 degrees and 80 degrees, this embodiment can not only ensure the film formation effect of the conductive part 171 on the sidewall of the first hole H1 and prevent the conductive part 171 from breaking, but also ensure that the contact area between the conductive part 171 and the upper surface of the doped part 132 and the sidewall of the first hole H1 is large enough to reduce the contact resistance between the conductive part 171 and the doped part 132.

[0074] Based on the array substrate provided in the above embodiments of this application, embodiments of this application also provide a display panel, combined with... Figure 5 As shown, Figure 5 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. The display panel 1000 includes an array substrate 100, a counter substrate 200, and a liquid crystal layer 300. The array substrate 100 and the counter substrate 200 are disposed at a distance from each other, and the liquid crystal layer 300 is disposed between the array substrate 100 and the counter substrate 200. The array substrate in the display panel provided in this application can be any of the array substrates provided in the above embodiments. This array substrate can achieve the same technical effects as the above embodiments in the embodiments of this application, and will not be described in detail here.

[0075] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide an array substrate and a display panel. The array substrate includes an active layer and a source-drain layer. The active layer includes an active portion, which includes a channel portion and a doped portion connected to the channel portion. The source-drain layer is disposed on the active layer and includes a conductive portion. By providing a plurality of first holes in the doped portion and disposing the conductive portion in the plurality of first holes, the conductive portion contacts the surface of the doped portion near the source-drain layer and the sidewall of the first hole H1. This increases the contact area between the conductive portion and the doped portion and reduces the contact impedance between the conductive portion and the doped portion.

[0076] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0077] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0078] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0079] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An array substrate, characterized in that, include: An active layer includes an active portion, the active portion including a channel portion and a doped portion connected to the channel portion; as well as A source / drain layer is disposed on the active layer, and the source / drain layer includes conductive portions; The doped portion is provided with a plurality of first holes, and the conductive portion is disposed in the plurality of first holes, such that the conductive portion contacts the surface of the doped portion near the source and drain layers and the sidewall of the first holes.

2. The array substrate as described in claim 1, characterized in that, The sidewall of the first hole is a continuously arranged inclined sidewall; Wherein, the angle between the tangent at any point on the inclined sidewall and the reference plane is greater than or equal to 10 degrees and less than or equal to 80 degrees, and the reference plane is parallel to the light-emitting surface of the array substrate.

3. The array substrate as described in claim 1, characterized in that, The first hole includes: First subsection; and The second sub-part is disposed on the first sub-part; In the direction from the active layer to the source / drain layer, the dimensions of the first sub-section and the second sub-section gradually increase, with the top dimension of the first sub-section being larger than the bottom dimension of the second sub-section.

4. The array substrate as described in claim 3, characterized in that, The first sub-part has a first inclined sidewall, and the angle between the tangent at any point on the first inclined sidewall and the reference plane is greater than or equal to 10 degrees and less than or equal to 80 degrees. And / or, the second sub-part has a second inclined sidewall, the angle between the tangent at any point on the second inclined sidewall and the reference plane is greater than or equal to 10 degrees and less than or equal to 80 degrees, the reference plane being parallel to the light-emitting surface of the array substrate.

5. The array substrate as described in any one of claims 1 to 4, characterized in that, The multiple first holes are arranged in a grid pattern.

6. The array substrate as described in any one of claims 1 to 4, characterized in that, The doped portion includes: Heavily doped regions; and A lightly doped portion is connected between the heavily doped portion and the channel portion; The heavily doped portion is provided with a plurality of the first holes.

7. The array substrate as described in any one of claims 1 to 4, characterized in that, Also includes: A gate insulating layer is disposed on the active layer; A gate layer is disposed on the gate insulating layer; as well as An interlayer dielectric layer is disposed on the gate layer and the gate insulating layer, and the source and drain layers are disposed on the interlayer dielectric layer; The interlayer dielectric layer is provided with a second hole, which penetrates the interlayer dielectric layer and the gate insulating layer in the thickness direction of the array substrate. The size of the second hole is larger than the size of the first hole, and the conductive part contacts the doped part through the second hole.

8. The array substrate as claimed in claim 7, characterized in that, The orthographic projections of multiple first holes on the same doped portion onto a reference plane are located within the orthographic projections of the corresponding second hole on the reference plane, and the reference plane is parallel to the light-emitting surface of the array substrate.

9. The array substrate as described in any one of claims 1 to 4, characterized in that, The shape of the first hole includes at least one of strip, circle and ellipse.

10. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 9.

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