Array substrate and display panel

Abstract

The utility model discloses an array substrate and display panel, this array substrate is through setting first active layer and second active layer, make array substrate can adopt low temperature polycrystal silicon thin film transistor and metal oxide thin film transistor, thereby give consideration to low power consumption, high switching speed, high mobility, low leakage etc. Advantage, and through make first electrode layer set up in source drain electrode layer close to first active layer's one side, first electrode layer and source drain electrode layer direct contact, then can make first electrode layer and insulating layer adopt same mask plate formation, reduce the quantity of required mask plate, and can reduce the insulating layer and conductive layer between first electrode layer and source drain electrode layer, further reduce the quantity of mask plate, improve preparation efficiency.

Description

Technical Field

[0001] This utility model relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] With the development of display devices, the requirements for thin-film transistors (TFTs) in existing display devices are becoming increasingly stringent. Metal-oxide-semiconductor (MOS) TFTs offer advantages such as high carrier mobility, low deposition temperature, and high transparency, but suffer from high power consumption and slow switching speeds. Low-temperature polysilicon (LTPS) TFTs, on the other hand, offer fast switching speeds and low power consumption, but have low mobility. Therefore, to improve TFT performance, existing display devices employ LTPO (Low Temperature Polysilicon Oxide) technology. Specifically, LTPO TFTs and MOS TFTs are fabricated simultaneously on the same backplane, combining the advantages of both to enhance display device performance. However, LTPO technology requires a large number of film layers, resulting in a higher number of photomasks. Furthermore, some display devices use transparent indium tin oxide (ITO) in direct contact with the first active layer within the display area to increase aperture ratio, further increasing the number of photomasks, leading to higher fabrication costs, more complex fabrication processes, and lower fabrication efficiency.

[0003] Therefore, existing display devices using LTPO technology suffer from the technical problem of relatively complex manufacturing processes leading to low manufacturing efficiency. Utility Model Content

[0004] This utility model provides an array substrate and a display panel to improve the technical problem of low manufacturing efficiency caused by the complex manufacturing process of existing display devices using LTPO technology.

[0005] To achieve the above objectives, according to a first aspect of the present invention, an array substrate is provided, the array substrate comprising: Substrate; A first active layer is disposed on one side of the substrate; The source and drain layers are disposed on the side of the first active layer away from the substrate; The second active layer is disposed on the side of the first active layer away from the substrate; The first electrode layer is disposed on the side of the source / drain layer close to the first active layer, and the first electrode layer is in direct contact with the source / drain layer.

[0006] According to a second aspect of the present invention, a display panel is provided, the display panel comprising an array substrate as described in any of the above embodiments.

[0007] This utility model provides an array substrate and a display panel. By setting a first active layer and a second active layer, the array substrate can use low-temperature polycrystalline silicon thin-film transistors and metal oxide thin-film transistors, thereby taking into account the advantages of low power consumption, high switching speed, high mobility, and low leakage current. Furthermore, by setting the first electrode layer on the side of the source-drain layer close to the first active layer, and the first electrode layer is in direct contact with the source-drain layer, the first electrode layer and the insulating layer can be formed using the same photomask, reducing the number of photomasks required. It can also reduce the number of insulating layers and conductive layers located between the first electrode layer and the source-drain layer, further reducing the number of photomasks and improving the fabrication efficiency.

[0008] Other features and advantages of this invention will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] To gain a more complete understanding of this utility model and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0010] Figure 1 A schematic diagram of a comparison display device provided in an embodiment of this utility model.

[0011] Figure 2 This is a schematic diagram of the array substrate provided in an embodiment of the present invention.

[0012] Figure 3 This is a schematic diagram of a display panel provided in an embodiment of the present utility model. Detailed Implementation

[0013] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without creative effort are within the protection scope of the present utility model.

[0014] To illustrate the principle behind the technical problems in the embodiments of this utility model, some comparative display devices are provided. It should be understood that these comparative display devices are not considered prior art in the embodiments of this utility model. Figure 1As shown, the comparative display device includes a substrate 111, a buffer film 112, a low-temperature polycrystalline silicon film 113, a first gate insulating film 114, a first metal film 115, a second gate insulating film 116, an indium gallium zinc oxide film 117, a third gate insulating film 118, a second metal film 119, a first interlayer insulating film 121, a third metal film 122, a second interlayer insulating film 123, a first indium tin oxide film 124, a third interlayer insulating film 125, a planarization film 126, a bottom electrode film 127, a passivation film 128, and a top electrode film 129. The low-temperature polycrystalline silicon film 113 is used to form a low-temperature polycrystalline silicon thin-film transistor, and the indium gallium zinc oxide film 117 is used to form a metal oxide thin-film transistor, thereby combining the advantages of low-temperature polycrystalline silicon thin-film transistors and metal oxide thin-film transistors, improving the performance of the display device. Furthermore, using the first indium tin oxide film 124 to connect the indium gallium zinc oxide film 117 can improve the aperture ratio.

[0015] But from Figure 1 As can be seen, 12 photomasks are required when forming a contrast display device. These photomasks are: one for forming a buffer film 112 and a low-temperature polysilicon film 113; one for forming a first gate insulating film 114 and a first metal film 115; one for forming a second gate insulating film 116 and an indium gallium zinc oxide film 117; one for forming a third gate insulating film 118 and a second metal film 119; one for forming a via of a first interlayer insulating film 121; one for forming a third metal film 122; one for forming a via of a second interlayer insulating film 123; one for forming a first indium tin oxide film 124; one for forming a via of a planarization film 126; one for forming a bottom electrode film 127; one for forming a passivation film 128; and one for forming a top electrode film 129. It is evident that the fabrication process of contrast display devices requires a large number of photomasks and involves numerous steps, resulting in a complex, costly, and inefficient fabrication process. Therefore, existing display devices employing LTPO technology suffer from the technical problem of complex fabrication processes leading to low fabrication efficiency.

[0016] This utility model provides an array substrate and a display panel to address the aforementioned technical problems.

[0017] like Figure 2As shown, this embodiment of the present invention provides an array substrate 2, which includes a substrate 211, a first active layer 213, a source-drain layer 217, a second active layer 219, and a first electrode layer 218. The first active layer 213 is disposed on one side of the substrate 211, the source-drain layer 217 is disposed on the side of the first active layer 213 away from the substrate 211, the second active layer 219 is disposed on the side of the first active layer 213 away from the substrate 211, and the first electrode layer 218 is disposed on the side of the source-drain layer 217 close to the first active layer 213. The first electrode layer 218 is in direct contact with the source-drain layer 217.

[0018] This utility model embodiment provides an array substrate; the array substrate 2, by setting a first active layer 213 and a second active layer 219, enables the array substrate to use low-temperature polycrystalline silicon thin-film transistors and metal oxide thin-film transistors, thereby taking into account the advantages of low power consumption, high switching speed, high mobility, and low leakage current; and by setting the first electrode layer 218 on the side of the source-drain layer 217 close to the first active layer 213, the first electrode layer 218 and the source-drain layer 217 are in direct contact, so that the first electrode layer 218 and the insulating layer can be formed using the same mask, reducing the number of masks required, and reducing the insulating layer and conductive layer located between the first electrode layer 218 and the source-drain layer, further reducing the number of masks and improving the fabrication efficiency of the array substrate.

[0019] Specifically, it can be understood that, compared to contrast display devices where planarization films and passivation films are provided between the first electrode layer and the source / drain layer, which requires etching the planarization film to form vias, resulting in a large number of photomasks and low fabrication efficiency, this embodiment of the invention allows the first electrode layer to be in direct contact with the source / drain layer 217, thus eliminating the need for a planarization film and reducing the number of film layers. Consequently, the need to etch the planarization film to form vias reduces the number of photomasks and improves fabrication efficiency. Furthermore, by placing the first electrode layer 218 on the side of the source / drain layer 217 close to the first active layer 213, compared to contrast display devices where a separate interlayer insulating film needs to be formed for the vias, this embodiment of the invention can use a single photomask to form the insulating layer vias and the first electrode layer, reducing the number of photomasks and improving the fabrication efficiency of the array substrate.

[0020] In some embodiments, such as Figure 2As shown, the second active layer 219 is disposed on the side of the source-drain layer 217 away from the first active layer 213. The source-drain layer 217 includes a first source 217a and a first drain 217b, which are spaced apart. The second active layer 219 is disposed between the first source 217a and the first drain 217b, and the second active layer 219 is in contact with the upper surfaces of the first source 217a and the first drain 217b. By placing the second active layer 219 on the side of the source / drain layer 217 away from the first active layer 213, the second active layer 219 can directly contact the first source 217a and the first drain 217b. There is no need to set an insulating layer between the source / drain layer 217 and the second active layer 219. Correspondingly, there is no need to form vias in the insulating layer between the source / drain layer 217 and the second active layer 219, thereby reducing the number of photomasks and improving the fabrication efficiency of the array substrate.

[0021] Specifically, compared to the contrast display device where a first interlayer insulating film 121 is provided between the indium gallium zinc oxide film 117 and the third metal film 122, requiring etching of the first interlayer insulating film 121 to form vias so that the third metal film 122 can connect with the indium gallium zinc oxide film 117, in this embodiment of the invention, by making the second active layer 219 directly contact the first source 217a and the first drain 217b, there is no need to set an insulating layer between the second active layer 219 and the source / drain layers 217, and therefore no need to etch the insulating layer to form vias, thereby reducing the number of photomasks and improving the fabrication efficiency of the array substrate.

[0022] Specifically, compared to the method used in contrast display devices where etching is required to form vias on the insulating layer of the indium gallium zinc oxide film 117, resulting in poor electrical stability of the indium gallium zinc oxide film 117, this embodiment of the invention places the second active layer 219 on the side of the source / drain layer 217 away from the substrate 211. This means that the surface of the second active layer 219 is not etched during its formation, resulting in better electrical stability. Furthermore, since the second active layer 219 is not etched, there is no need to design excessive process allowance for it, allowing for a reduction in its thickness and thus improving its electrical properties.

[0023] Specifically, the second active layer 219 includes a semiconductor pattern, which includes a conductor portion and a semiconductor portion. The semiconductor portion is disposed between the first source 217a and the first drain 217b, and the first source 217a and the first drain 217b are in contact with the conductor portions on both sides respectively.

[0024] Specifically, the conductivity of the conductor portion is better than that of the semiconductor portion.

[0025] In some embodiments, such as Figure 2 As shown, the first electrode layer 218 includes a first electrode 218a, which is in contact with one of the first source electrode 217a and the first drain electrode 217b, and there is a gap between the first electrode 218a and the second active layer 219. By making the first electrode 218a in contact with one of the first source electrode 217a and the first drain electrode 217b, the first electrode 218a does not need to be transferred to the second active layer 219 through other conductive layers, reducing the number of required photomasks and improving the fabrication efficiency of the array substrate.

[0026] Specifically, compared to the use of a first indium tin oxide film 124 to connect the indium gallium zinc oxide film 117 and the top electrode film 129 in contrast display devices, which requires setting and patterning the first indium tin oxide film 124, setting an insulating layer between the first indium tin oxide film 124 and the indium gallium zinc oxide film 117, and etching it to form vias, in this embodiment of the present invention, the first electrode 218a is in direct contact with one of the first source electrode 217a and the first drain electrode 217b, so that the first indium tin oxide film 124 is not required. Correspondingly, the insulating layer between the first indium tin oxide film 124 and the indium gallium zinc oxide film 117 is not required, and therefore, it is not necessary to etch it to form vias. This reduces the number of required photomasks and improves the fabrication efficiency of the array substrate.

[0027] Specifically, the above embodiment is illustrated by taking the first electrode 218a connected to the second active layer 219 via one of the first source electrode 217a and the first drain electrode 217b. However, the present invention is not limited to this. The source-drain layer 217 may include one of the first source electrode 217a and the first drain electrode 217b, such that one of the first source electrode 217a and the first drain electrode 217b is connected to a conductor portion on one side of the second active layer 219, and the first electrode 218a is connected to a conductor portion on the other side of the second active layer 219. The semiconductor portion of the second active layer 219 is disposed between one of the first source electrode 217a and the first drain electrode 217b and the first electrode 218a.

[0028] Specifically, it is understood that the source and drain are merely differentiating names for two electrodes connected to the second active layer 219 or the first active layer 213, and do not limit their potential levels or connection points. For example, in some naming conventions, the electrode connected to the first electrode 218a is named the drain, while in others, it is named the source. In some display devices, the potentials of the two electrodes change between positive and negative frames, such that in a positive frame, the electrode with the high / low potential is connected to the first electrode 218a, and in a negative frame, the electrode with the low / high potential is connected to the first electrode 218a. In this case, one of the two electrodes can be named the source / drain in a positive frame and the drain / source in a negative frame. Therefore, it is understood that the source and drain are only used to distinguish the two electrodes and do not limit their potentials or the connected electrodes or signal lines, which will not be elaborated further in the following embodiments.

[0029] In some embodiments, such as Figure 2 As shown, the array substrate 2 further includes a first gate insulating layer 214, a gate layer 215, and a second gate insulating layer 216. The first gate insulating layer 214 is disposed between the gate layer 215 and the first active layer 213. The gate layer 215 is disposed between the first gate insulating layer 214 and the second gate insulating layer 216. The second gate insulating layer 216 is disposed between the gate layer 215 and the source / drain layer 217. The first electrode layer 218 is in direct contact with the second gate insulating layer 216. By making the first electrode layer 218 and the second gate insulating layer 216 in direct contact, the pattern of the first electrode layer 218 can be formed simultaneously when etching the second gate insulating layer 216 to form vias. This allows the first electrode 218 and the second gate insulating layer 216 to be formed using the same photomask, thereby reducing the number of photomasks required and improving the fabrication efficiency of the array substrate.

[0030] Specifically, the gate layer 215 may include a first gate corresponding to the first active layer 213 and a second gate corresponding to the second active layer 219, so that the gate layer 215 can form the gate of a low-temperature polysilicon thin-film transistor and the gate of a metal oxide thin-film transistor, enabling each thin-film transistor to operate normally.

[0031] In some embodiments, such as Figure 2As shown, the source-drain layer 217 further includes a second source 217c and a second drain 217d. The second source 217c and the second drain 217d are connected to the first active layer 213 through a first via 216a. The first via 216a is spaced from the first electrode layer 218. By including the second source 217c and the second drain 217d in the source-drain layer 217, and connecting the second source 217c and the second drain 217d to the first active layer 213 through the first via 216a, the low-temperature polycrystalline silicon thin-film transistor can operate normally. Furthermore, by creating a gap between the first via 216a and the first electrode layer 218, the same photomask can be used to fabricate the first via 216a and the first electrode layer 218, thereby reducing the number of photomasks required and improving the fabrication efficiency of the array substrate.

[0032] Specifically, the material of the first active layer includes silicon semiconductors, specifically low-temperature polycrystalline silicon.

[0033] Specifically, the first via 216a can be a via that passes through the first gate insulating layer 214 and the second gate insulating layer 216, or it can be a via that passes through the second gate insulating layer 216.

[0034] Specifically, the first active layer may include a channel portion, a lightly doped portion, and a heavily doped portion. The lightly doped portion is disposed between the channel portion and the heavily doped portion, and the ion doping concentration of the lightly doped portion is greater than that of the channel portion and lower than that of the heavily doped portion.

[0035] Specifically, the second source 217c and the second drain 217d are connected to the heavily doped portion.

[0036] In some embodiments, such as Figure 2 As shown, the array substrate 2 further includes a passivation layer 231 and a second electrode layer 232. The passivation layer 231 is disposed on the side of the second active layer 219 away from the source / drain layer 217, and the second electrode layer 232 is disposed on the side of the passivation layer 231 away from the second active layer 219. The second electrode layer 232 passes through a second via 231c and contacts the source / drain layer 217. By connecting the second electrode layer 232 to the source / drain layer 217 through the second via 231c, there is no need to set planarization layers or other films, reducing the number of required photomasks and improving the fabrication efficiency of the array substrate.

[0037] Specifically, the second via 231c can be a via that passes through the passivation layer.

[0038] In some embodiments, such as Figure 2As shown, the passivation layer 231 includes a first sub-layer 231a and a second sub-layer 231b. The second sub-layer 231b is disposed between the first sub-layer 231a and the second electrode layer 232. The material of the first sub-layer 231a is different from that of the second sub-layer 231b. By including the first sub-layer 231a and the second sub-layer 231b in the passivation layer, and by making the materials of the first sub-layer 231a and the second sub-layer 231b different, the metal oxide thin-film transistor exhibits better electrical properties and can meet the storage capacitance requirements.

[0039] Specifically, the material of the first sublayer 231a can be silicon oxide, and the material of the second sublayer 231b can be silicon nitride.

[0040] Specifically, the thickness of the first sublayer 231a can be 300 angstroms to 1000 angstroms, and the thickness of the second sublayer 231b can be 1000 angstroms to 2000 angstroms.

[0041] In some embodiments, such as Figure 2 As shown, the thickness L1 of the second active layer 219 is 300 angstroms to 1000 angstroms; by making the thickness of the second active layer 219 range from 300 angstroms to 1000 angstroms, the thickness of the second active layer is smaller and the electrical performance is better.

[0042] Specifically, compared to the method used in contrast display devices where etching is required to form vias on the insulating layer of the indium gallium zinc oxide film 117, resulting in corrosion of the indium gallium zinc oxide film 117 and consequently poor electrical stability, thus necessitating a relatively large thickness for the indium gallium zinc oxide film 117, this embodiment of the invention places the second active layer 219 on the side of the source / drain layer 217 away from the substrate 211. This ensures that the surface of the second active layer 219 is not etched during its formation, resulting in better electrical stability. Furthermore, the second active layer 219 is not etched, eliminating the need for excessive process allowance and allowing for a reduction in its thickness, thus improving its electrical properties.

[0043] In some embodiments, the first active layer 213 is made of silicon semiconductor, and the second active layer 219 is made of oxide semiconductor. The array substrate 2 includes a display area 201 and a gate driving circuit area 202. The gate driving circuit area 202 is disposed on at least one side of the display area 201. The first active layer 213 is disposed on the gate driving circuit area 202, and the second active layer 219 is disposed on the display area 201. By disposing the first active layer 213 on the gate driving circuit area, the transistors in the gate driving circuit area are formed using silicon semiconductor, resulting in faster switching speeds and lower power consumption, thus enabling faster transistor activation. By using oxide semiconductor for the transistors in the display area, the transistors in the display area have higher mobility and lower leakage current, avoiding display defects caused by leakage current. This combines the advantages of low-temperature polycrystalline silicon thin-film transistors and metal oxide thin-film transistors, improving the performance of the array substrate.

[0044] Specifically, the material of the first active layer 213 can be silicon semiconductor, specifically low-temperature polycrystalline silicon; the material of the second active layer 219 is oxide semiconductor, specifically metal oxide, and more specifically, indium gallium zinc oxide.

[0045] Specifically, when setting the first active layer and the second active layer, the first active layer can be set in the gate driving circuit area and the second active layer can be set in the display area. However, the present invention is not limited to this. The first active layer can be set in both the gate driving circuit area and the display area, and the second active layer can be set in the display area.

[0046] Specifically, such as Figure 2 As shown, the array substrate 2 includes a substrate 211, a buffer layer 212, a first active layer 213, a first gate insulating layer 214, a gate layer 215, a second gate insulating layer 216, a first electrode layer 218, a source / drain layer 217, a second active layer 219, a passivation layer 231, and a second electrode layer 232 arranged sequentially.

[0047] Specifically, the first electrode layer 218 may include pixel electrodes, and the second electrode layer 232 may include common electrodes.

[0048] Specifically, the array substrate may also include a light-shielding layer.

[0049] Specifically, the array substrate may also include a metal layer, which may be disposed on the side of the second active layer away from the source and drain layers, and the metal layer forms another gate of the thin film transistor.

[0050] Specifically, the material of the first electrode layer can be indium tin oxide, and the material of the second electrode layer can be indium tin oxide.

[0051] Specifically, it is understood that the above embodiments have provided a detailed description of the array substrate from the aspects of film layer design, structure of each film layer, and material design. It is understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the second active layer is disposed on the side of the source-drain layer away from the first active layer. The source-drain layer includes a first source and a first drain, which are spaced apart. The second active layer is disposed between the first source and the first drain, and the second active layer is in contact with the upper surfaces of the first source and the first drain. The array substrate also includes a first gate insulating layer, a gate layer, and a second gate insulating layer. The first gate insulating layer is disposed between the gate layer and the first active layer. The gate layer is disposed between the first gate insulating layer and the second gate insulating layer. The second gate insulating layer is disposed between the gate layer and the source-drain layer. The first electrode layer is in direct contact with the second gate insulating layer.

[0052] Meanwhile, this utility model embodiment provides a method for fabricating an array substrate, the method comprising: A substrate is provided, and a buffer layer and a first active layer are sequentially disposed on the substrate, and the first active layer is patterned. A first gate insulating layer and a gate layer are formed on the first active layer, and the gate layer is patterned. A second gate insulating layer and a first electrode layer are formed on the gate layer, and the second gate insulating layer is etched to form a first via, and the first electrode layer is patterned. Source and drain layers are formed on the first electrode layer, and the source and drain layers are patterned. A second active layer is formed in the source-drain layer, and the second active layer is patterned. A passivation layer is formed on the second active layer, and the passivation layer is etched to form a second via. A second electrode layer is formed on the passivation layer, and the second electrode layer is patterned.

[0053] This invention provides a method for fabricating an array substrate. As can be seen from this method, by removing the third metal film 122, the first indium tin oxide film 124, the third interlayer insulating film 125, and the planarization film 126, and by using the same mask to form the second gate insulating layer and the first electrode layer, an array substrate can be formed with only 7 masks, reducing the number of masks and improving the fabrication efficiency of the array substrate.

[0054] Specifically, the steps of forming a second gate insulating layer and a first electrode layer on the gate layer, etching the second gate insulating layer to form a first via, and patterning the first electrode layer include: A second gate insulating layer and a first electrode layer are formed on the gate layer. Then, a semi-transparent photomask is used for exposure patterning. A first wet etching process is used to etch away part of the first electrode layer corresponding to the first via. Then, a dry etching process is used to etch the second gate insulating layer to form the first via. Then, the photoresist other than the part that needs to be retained in the first electrode layer is removed. A second wet etching process is used to remove the other parts of the first electrode layer. Finally, the photoresist is removed by a stripping process.

[0055] Meanwhile, this utility model embodiment provides a display panel, which includes an array substrate as described in any of the above embodiments.

[0056] Specifically, such as Figure 3 As shown, the display panel 3 includes an array substrate 2, a color filter substrate 31, and a liquid crystal layer 32; however, the present invention is not limited to this, and the display panel can be other display panels.

[0057] Specifically, this utility model embodiment provides a display device, which includes a display panel as described in any of the above embodiments.

[0058] Specifically, the display device also includes a backlight module.

[0059] In the description of this utility model, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.

[0060] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0061] The embodiments, implementation methods, and related technical features of this utility model can be combined and substituted for each other without conflict.

[0062] The above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present utility model without departing from the scope of the present utility model's technical solution shall still fall within the scope of the present utility model's technical solution.

Claims

1. An array substrate, characterized in that, include: Substrate; A first active layer is disposed on one side of the substrate; The source and drain layers are disposed on the side of the first active layer away from the substrate; The second active layer is disposed on the side of the first active layer away from the substrate; The first electrode layer is disposed on the side of the source / drain layer close to the first active layer, and the first electrode layer is in direct contact with the source / drain layer.

2. The array substrate according to claim 1, characterized in that, The second active layer is disposed on the side of the source-drain layer away from the first active layer. The source-drain layer includes a first source and a first drain, which are spaced apart. The second active layer is disposed between the first source and the first drain, and the second active layer is in contact with the upper surfaces of the first source and the first drain.

3. The array substrate according to claim 2, characterized in that, The first electrode layer includes a first electrode, which is in contact with one of the first source and the first drain, and there is a gap between the first electrode and the second active layer.

4. The array substrate according to claim 1, characterized in that, The array substrate further includes a first gate insulating layer, a gate layer, and a second gate insulating layer. The first gate insulating layer is disposed between the gate layer and the first active layer. The gate layer is disposed between the first gate insulating layer and the second gate insulating layer. The second gate insulating layer is disposed between the gate layer and the source / drain layer. The first electrode layer is in direct contact with the second gate insulating layer.

5. The array substrate according to claim 4, characterized in that, The source-drain layer further includes a second source and a second drain, the second source and the second drain passing through a first via and connected to the first active layer, and the first via having a gap with the first electrode layer.

6. The array substrate according to claim 1, characterized in that, The array substrate further includes a passivation layer and a second electrode layer. The passivation layer is disposed on the side of the second active layer away from the source and drain layers, and the second electrode layer is disposed on the side of the passivation layer away from the second active layer. The second electrode layer passes through the second via and contacts the source and drain electrode layers.

7. The array substrate according to claim 6, characterized in that, The passivation layer includes a first sub-layer and a second sub-layer, the second sub-layer being disposed between the first sub-layer and the second electrode layer, and the material of the first sub-layer being different from the material of the second sub-layer.

8. The array substrate according to claim 1, characterized in that, The thickness of the second active layer ranges from 300 angstroms to 1000 angstroms.

9. The array substrate according to any one of claims 1 to 8, characterized in that, The first active layer is made of silicon semiconductor, the second active layer is made of oxide semiconductor, the array substrate includes a display area and a gate driving circuit area, the gate driving circuit area is disposed on at least one side of the display area, the first active layer is disposed in the gate driving circuit area, and the second active layer is disposed in the display area.

10. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 9.

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