Solar cell

Abstract

This application relates to a solar cell, wherein at least one surface of the solar cell includes a polycrystalline silicon region and a non-polycrystalline silicon region. The polycrystalline silicon region includes a stacked silicon substrate, a tunneling oxide layer, a doped polycrystalline silicon layer, a passivation antireflection layer, and a grid electrode. The non-polycrystalline silicon region includes a stacked silicon substrate and a passivation antireflection layer. The polycrystalline silicon region includes multiple polycrystalline silicon sub-regions, and the non-polycrystalline silicon region includes multiple non-polycrystalline silicon sub-regions, with the polycrystalline silicon sub-regions and non-polycrystalline silicon sub-regions alternating. At least two of the polycrystalline silicon sub-regions have unequal widths, and / or two of the non-polycrystalline silicon sub-regions have unequal widths. The solar cell of this application combines high short-circuit current and bifaciality with low series resistance, thereby significantly improving the conversion efficiency of the solar cell.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and in particular to a solar cell. Background Technology

[0002] With the photovoltaic industry's continuous pursuit of high-efficiency and low-cost solar cells, passivating contact technology has become the core structure of next-generation high-efficiency crystalline silicon solar cells (such as TOPCon, HJT, POLO, etc.). Among them, polycrystalline silicon layers (such as n+ or p+ doped polycrystalline silicon) are widely used to form electron- or hole-selective contacts, achieving excellent surface passivation effects and low contact resistance.

[0003] In existing passivated contact solar cells, a polycrystalline silicon layer is typically deposited across the entire surface as the passivation contact transport layer. On the one hand, the polycrystalline silicon layer can form a good interface passivation with the silicon substrate, reducing carrier recombination losses. On the other hand, polycrystalline silicon has excellent lateral carrier transport capabilities, which can efficiently collect photogenerated carriers generated in the silicon substrate to the metal grid lines.

[0004] However, polycrystalline silicon exhibits significant parasitic absorption of visible light (especially in the 400nm~800nm ​​band). A full polycrystalline silicon layer can cause some incident light to be absorbed and unable to reach the silicon substrate, directly reducing the short-circuit current density (Jsc) and bifaciality of the solar cell, thereby limiting the conversion efficiency of the solar cell. Utility Model Content

[0005] Therefore, it is necessary to provide a solar cell to address the above problems; the solar cell described in this application has both high short-circuit current and bifaciality as well as low series resistance, thereby significantly improving the conversion efficiency of the solar cell.

[0006] This application provides a solar cell, at least one side surface of which includes a polycrystalline silicon region and a non-polycrystalline silicon region. The polycrystalline silicon region includes a silicon substrate, a tunneling oxide layer, a doped polycrystalline silicon layer, a passivation antireflection layer, and a grid electrode stacked together. The non-polycrystalline silicon region includes a silicon substrate and a passivation antireflection layer stacked together.

[0007] The polycrystalline silicon region includes multiple polycrystalline silicon sub-regions, and the non-polycrystalline silicon region includes multiple non-polycrystalline silicon sub-regions, with the polycrystalline silicon sub-regions and the non-polycrystalline silicon sub-regions alternating.

[0008] There are at least two polycrystalline silicon sub-regions with unequal widths and / or two non-polycrystalline silicon sub-regions with unequal widths.

[0009] In one embodiment, the polycrystalline silicon region accounts for 25% to 95% of the area on one side surface.

[0010] By adjusting the area ratio of the polycrystalline silicon region on one side of the surface, it is beneficial to optimize and balance the optical absorption and electrical carrier transport performance, achieve the optimal solution for optical gain and electrical loss, and maintain a certain high bifaciality without loss, thereby further improving the conversion efficiency of solar cells.

[0011] In one embodiment, when any two of the polycrystalline silicon sub-regions have equal widths, at least two of the non-polycrystalline silicon sub-regions have unequal widths.

[0012] By designing at least two polycrystalline silicon sub-regions with unequal widths in the polycrystalline silicon region, the parasitic absorption of light by the doped polycrystalline silicon layer is reduced, which is beneficial to improving the bifaciality. Furthermore, the lateral transport path of charge carriers is optimized, and the lateral transport resistance is reduced, thereby further improving the conversion efficiency of the solar cell.

[0013] In one embodiment, the width of the non-polycrystalline silicon sub-regions is independently selected from 25 μm to 1000 μm.

[0014] By designing the width of the non-polycrystalline silicon sub-region, it is beneficial to optimize and balance the optical absorption and electrical carrier transport performance, achieve the optimal solution for optical gain and electrical loss, and maintain a certain high bifaciality without loss, thereby further improving the conversion efficiency of solar cells.

[0015] In one embodiment, when any two of the non-polycrystalline silicon sub-regions have equal widths, at least two of the polycrystalline silicon sub-regions have unequal widths.

[0016] By designing unequal widths for at least two non-polycrystalline silicon sub-regions within the non-polycrystalline silicon region, it is beneficial to further optimize the lateral transport path of charge carriers, forming an efficient "charge carrier transport channel," thereby further improving the conversion efficiency of the solar cell.

[0017] In one embodiment, the width of each polycrystalline silicon sub-region is independently selected from 25 μm to 1000 μm.

[0018] By designing the width of the polycrystalline silicon sub-region, it is beneficial to optimize and balance the optical absorption and electrical carrier transport performance, achieve the optimal solution for optical gain and electrical loss, and maintain a certain high bifaciality without loss, thereby further improving the conversion efficiency of solar cells.

[0019] In one embodiment, at least two of the polycrystalline silicon sub-regions have unequal widths, and at least two of the non-polycrystalline silicon sub-regions have unequal widths.

[0020] By designing unequal widths for at least two polycrystalline silicon sub-regions in the polycrystalline silicon region and at least two non-polycrystalline silicon sub-regions in the non-polycrystalline silicon region, the parasitic absorption of light by the doped polycrystalline silicon layer is reduced, which is beneficial to improving the bifaciality. Furthermore, the lateral transport path of charge carriers is optimized, and the lateral transport resistance is reduced, thereby further improving the conversion efficiency of the solar cell.

[0021] In one embodiment, the width of the polycrystalline silicon sub-region and the width of the non-polycrystalline silicon sub-region are each independently selected from 25 μm to 1000 μm.

[0022] By designing the widths of the polycrystalline silicon sub-regions and the non-polycrystalline silicon sub-regions, it is beneficial to optimize and balance the optical absorption and electrical carrier transport performance, achieve the optimal solution for optical gain and electrical loss, and maintain a certain high bifaciality without loss, thereby further improving the conversion efficiency of solar cells.

[0023] In one embodiment, the doped polysilicon layer is selected from an n-type structure or a p-type structure.

[0024] In one embodiment, the linewidth of the gate electrode is 5 μm to 200 μm.

[0025] The solar cell described in this application, by designing unequal widths for at least two polycrystalline silicon sub-regions in the polycrystalline silicon region and / or at least two non-polycrystalline silicon sub-regions in the non-polycrystalline silicon region, reduces parasitic absorption of light by the doped polycrystalline silicon layer, thereby improving the short-circuit current and bifaciality of the solar cell. Furthermore, it optimizes the lateral transport path of charge carriers, facilitating the formation of efficient "carrier transport channels," reducing lateral transport resistance, and thus lowering the series resistance of the solar cell. Ultimately, by balancing optical and electrical performance, it achieves an optimal solution for optical gain and electrical loss, significantly improving the conversion efficiency of the solar cell. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a partial structural schematic diagram of a solar cell according to one embodiment of this application;

[0028] Figure 2 This is a partial structural schematic diagram of a solar cell according to another embodiment of this application;

[0029] Figure 3 This is a partial structural schematic diagram of a solar cell according to another embodiment of this application.

[0030] Among them, 101 is the silicon substrate; 102 is the tunneling oxide layer; 103 is the doped polysilicon layer; 104 is the passivation antireflection layer; and 105 is the gate electrode. Detailed Implementation

[0031] To facilitate understanding of this application, it will be described in more detail below. However, it should be understood that this application can be implemented in many different forms and is not limited to the embodiments or examples described herein. Rather, these embodiments or examples are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular implementations or embodiments only and is not intended to be limiting of this application. The optional range of the term "and / or" as used herein includes any one of two or more of the related listed items, as well as any and all combinations of the related listed items, including any two related listed items, any more related listed items, or a combination of all related listed items. In this application, when numerical ranges are involved, unless otherwise specified, the numerical ranges are considered continuous and include the minimum and maximum values ​​of the range, and every value between such minimum and maximum values. Further, when a range refers to an integer, it includes every integer between the minimum and maximum values ​​of the range. Furthermore, when multiple ranges are provided to describe a feature or characteristic, the ranges may be merged. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all sub-ranges to which they are incorporated.

[0033] Through long-term and in-depth research, the applicant discovered that parasitic absorption can be reduced by patterning the polycrystalline silicon layer to decrease its coverage area. However, conventional symmetrical or regular locally patterned structures with equal spacing and width (such as equally spaced strips or grid structures) significantly weaken the lateral carrier transport capability of the doped polycrystalline silicon layer. Furthermore, since doped polycrystalline silicon is the core channel for lateral carrier transport, after symmetrical, equally spaced, and equally wide patterning, carriers in the areas without metal grid lines must rely entirely on the silicon substrate for lateral transport. However, the carrier mobility of the silicon substrate is much lower than that of polycrystalline silicon. This leads to a longer carrier transport path, increased losses, and ultimately a significant increase in the cell's series resistance (Rs), which offsets the benefits of short-circuit current and fails to achieve a balance between optical and electrical performance. Therefore, how to reduce parasitic absorption in polycrystalline silicon while maintaining an efficient lateral carrier transport and collection path has become a key challenge in the current design of high-efficiency solar cell structures.

[0034] Based on this, this application provides a solar cell, combined with Figures 1-3 As shown, at least one side surface includes a polycrystalline silicon region and a non-polycrystalline silicon region, wherein the polycrystalline silicon region includes a silicon substrate 101, a tunneling oxide layer 102, a doped polycrystalline silicon layer 103, a passivation antireflection layer 104 and a gate electrode 105 stacked together, and the non-polycrystalline silicon region includes a silicon substrate 101 and a passivation antireflection layer 104 stacked together.

[0035] The polycrystalline silicon region includes multiple polycrystalline silicon sub-regions, and the non-polycrystalline silicon region includes multiple non-polycrystalline silicon sub-regions, with the polycrystalline silicon sub-regions and the non-polycrystalline silicon sub-regions alternating.

[0036] There are at least two polycrystalline silicon sub-regions with unequal widths and / or two non-polycrystalline silicon sub-regions with unequal widths.

[0037] The solar cell described in this application improves the performance of the solar cell in several ways by designing unequal dimensions for the widths of at least two polycrystalline silicon sub-regions in the polycrystalline silicon region and / or at least two non-polycrystalline silicon sub-regions in the non-polycrystalline silicon region:

[0038] (1) Reduced parasitic light absorption: By setting up non-polycrystalline silicon regions, the parasitic light absorption of the doped polycrystalline silicon layer 103 is reduced, which improves the short-circuit current and conversion efficiency of the solar cell. Compared with the traditional whole-surface doped polycrystalline silicon layer structure, this application can reduce light loss by about 10% to 30% and increase the short-circuit current by more than 80mA.

[0039] (2) Optimize carrier transport: It helps to preserve the continuity of polycrystalline silicon on the critical path, form an efficient "carrier transport channel", reduce the lateral transport resistance, and thus reduce the series resistance of the solar cell, especially by 0.02mΩ·cm²~0.05mΩ·cm².

[0040] (3) Improve bifaciality: Since more light can penetrate the battery, the bifaciality of the battery is improved, making the solar cell perform better in bifacial power generation modules, especially improving the bifaciality by more than 5%.

[0041] (4) Balancing optical and electrical performance: It overcomes the structural contradiction in traditional solar cells that “large spacing results in poor transmission and small spacing results in excessive light absorption”, and achieves the optimal solution for optical gain and electrical loss, which significantly improves the conversion efficiency of solar cells, especially by 0.1% to 0.3%.

[0042] It is understood that, depending on the structure of different solar cells, polycrystalline silicon regions and non-polycrystalline silicon regions can be set on different surfaces. For example, polycrystalline silicon regions and non-polycrystalline silicon regions can be set on the front side, on the back side, or on both the front and back sides. This application does not limit this.

[0043] It should be noted that, based on the parallel-distributed gate electrodes 105, the polycrystalline silicon region is also composed of multiple parallel-distributed polycrystalline silicon sub-regions. Each polycrystalline silicon sub-region has one gate electrode 105, and the surface is divided into multiple parallel-distributed non-polycrystalline silicon regions, so that the polycrystalline silicon sub-regions and non-polycrystalline silicon sub-regions are alternately distributed. It is understood that this application does not limit the number of polycrystalline silicon sub-regions and non-polycrystalline silicon sub-regions, but can determine them based on the number of gate electrodes 105. In this application, there are at least two polycrystalline silicon sub-regions with unequal widths, or at least two non-polycrystalline silicon sub-regions with unequal widths, or at least two polycrystalline silicon sub-regions with unequal widths and two non-polycrystalline silicon sub-regions with unequal widths.

[0044] In one embodiment of this application, the area ratio of the polycrystalline silicon region on one side surface is preferably 25% to 95%, which is beneficial for optimizing and balancing optical absorption and electrical carrier transport performance, achieving the optimal solution for optical gain and electrical loss, and maintaining a certain high bifaciality without loss, thereby further improving the conversion efficiency of the solar cell. If the area ratio of the polycrystalline silicon region on one side surface is too high or too low, optical and electrical mismatch will occur, causing the conversion efficiency of the solar cell to decrease.

[0045] It is understood that the area percentage of the polycrystalline silicon region on the surface of one side includes, but is not limited to, any one of 25%, 30%, 40%, 50%, 60%, 70%, 80%, 95%, or any range between two of them.

[0046] In one embodiment of this application, when any two polycrystalline silicon sub-regions have equal widths, at least two non-polycrystalline silicon sub-regions have unequal widths. For example: specifically combined with... Figure 1 As shown, the widths of the three polycrystalline silicon sub-regions are D1=D2=D3, and the widths of the three non-polycrystalline silicon sub-regions are d1≠d2≠d3.

[0047] Understandably, in Figure 1 The widths of the three non-polycrystalline silicon sub-regions are not equal, including d1. <d2<d3、d1> d2>d3、d1 <d2>This application does not impose restrictions on various situations such as d3.

[0048] By designing at least two polycrystalline silicon sub-regions with unequal widths in the polycrystalline silicon region, the parasitic absorption of light by the doped polycrystalline silicon layer is reduced, which is beneficial to improving the bifaciality. Furthermore, the lateral transport path of charge carriers is optimized, and the lateral transport resistance is reduced, thereby further improving the conversion efficiency of the solar cell.

[0049] Further preferably, the width of the non-polycrystalline silicon sub-regions is independently selected from 25μm to 1000μm. By designing the width of the non-polycrystalline silicon sub-regions, it is beneficial to optimize and balance the optical absorption and electrical carrier transport performance, achieve the optimal solution for optical gain and electrical loss, and maintain a certain high bifaciality without loss, thereby further improving the conversion efficiency of the solar cell. If the width of the non-polycrystalline silicon sub-regions is too high or too low, optical and electrical mismatch will occur, causing the conversion efficiency of the solar cell to decrease.

[0050] Specifically, the width of the non-polycrystalline silicon sub-region includes, but is not limited to, any value among 25 μm, 100 μm, 200 μm, 300 μm, 500 μm, 600 μm, 800 μm, and 1000 μm, or a range between any two. It should be noted that this application does not limit the width of the polycrystalline silicon sub-region, as long as the width of the polycrystalline silicon sub-region is greater than the linewidth of the gate electrode 105.

[0051] In another embodiment of this application, when the widths of any two non-polycrystalline silicon sub-regions are equal, the widths of any two polycrystalline silicon sub-regions are not equal, for example: specifically combined with Figure 2 As shown, the widths of the three non-polycrystalline silicon sub-regions are d1=d2=d3, and the widths of the three polycrystalline silicon sub-regions are D1≠D2≠D3.

[0052] Understandably, in Figure 2 The widths of the three polycrystalline silicon sub-regions are not equal, including D1. <D2<D3、D1> D2>D3、D1 <d2>This application does not impose restrictions on various situations, such as D3.

[0053] By designing unequal widths for at least two non-polycrystalline silicon sub-regions within the non-polycrystalline silicon region, it is beneficial to further optimize the lateral transport path of charge carriers, forming an efficient "charge carrier transport channel," thereby further improving the conversion efficiency of the solar cell.

[0054] Further preferably, the width of each polycrystalline silicon sub-region is independently selected from 25μm to 1000μm. By designing the width of the polycrystalline silicon sub-region, it is beneficial to optimize and balance the optical absorption and electrical carrier transport performance, achieve the optimal solution for optical gain and electrical loss, and maintain a certain high bifaciality without loss, thereby further improving the conversion efficiency of the solar cell. If the width of the non-polycrystalline silicon sub-region is too high or too low, optical and electrical mismatch will occur, causing the conversion efficiency of the solar cell to decrease.

[0055] Specifically, the width of the polycrystalline silicon sub-region includes, but is not limited to, any value among 25 μm, 100 μm, 200 μm, 300 μm, 500 μm, 600 μm, 800 μm, and 1000 μm, or a range between any two. It should be noted that this application does not limit the width of the non-polycrystalline silicon sub-region.

[0056] In another embodiment of this application, at least two of the polycrystalline silicon sub-regions have unequal widths, and at least two of the non-polycrystalline silicon sub-regions have unequal widths, for example: specifically combined with Figure 3 As shown, the widths of the three non-polycrystalline silicon sub-regions are d1≠d2≠d3, and the widths of the three polycrystalline silicon sub-regions are D1≠D2≠D3.

[0057] By designing unequal widths for at least two polycrystalline silicon sub-regions in the polycrystalline silicon region and at least two non-polycrystalline silicon sub-regions in the non-polycrystalline silicon region, the parasitic absorption of light by the doped polycrystalline silicon layer is reduced, which is beneficial to improving the bifaciality. Furthermore, the lateral transport path of charge carriers is optimized, and the lateral transport resistance is reduced, thereby further improving the conversion efficiency of the solar cell.

[0058] Preferably, the width of the polycrystalline silicon sub-region and the width of the non-polycrystalline silicon sub-region are each independently selected from 25μm to 1000μm. By designing the widths of the polycrystalline silicon sub-region and the non-polycrystalline silicon sub-region, it is beneficial to optimize and balance the optical absorption and electrical carrier transport performance, achieve the optimal solution for optical gain and electrical loss, and maintain a certain high bifaciality without loss, thereby further improving the conversion efficiency of the solar cell. If the widths of the polycrystalline silicon sub-region and the non-polycrystalline silicon sub-region are too high or too low, optical and electrical mismatch will occur, causing the conversion efficiency of the solar cell to decrease.

[0059] Specifically, the width of the polycrystalline silicon sub-region and the width of the non-polycrystalline silicon sub-region include, but are not limited to, any value among 25 μm, 100 μm, 200 μm, 300 μm, 500 μm, 600 μm, 800 μm, and 1000 μm, or any range between the two. It should be noted that the width of any polycrystalline silicon sub-region and the width of any non-polycrystalline silicon sub-region may be partially equal or completely unequal; this application does not impose any limitation in this regard.

[0060] It is understood that, since both the polycrystalline silicon region and the non-polycrystalline silicon region are distributed in parallel based on the grid electrode 105, the direction in which the polycrystalline silicon sub-region and the non-polycrystalline silicon sub-region alternate is perpendicular to the grid electrode 105. This application does not limit the specific dimensions of the tunneling oxide layer 102, the doped polycrystalline silicon layer 103, the passivation antireflection layer 104, and the grid electrode 105. Those skilled in the art can make personalized designs for different solar cell products within the conventionally feasible width range.

[0061] Preferably, the thickness of the tunneling oxide layer 102 is 1 nm to 5 nm, and the material is an interface oxide layer such as silicon oxide or aluminum oxide; the thickness of the doped polycrystalline silicon layer 103 is 50 nm to 200 nm, and the doping type is opposite to that of the silicon substrate; the passivation antireflection layer includes, but is not limited to, SiN. x Passivation layer, Al2O3 passivation layer and MgF2 antireflection layer, SiN x / Any combination of SiO2 antireflection layers stacked; the linewidth of the gate electrode 105 is 5μm~200μm, and the material includes silver, copper or aluminum. This application does not limit the number of gate electrodes 105, which is usually more than 100; especially in the region where the expected carrier generation concentration is high, the width of the non-polycrystalline silicon region is small, while in the region where the expected carrier generation concentration is low, the width of the non-polycrystalline silicon region is large, that is, the width of the non-polycrystalline silicon region decreases as the expected carrier generation concentration increases.

[0062] In one embodiment of this application, the solar cell includes, but is not limited to, TOPCon solar cells or TBC solar cells.

[0063] This application also provides a method for preparing the solar cell as described above, comprising the following steps:

[0064] Step 1: Sequentially deposit a tunneling oxide layer and a polycrystalline silicon layer on at least one side surface of the silicon substrate;

[0065] Step 2: The polysilicon layer is annealed to form a doped polysilicon layer, and the doped polysilicon layer is patterned.

[0066] Step 3: Deposit a passivation and antireflection layer on the patterned doped polysilicon layer surface;

[0067] Step 4: Fabricate gate electrodes on the passivation and antireflection layer corresponding to the doped polysilicon layer region.

[0068] The preparation method described in this application is compatible with existing conventional passivated contact cell processes such as TOPCon solar cells or TBC solar cells. It can add a patterning step between the second step of annealing to form a doped polycrystalline silicon layer and the third step of depositing a passivation and antireflection layer, without requiring significant modifications to existing production lines, and has great potential for widespread application.

[0069] It is understood that, prior to depositing the tunneling oxide layer and the polycrystalline silicon layer in step one, it is preferable to perform conventional cleaning and texturing on the silicon substrate surface, and this application does not impose any restrictions on this.

[0070] In step one, the process for depositing the tunneling oxide layer includes, but is not limited to, thermal oxidation; the process for depositing the polycrystalline silicon layer includes, but is not limited to, plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD). It is understood that the polycrystalline silicon layer formed contains dopants and can form the desired n-type or p-type structure.

[0071] In step two, the patterning process can be prepared using a masking process. For example, a protective film can be printed using screen printing patterning technology to form a preset polycrystalline silicon region and a preset non-polycrystalline silicon region on the doped polycrystalline silicon layer. Then, the polycrystalline silicon layer and tunnel oxide layer in the unmasked areas can be removed by chemical etching. Finally, the masking material can be removed by wet etching.

[0072] In step three, the process of depositing the passivation and antireflection layer includes, but is not limited to, atomic layer deposition (ALD).

[0073] In step four, the grid electrodes are mainly produced using screen printing technology.

[0074] The solar cell will be further described below through specific embodiments. However, those skilled in the art will understand that the following embodiments are for illustrative purposes only and should not be considered as limiting the scope of this application. Unless otherwise specified, specific conditions in the embodiments are performed under conventional conditions or conditions recommended by the manufacturer. Reagents or instruments used without specified manufacturers are all commercially available conventional products.

[0075] Example 1

[0076] (1) Surface treatment: Provide n-type monocrystalline silicon wafers, perform conventional cleaning and texturing on the surface of the silicon wafers to form the required surface structure;

[0077] (2) Preparation of tunneling oxide layer: A silicon oxide layer with a thickness of about 2 nm is formed on the surface of the silicon wafer by thermal oxidation;

[0078] (3) Polycrystalline silicon layer deposition: A polycrystalline silicon layer containing dopants is deposited on the tunneling oxide layer by plasma-enhanced chemical vapor deposition;

[0079] (4) High-temperature annealing: Rapid thermal annealing is performed at temperatures above 500°C to crystallize amorphous silicon and form a p-type polycrystalline silicon layer;

[0080] (5) Patterned mask fabrication: Using screen printing patterning technology, a protective film is printed to form a preset polycrystalline silicon region and a preset non-polycrystalline silicon region on the doped polycrystalline silicon layer. The preset polycrystalline silicon region accounts for approximately 50% of the area on this surface. (Refer to...) Figure 1 As shown, from left to right, the widths of the three polycrystalline silicon sub-regions are D1=D2=D3=200μm, and the widths of the three non-polycrystalline silicon sub-regions are d1=100, d2=200, and d3=300, respectively. This constitutes one cycle, and multiple cycles are set according to hundreds of gate electrodes. Then, the polycrystalline silicon layer and tunneling oxide layer in the unmasked areas are removed by chemical etching. Finally, the mask material is removed by wet etching.

[0081] (6) Preparation of passivation film and antireflection film: An aluminum oxide layer of about 10 nm was deposited on the surface of the battery by atomic layer deposition (ALD), and then a silicon nitride layer of about 80 nm was deposited by PECVD as an antireflection film;

[0082] (7) Electrode preparation: Patterned silver paste is printed on the polycrystalline silicon / passivation antireflection film using screen printing technology to form a metal grid electrode with a line width of about 50 μm. After sintering, a good ohmic contact is formed.

[0083] Example 2

[0084] The difference between Example 2 and Example 1 is that in step (5) of patterned mask fabrication, the pre-defined polysilicon region accounts for approximately 66% of the area on the surface. Figure 2 As shown, from left to right, the widths of the three polycrystalline silicon sub-regions are D1=300, D2=200, and D3=100, respectively, and the widths of the three non-polycrystalline silicon sub-regions are d1=d2=d3=100μm, respectively. This is one cycle, and multiple cycles are set according to hundreds of gate electrodes.

[0085] Example 3

[0086] The difference between Example 3 and Example 1 is that in step (5) of patterned mask fabrication, the pre-defined polysilicon region accounts for approximately 50% of the area on the surface. Figure 3 As shown, from left to right, the widths of the three polycrystalline silicon sub-regions are D1=300, D2=200, and D3=100, respectively, and the widths of the three non-polycrystalline silicon sub-regions are d1=300, d2=200, and d3=100, respectively. This constitutes one cycle, and multiple cycles are set based on hundreds of gate line electrodes.

[0087] Example 4

[0088] The difference between Example 4 and Example 1 is that in step (5) patterned mask preparation, the widths of the three polycrystalline silicon sub-regions along the left-to-right direction are D1=300, D2=200, and D3=100, respectively, and the widths of the three non-polycrystalline silicon sub-regions are d1=100, d2=200, and d3=300, respectively. This is one cycle, and multiple cycles are set according to hundreds of gate line electrodes.

[0089] Example 5

[0090] The difference between Example 5 and Example 1 is that in step (5) patterned mask preparation, the widths of the three polycrystalline silicon sub-regions along the left-to-right direction are D1=300, D2=100, and D3=200, respectively, and the widths of the three non-polycrystalline silicon sub-regions are d1=100, d2=300, and d3=200, respectively. This is one cycle, and multiple cycles are set according to hundreds of gate line electrodes.

[0091] Example 6

[0092] The difference between Example 6 and Example 1 is that in step (5) patterned mask preparation, the widths of the three polycrystalline silicon sub-regions along the left-to-right direction are D1=D2=D3=200μm, and the widths of the three non-polycrystalline silicon sub-regions are d1=100, d2=300, and d3=200, respectively. This is one cycle, and multiple cycles are set according to hundreds of gate line electrodes.

[0093] Example 7

[0094] The difference between Example 7 and Example 1 is that in step (5) patterned mask preparation, the widths of the three polycrystalline silicon sub-regions along the left-to-right direction are D1=300, D2=100, and D3=200, respectively, and the widths of the three non-polycrystalline silicon sub-regions are d1=d2=d3=200μm, respectively. This is one cycle, and multiple cycles are set according to hundreds of gate line electrodes.

[0095] Example 8

[0096] The difference between Example 8 and Example 1 is that in step (5) patterned mask preparation, the widths of the three polycrystalline silicon sub-regions along the left-to-right direction are D1=D2=D3=200μm, and the widths of the three non-polycrystalline silicon sub-regions are d1=100, d2=100, and d3=300, respectively. This is one cycle, and multiple cycles are set according to hundreds of gate line electrodes.

[0097] Example 9

[0098] The difference between Example 9 and Example 1 is that in step (5) patterned mask preparation, the widths of the three polycrystalline silicon sub-regions along the left-to-right direction are D1=300, D2=200, and D3=200, respectively, and the widths of the three non-polycrystalline silicon sub-regions are d1=d2=d3=100μm, respectively. This is one cycle, and multiple cycles are set according to hundreds of gate line electrodes.

[0099] Example 10

[0100] The difference between Example 10 and Example 1 is that in step (5) patterned mask preparation, the widths of the three polycrystalline silicon sub-regions along the left-to-right direction are D1=200, D2=200, and D3=100, respectively, and the widths of the three non-polycrystalline silicon sub-regions are d1=300, d2=100, and d3=100, respectively. This is one cycle, and multiple cycles are set according to hundreds of gate line electrodes.

[0101] Comparative Example 1

[0102] The difference between Comparative Example 1 and Example 1 is that after high-temperature annealing in step (4), the passivation film and antireflection film were prepared directly in step (6), and the patterned mask was not prepared in step (5).

[0103] Comparative Example 2

[0104] The difference between Comparative Example 2 and Example 1 is that in step (5) patterned mask preparation, the widths of the three polycrystalline silicon sub-regions along the left-to-right direction are D1=D2=D3=200μm, and the widths of the three non-polycrystalline silicon sub-regions are d1=d2=d3=200μm.

[0105] All solar cells prepared in the examples and comparative examples were tested for electrical performance, including conversion efficiency (Eff), open circuit voltage (Uoc), short circuit current (Isc), series resistance (Rser), fill factor (FF), reverse current (Irev2) under reverse voltage (-12V), and bifaciality. The results are shown in Table 1.

[0106] Table 1

[0107]

[0108] As shown in Table 1, the solar cell provided in this application has both high short-circuit current and bifaciality as well as low series resistance, thus significantly improving the conversion efficiency.

[0109] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0110] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A solar cell, characterized in that, At least one surface includes a polycrystalline silicon region and a non-polycrystalline silicon region, wherein the polycrystalline silicon region includes a silicon substrate, a tunneling oxide layer, a doped polycrystalline silicon layer, a passivation anti-reflection layer and a gate electrode stacked together, and the non-polycrystalline silicon region includes a silicon substrate and a passivation anti-reflection layer stacked together. The polycrystalline silicon region includes multiple polycrystalline silicon sub-regions, and the non-polycrystalline silicon region includes multiple non-polycrystalline silicon sub-regions, with the polycrystalline silicon sub-regions and the non-polycrystalline silicon sub-regions alternating. There are at least two polycrystalline silicon sub-regions with unequal widths and / or two non-polycrystalline silicon sub-regions with unequal widths.

2. The solar cell according to claim 1, characterized in that, The polycrystalline silicon region accounts for 25% to 95% of the area on one side surface.

3. The solar cell according to claim 1, characterized in that, When any two polycrystalline silicon sub-regions have equal widths, there are at least two non-polycrystalline silicon sub-regions with unequal widths.

4. The solar cell according to claim 3, characterized in that, The widths of the non-polycrystalline silicon sub-regions are independently selected from 25μm to 1000μm.

5. The solar cell according to claim 1, characterized in that, When any two non-polycrystalline silicon sub-regions have equal widths, there are at least two polycrystalline silicon sub-regions with unequal widths.

6. The solar cell according to claim 5, characterized in that, The widths of the polycrystalline silicon sub-regions are independently selected from 25μm to 1000μm.

7. The solar cell according to claim 1, characterized in that, There are at least two polycrystalline silicon sub-regions with unequal widths, and there are at least two non-polycrystalline silicon sub-regions with unequal widths.

8. The solar cell according to claim 7, characterized in that, The width of the polycrystalline silicon sub-region and the width of the non-polycrystalline silicon sub-region are each independently selected from 25μm to 1000μm.

9. The solar cell according to claim 1, characterized in that, The doped polycrystalline silicon layer is selected from either an n-type or a p-type structure.

10. The solar cell according to claim 1, characterized in that, The linewidth of the gate electrode is 5μm to 200μm.

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