Integrated circuit having gate conductor segments formed from a gate conductor

Abstract

The utility model provides a kind of integrated circuit.The integrated circuit includes the first power line and the second power line extending along the first direction.The integrated circuit includes the column of three gate conductor segments aligned along the second direction and bounded by the first power line and the second power line.The three gate conductor segments include the intermediate gate conductor segment between the first gate conductor segment and the second gate conductor segment.The first gate conductor line segment intersects the first active region structure at the channel region of the first transistor.The second gate conductor line segment intersects the second active region structure at the channel region of the second transistor.The utility model can reduce parasitic capacitance.

Description

Technical Field

[0001] This utility model relates to an integrated circuit. Background Technology

[0002] The latest trend in integrated circuit (IC) miniaturization is resulting in smaller devices that consume less power but deliver more functionality at higher speeds. Miniaturization processes also bring more stringent design and manufacturing specifications and reliability challenges. Various electronic design automation (EDA) tools generate, optimize, and verify standard cell layout designs for ICs, while ensuring compliance with standard cell layout design and manufacturing specifications. Utility Model Content

[0003] This utility model provides an integrated circuit, including: a first type active region structure and a second type active region structure extending along a first direction; a first power line and a second power line extending along the first direction; and a column of three gate conductor segments aligned along a second direction and bounded by the first power line and the second power line, wherein the three gate conductor segments include an intermediate gate conductor segment located between the first gate conductor segment and the second gate conductor segment, the first gate conductor segment intersecting the first type active region structure at a channel region of the first type transistor, and the second gate conductor segment intersecting the second type active region structure at a channel region of the second type transistor, and wherein the second direction is perpendicular to the first direction.

[0004] This utility model provides an integrated circuit, including: a first type of active region structure and a second type of active region structure extending along a first direction; a first power line and a second power line extending along the first direction; and a circuit unit having a first horizontal unit boundary and a second horizontal unit boundary extending along the first direction, wherein the first horizontal unit boundary overlaps with the first power line and the second horizontal unit boundary overlaps with the second power line, and wherein the circuit unit includes: a column of three terminal conductor segments aligned along a second direction and bounded by the first horizontal unit boundary and the second horizontal unit boundary, the second direction being perpendicular to the first direction, wherein the three terminal conductor segments include an intermediate terminal conductor segment between the first terminal conductor segment and the second terminal conductor segment, wherein the first terminal conductor segment intersects the first type of active region structure at a terminal region of a first type of transistor, wherein the second terminal conductor segment intersects the second type of active region structure at a terminal region of a second type of transistor, and wherein each terminal region is a source region or a drain region. Attached Figure Description

[0005] The present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the sizes of the various features may be arbitrarily increased or decreased.

[0006] Figure 1A This is a layout diagram of an integrated circuit according to some embodiments.

[0007] Figure 1B Based on some embodiments Figure 1A A schematic diagram of an integrated circuit is formed based on the layout diagram.

[0008] Figures 2A-2E According to some embodiments, the circuit unit is along Figure 1A The cross-sectional views of each section shown.

[0009] Figure 3A This is a layout diagram of an integrated circuit according to some embodiments.

[0010] Figure 3B Based on some embodiments Figure 3A A schematic diagram of an integrated circuit is formed based on the layout diagram.

[0011] Figures 4A-4E According to some embodiments, it is along Figure 3A The circuit unit cross-sections shown are shown.

[0012] Figure 5A This is a layout diagram of an integrated circuit according to some embodiments.

[0013] Figure 5B Based on some embodiments Figure 5A A schematic diagram of an integrated circuit is formed based on the layout diagram.

[0014] Figure 6A This is a layout diagram of an integrated circuit according to some embodiments.

[0015] Figure 6B Based on some embodiments Figure 6A A schematic diagram of an integrated circuit is formed based on the layout diagram.

[0016] Figure 7A This is a layout diagram of an integrated circuit according to some embodiments.

[0017] Figure 7B Based on some embodiments Figure 7A A schematic diagram of an integrated circuit is formed based on the layout diagram.

[0018] Figures 8A-8B Based on some embodiments Figure 1B A schematic diagram of a variant of an integrated circuit.

[0019] Figures 9A-9B This is a flowchart of a method for manufacturing an integrated circuit according to some embodiments.

[0020] Figure 10 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0021] Figure 11 This is a block diagram of an integrated circuit (IC) manufacturing system and the associated IC manufacturing process according to some embodiments. Detailed Implementation

[0022] The following utility model description provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify the utility model description. Of course, these specific examples are merely illustrative and not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the utility model description. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0023] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms may be used to describe the relationship between one component or feature and another, as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of components in use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0024] The integrated circuit includes a first power line and a second power line extending along the X direction at the horizontal cell boundary of the circuit cell. In some embodiments, the circuit cell includes a column of three gate conductor segments aligned along the Y direction and bounded by the first and second power lines. The column of three gate conductor segments includes an intermediate gate conductor segment between two gate conductor segments, each gate conductor segment intersecting an active region structure at the channel region of the transistor. In some embodiments, the circuit cell includes a column of three terminal conductor segments aligned along the Y direction and bounded by the first and second power lines. The column of three terminal conductor segments includes an intermediate terminal conductor segment between two terminal conductor segments, each terminal conductor segment intersecting an active region structure at the source / drain region of the transistor. In some embodiments, a third power line or routing line extends along the X direction and intersects one or both of the intermediate gate conductor segment and the intermediate terminal conductor segment. Including an intermediate gate conductor segment reduces the parasitic capacitance of the gate terminals formed by the gate conductor segments. Including an intermediate terminal conductor segment reduces the parasitic capacitance of the source / drain terminals formed by the terminal conductor segments. Including a third power line reduces the IR voltage drop of the power grid net used to power the circuit units.

[0025] Figure 1A This is a layout diagram of an integrated circuit according to some embodiments. Figure 1A The layout diagrams include a layout pattern 50pM for specifying the PMOS active region structure extending in the X direction, a layout pattern 50nM for specifying the NMOS active region structure extending in the X direction, layout patterns 122M and 128M for specifying the gate conductor extending in the Y direction, layout patterns 142M and 148M for specifying the terminal conductor extending in the Y direction, and layout patterns 101M and 109M for specifying the dummy gate conductor extending in the Y direction. In the XY coordinate system, the X and Y directions are perpendicular to each other. Figure 1A The layout diagrams also include layout patterns 20M and 40M for specifying power lines extending in the X direction, layout patterns 131M, 134M, 136M and 139M for specifying cuts of gate conductors and cuts of dummy gate conductors, and layout patterns 171M, 174PM, 174QM, 176PM, 176QM and 179M for specifying cuts of terminal conductors.

[0026] Figure 1B Based on some embodiments Figure 1A A schematic diagram of an integrated circuit is formed based on a layout diagram. Figure 1BThe integrated circuit includes a circuit cell 100 having vertical cell boundaries 101 and 109 extending along the Y direction and horizontal cell boundaries 102 and 108 extending along the X direction. The circuit cell 100 includes a PMOS active region structure 50p and an NMOS active region structure 50n, each extending along the X direction. The circuit cell 100 includes power lines 20 and 40, each extending along the X direction. The active region structure adjacent to power line 20 is the PMOS active region structure 50p, and the active region structure adjacent to power line 40 is the NMOS active region structure 50n. In some embodiments, power line 20 is configured to be maintained at a higher supply voltage VCC, and power line 40 is configured to be maintained at a lower supply voltage VSS, wherein the higher supply voltage VCC is higher than the lower supply voltage VSS. In some alternative embodiments, the active region structure adjacent to power line 20 is an NMOS active region structure, and the active region structure adjacent to power line 40 is a PMOS active region structure. In an alternative embodiment, power line 20 is configured to remain at a lower power supply voltage VSS, and power line 40 is configured to remain at a higher power supply voltage VCC.

[0027] Circuit unit 100 further includes gate conductor segments 122A-122C and 128A-128C, and dummy gate conductor segments 101A-101C and 109A-109C. Circuit unit 100 includes terminal conductor segments 142A-142C and 148A-148C, and dummy gate conductor segments 101A-101C and 109A-109C. Gate conductor segments 122A-122C form a first column of three gate conductor segments aligned along the Y direction, wherein gate conductor segment 122C is an intermediate gate conductor segment between the other gate conductor segments 122A and 122B. Gate conductor segments 128A-128C form a second column of three gate conductor segments aligned along the Y direction, wherein gate conductor segment 128C is an intermediate gate conductor segment between the other gate conductor segments 128A and 128B. The first column of the three gate conductor segments 122A-122C and the second column of the three gate conductor segments 128A-128C are each bounded by horizontal cell boundary 102 and horizontal cell boundary 108; that is, neither of the first column nor the second column extends through horizontal cell boundary 102 or 108. Furthermore, horizontal cell boundary 102 overlaps with power line 20, and horizontal cell boundary 108 overlaps with power line 40.

[0028] exist Figure 1BIn this embodiment, the first column of the three gate conductor segments 122A-122C is defined by power lines 20 and 40, because gate conductor segment 122A does not overlap with power line 20 and gate conductor segment 122B does not overlap with power line 40. In some alternative embodiments, gate conductor segment 122A extends through the first horizontal boundary 21 of power line 20 but does not extend through the second horizontal boundary 22 of power line 20; therefore, the first column of the three gate conductor segments 122A-122C is still defined by power lines 20 and 40. Similarly, in some alternative embodiments, gate conductor segment 122B extends through the first horizontal boundary 41 of power line 40 but does not extend through the second horizontal boundary 42 of power line 40; therefore, the first column of the three gate conductor segments 122A-122C is still defined by power lines 20 and 40.

[0029] exist Figure 1B In this embodiment, the second column of the three gate conductor segments 128A-128C is defined by power lines 20 and 40, because gate conductor segment 128A does not overlap with power line 20 and gate conductor segment 128B does not overlap with power line 40. In some alternative embodiments, gate conductor segment 128A extends across the first horizontal boundary 21 of power line 20 but does not extend across the second horizontal boundary 22 of power line 20, so the second column of the three gate conductor segments 128A-128C is still defined by power lines 20 and 40. Similarly, in some alternative embodiments, gate conductor segment 128B extends across the first horizontal boundary 41 of power line 40 but does not extend across the second horizontal boundary 42 of power line 40, so the second column of the three gate conductor segments 128A-128C is still defined by power lines 20 and 40.

[0030] In some embodiments, each of gate conductor segments 122A and 128A intersects with the PMOS active region structure 50p at the channel region of the PMOS transistor, and each of gate conductor segments 122B and 128B intersects with the NMOS active region structure 50n at the channel region of the NMOS transistor. In some embodiments, each of the PMOS active region structure 50p and the NMOS active region structure 50n includes one or more fin structures; therefore, the PMOS transistor and NMOS transistor formed by the active region structures are fin-type FET transistors. In some embodiments, both the PMOS active region structure 50p and the NMOS active region structure 50n include one or more nanosheets; therefore, the PMOS transistor and NMOS transistor formed by the active region structures are nanosheet transistors. In some embodiments, both the PMOS active region structure 50p and the NMOS active region structure 50n include one or more nanowires; therefore, the PMOS transistor and NMOS transistor formed by the active region structures are nanowire transistors.

[0031] The first column of the three gate conductor segments 122A-122C is based on... Figure 1A The layout is formed according to the specifications defined by layout patterns 122M and layout patterns 131M, 134M, 136M and 139M in the layout diagram. The second column of the three gate conductor segments 128A-128C is based on the specifications defined by the layout pattern 122M and layout patterns 131M, 134M, 136M and 139M in the layout diagram. Figure 1A The specifications defined by layout patterns 128M and 131M, 134M, 136M, and 139M in the layout diagram are formed. The spacing distance (along the Y direction) between gate conductor segments 122A and 122C, or between gate conductor segments 128A and 128C, is determined by the width (along the Y direction) of layout pattern 134M. Similarly, the spacing distance (along the Y direction) between gate conductor segments 122B and 122C, or between gate conductor segments 128B and 128C, is determined by the width (along the Y direction) of layout pattern 136M.

[0032] The dummy gate conductor segments 101A-101C aligned along the Y direction at the vertical cell boundary 101 are based on Figure 1A The layout pattern 101M and layout patterns 131M, 134M, 136M and 139M in the layout diagram are formed according to the specifications defined therein. The dummy gate conductor segments 109A-109C arranged along the Y direction at the vertical cell boundary 109 are based on Figure 1A It is formed by defining the specifications of layout pattern 109M and layout patterns 131M, 134M, 136M and 139M in the layout diagram.

[0033] exist Figure 1B In this configuration, terminal conductor segments 142A-142C form a first column of three terminal conductor segments aligned along the Y direction, wherein terminal conductor segment 142C is an intermediate terminal conductor segment between the other terminal conductor segments 142A and 142B. Terminal conductor segments 148A-148C form a second column of three terminal conductor segments aligned along the Y direction, wherein terminal conductor segment 142C is an intermediate terminal conductor segment between the other terminal conductor segments 142A and 142B. The first column of the three terminal conductor segments 142A-142C and the second column of the three terminal conductor segments 148A-148C are respectively bounded by horizontal unit boundary 102 and horizontal unit boundary 108; that is, neither the first column nor the second column extends through horizontal unit boundary 102 or 108. Furthermore, horizontal unit boundary 102 overlaps with power line 20, and horizontal unit boundary 108 overlaps with power line 40.

[0034] exist Figure 1BIn this embodiment, the first column of the three terminal conductor segments 142A-142C is defined by power lines 20 and 40, because terminal conductor segment 142A does not overlap with power line 20, and terminal conductor segment 142B does not overlap with power line 40. In some alternative embodiments, terminal conductor segment 142A extends through the first horizontal boundary 21 of power line 20 but does not extend through the second horizontal boundary 22 of power line 20; therefore, the first column of the three terminal conductor segments 142A-142C is still defined by power lines 20 and 40. Similarly, in some alternative embodiments, terminal conductor segment 142B extends through the first horizontal boundary 41 of power line 40 but does not extend through the second horizontal boundary 42 of power line 40; therefore, the first column of the three terminal conductor segments 142A-142C is still defined by power lines 20 and 40.

[0035] exist Figure 1B In this embodiment, the second column of the three terminal conductor segments 148A-148C is defined by power lines 20 and 40, because terminal conductor segment 148A does not overlap with power line 20, and terminal conductor segment 148B does not overlap with power line 40. In some alternative embodiments, terminal conductor segment 148A extends through the first horizontal boundary 21 of power line 20 but does not extend through the second horizontal boundary 22 of power line 20; therefore, the second column of the three terminal conductor segments 148A-148C is still defined by power lines 20 and 40. Similarly, in some alternative embodiments, terminal conductor segment 148B extends through the first horizontal boundary 41 of power line 40 but does not extend through the second horizontal boundary 42 of power line 40; therefore, the second column of the three terminal conductor segments 148A-148C is still defined by power lines 20 and 40.

[0036] The first column of the three terminal conductor segments 142A-142C is based on Figure 1A The layout diagrams are formed according to the specifications defined in layout patterns 142M, 171M, 174PM, 174QM, 176PM, 176QM, and 179M. The second column of the three terminal conductor segments 148A-148C is based on... Figure 1AThe layout pattern 148M and layout patterns 171M, 174PM, 174QM, 176PM, 176QM, and 179M are formed according to the specifications defined in the layout diagram. The spacing (along the Y direction) between terminal conductor segments 142A and 142C is determined by the width (along the Y direction) of layout pattern 174PM. The spacing (along the Y direction) between terminal conductor segments 148A and 148C is determined by the width (along the Y direction) of layout pattern 174QM. Similarly, the spacing (along the Y direction) between terminal conductor segments 142B and 142C is determined by the width (along the Y direction) of layout pattern 176PM. The spacing (along the Y direction) between terminal conductor segments 148B and 148C is determined by the width (along the Y direction) of layout pattern 176QM.

[0037] Figure 2A Circuit unit 100 along Figure 1B The cross-sectional view of section AA' shown (shown on the plane formed by the X and Z directions). Figure 2A In this configuration, the PMOS active region structure 50p is located on the substrate 30. Each of the gate conductor segments 122A and 128A intersects the PMOS active region structure 50p at the channel region of the corresponding PMOS transistor. Each of the terminal conductor segments 142A, 145, and 148A intersects the PMOS active region structure 50p at the terminal region of at least one corresponding PMOS transistor. The terminal region of the PMOS transistor is either the source or drain region of the PMOS transistor. In some embodiments, the active regions (e.g., source, channel, or drain regions) in the PMOS active region structure 50p are isolated from the active regions in adjacent cells by boundary isolation regions i101A under the dummy gate conductor 101A and i109A under the dummy gate conductor 109A. The gate conductor segments 122A and 128A, as well as the terminal conductor segments 142A, 145, and 148A, are all covered by the interlayer dielectric ILD0.

[0038] Figure 2B Circuit unit 100 along Figure 1B The cross-sectional view shown is of section BB'. Figure 2BIn this embodiment, the NMOS active region structure 50n is on the substrate 30. Each of the gate conductor segments 122B and 128B intersects the NMOS active region structure 50n at the channel region of the corresponding NMOS transistor. Each of the terminal conductor segments 142B, 145, and 148B intersects the NMOS active region structure 50n at the terminal region of at least one corresponding NMOS transistor. In some embodiments, the active regions (e.g., source regions, channel regions, or drain regions) in the NMOS active region structure 50n are isolated from the active regions in adjacent cells by boundary isolation regions i101B under the dummy gate conductor 101B and i109B under the dummy gate conductor 109B. The gate conductor segments 122B and 128B, as well as the terminal conductor segments 142B, 145, and 148B, are all covered by the interlayer dielectric ILD0.

[0039] Figure 1B The vertical cell boundaries 101 and 109 of circuit cell 100 in the integrated circuit can be identified as boundary isolation regions in the integrated circuit. The boundary isolation region i101A below the dummy gate conductor 101A (e.g., ...) Figure 2A (as shown) and the boundary isolation region i101B below the dummy gate conductor 101A (as shown) Figure 2B As shown, the circuit cell 100 is vertically aligned along the Y direction, and the vertical cell boundary 101 is depicted. A boundary isolation region i109A is dummy below the gate conductor 109A (as shown). Figure 2A (as shown) and the boundary isolation region i109B below the dummy gate conductor 109A (as shown) Figure 2B (As shown) Aligned vertically along the Y direction and depict the vertical cell boundary 109 of the circuit cell 100.

[0040] Figure 2C Circuit unit 100 along Figure 1B The cross-sectional view shown is of section CC'. Figure 2C In this substrate 30, each of gate conductor segments 122C and 128C extends in the Y direction on the substrate 30, and each of terminal conductor segments 142C, 145, and 148C also extends in the Y direction on the substrate 30. Gate conductor segments 122C and 128C, as well as terminal conductor segments 142C, 145, and 148C, are all covered by interlayer dielectric ILD0.

[0041] Figure 2D The circuit unit 100 according to some embodiments is along Figure 1BThe cross-sectional view of section PP' is shown. Each of the terminal conductor segments 142A, 142C, and 142B extends along the Y direction on the substrate 30. Terminal conductor segments 142A and 142B intersect the PMOS active region structure 50p and the NMOS active region structure 50n respectively. Power lines 20 and 40 extending in the X direction are formed in a first metal layer (e.g., metal layer M0), which overlays an interlayer dielectric ILD0 covering the terminal conductor segments 142A, 142C, and 142B.

[0042] Figure 2E The circuit unit 100 according to some embodiments is along Figure 1B The diagram shows a cross-sectional view of section QQ'. Each of the gate conductor segments 128A, 128C, and 128B extends along the Y direction on the substrate 30. Gate conductor segments 128A and 128B intersect the PMOS active region structure 50p and the NMOS active region structure 50n, respectively. Power lines 20 and 40 extending in the X direction are formed in a first metal layer (e.g., metal layer M0), which overlays an interlayer dielectric ILD0 covering the gate conductor segments 128A, 128C, and 128B.

[0043] Figure 1A Some variations in the layout diagram are depicted in Figure 3A , Figure 5A , Figure 6A and Figure 7A middle. Figure 1B Some variations of the schematic diagram forming an integrated circuit are depicted in Figure 3B , Figure 5B , Figure 6B and Figure 7B middle.

[0044] Figure 3A This is a layout diagram of an integrated circuit according to some embodiments. Figure 3A The layout diagram in the middle is from Figure 1A The layout diagram is modified from the previous one, with the addition of layout pattern 60M to specify the power lines extending in the X direction. Layout pattern 60M, extending in the X direction, is located between layout patterns 134M and 136M and is used to specify the cut of the gate conductor. The additional power lines specified by layout pattern 60M reduce the IR voltage drop of the power grid net used to supply power to the circuit units.

[0045] Figure 3B Based on some embodiments Figure 3A A schematic diagram of an integrated circuit is formed based on the layout diagram. Figure 3B Integrated circuits in Figure 1BThe integrated circuit is modified by adding a power line 60 extending in the X direction. The power line 60 intersects with gate conductor segments 122C and 128C, terminal conductor segments 142C and 148C, and dummy gate conductor segments 101C and 109C. In some embodiments, the power line 60 is connected to the terminal conductor segment 145 via a through-hole connector.

[0046] Figures 4A-4C Circuit unit 100 along Figure 1B The cross-sectional views of the corresponding sections AA', BB', and CC' are shown. Figure 4A Sectional view and Figure 2A The sectional views are the same as those in the original text. Figure 4B Sectional view and Figure 2B The sectional views are the same. Figure 4C The sectional view shown is from Figure 2C The cross-sectional view is modified from the image, showing a power line 60 extending in the X direction overlying the interlayer dielectric ILD0 in the first metal layer (e.g., metal layer M0). In some embodiments, the power line 60 is connected to the terminal conductor segment 145 via a through-hole connector 495 that passes through the interlayer dielectric ILD0 beneath the first metal layer.

[0047] Figure 4D-4E Circuit unit 100 along Figure 3B The cross-sectional views of the corresponding sections PP' and QQ' are shown. Figure 4D The sectional view shown is from Figure 2D The cross-sectional view is modified from the figure, wherein a power line 60 overlying an interlayer dielectric ILD0 is added in the first metal layer (e.g., metal layer M0). The power line 60, extending in the X direction, is located directly above the terminal conductor segment 142C. Figure 4E The sectional view shown is from Figure 2E The cross-sectional view is modified from the image, wherein a power line 60 is added overlying the interlayer dielectric ILD0 in the first metal layer (e.g., metal layer M0). The power line 60, extending along the X direction, is located directly above the gate conductor segment 128C.

[0048] Figure 5A This is a layout diagram of an integrated circuit according to some embodiments. Figure 5A The layout diagram in the middle is made by Figure 3A It is derived from the layout diagram in [the original text]. This modification includes [the following]. Figure 5A Replacement of layout patterns 534PM and 534QM Figure 3ALayout pattern 134M is specified in the diagram. Layout pattern 534PM specifies a cut to the dummy gate conductor specified in layout pattern 101M. Layout pattern 534QM specifies a cut to the gate conductor specified in layout pattern 128M and a cut to the dummy gate conductor specified in layout pattern 109M. Due to layout patterns 534PM and 534QM, the gate conductor specified in layout pattern 128M is cut in half, with one of the two segments extending through power line 60, allowing one gate conductor segment to be connected to power line 60.

[0049] Figure 5B Based on some embodiments Figure 5A A schematic diagram of an integrated circuit is formed based on the layout diagram. Figure 5B The integrated circuit in it is made of Figure 3B It is derived from the modification of integrated circuits. This modification includes... Figure 5B Gate conductor segments 522A and 522B are replaced Figure 3B Gate conductor segments 122A-122C are included. Gate conductor segments 522A and 522B form a column of two gate conductor segments aligned along the Y direction and defined by power lines 20 and 40. In some embodiments, gate conductor segment 522A is connected to power line 60 via a via connector passing through the interlayer dielectric ILD0 beneath the first metal layer. In some embodiments, power line 60 is a routing line (similarly formed by...). Figure 5A The layout pattern 60M is replaced, and the gate conductor segment 522A is connected to the routing line through a via connector passing through the interlayer dielectric ILD0 beneath the first metal layer.

[0050] Figure 6A This is a layout diagram of an integrated circuit according to some embodiments. Figure 6A The layout diagram in the middle is made by Figure 1A This layout was modified from the original. The modifications included replacing layout patterns 634PM and 634QM. Figure 1A Replace layout patterns 636PM and 636QM with layout pattern 134M. Figure 1A Replace layout pattern 674M with layout pattern 136M. Figure 1A The layout patterns 174PM and 174QM, and the replacement of layout pattern 676M. Figure 1ALayout patterns 176PM and 176QM are specified. Layout patterns 634PM and 636PM specify the cutting of the dummy gate conductor specified by layout pattern 101M and the cutting of the gate conductor specified by layout pattern 122M. Layout patterns 634QM and 636QM specify the cutting of the dummy gate conductor specified by layout pattern 109M. Layout patterns 674M and 676M specify the cutting of the terminal conductors specified by layout patterns 142M, 145M, and 148M. Due to layout patterns 634PM and 634QM, as well as layout patterns 636PM and 636QM, the gate conductor specified by layout pattern 128M is not cut in the region between the PMOS active region structure 50p and the NMOS active region structure 50n.

[0051] Figure 6B Based on some embodiments Figure 6A A schematic diagram of an integrated circuit is formed based on the layout diagram. Figure 6B The integrated circuit in it is made of Figure 1B It is derived from the modification of integrated circuits. This modification includes... Figure 6B Gate conductor segment 628 is replaced Figure 1B The gate conductor segments 128A-128C are replaced by terminal conductor segments 645A-645C. Gate conductor segment 628 forms a column of gate conductor segments aligned along the Y direction and defined by power lines 20 and 40. Because gate conductor segment 628 extends through both the PMOS active region structure 50p and the NMOS active region structure 50n, the gate terminals of the PMOS transistor and the NMOS transistor are connected together in the circuit cell.

[0052] Figure 7A This is a layout diagram of an integrated circuit according to some embodiments. Figure 7A The layout diagram in the middle is made by Figure 3A It is derived from the layout diagram in [the original text]. This modification includes using [the following text is incomplete and likely refers to a different source Figure 7A Replacement of layout pattern 776M Figure 1A The layout patterns 176PM and 176QM are used. Layout pattern 776M specifies the cutting of the terminal conductors specified by layout patterns 142M, 145M, and 148M. Due to layout pattern 776M, the terminal conductors specified by layout pattern 145M are cut in half, which allows one of the two segments to be connected to the power line 60.

[0053] Figure 7B Based on some embodiments Figure 7A A schematic diagram of an integrated circuit is formed based on the layout diagram. Figure 7B The integrated circuit in it is made of Figure 3BThe modification is derived from the integrated circuit in the image. The modification includes replacing terminal conductor segment 145 with terminal conductor segments 745A and 745B. Terminal conductor segments 745A and 745B form two columns of terminal conductor segments aligned along the Y direction and bounded by power lines 20 and 40. In some embodiments, terminal conductor segment 745A is connected to power line 60 via a through-hole connector passing through the interlayer dielectric ILD0 beneath the first metal layer. In some embodiments, power line 60 is connected by a routing line (which is similarly formed by...). Figure 5A The layout pattern 60M is replaced, and the terminal conductor segment 745A is connected to the routing line through a through-hole connector passing through the interlayer dielectric ILD0 beneath the first metal layer.

[0054] Apart from Figure 1B , Figure 3B , Figure 5B , Figure 6B and Figure 7B Besides the integrated circuits shown, other variations of integrated circuits are... Figures 8A-8B It is shown schematically in the diagram.

[0055] Figure 8A This is a schematic diagram of an integrated circuit, which is based on some embodiments. Figure 1B The transformation of integrated circuits in China. Figure 8A The integrated circuit includes active region structures 82, 84, 86, and 88 extending in the X direction. Each of gate conductor segments 122A and 128A intersects active region structures 82 and 84, and each of terminal conductor segments 142A, 145, and 148A also intersects active region structures 82 and 84. Each of gate conductor segments 122B and 128B interacts with active region structures 86 and 88, and each of terminal conductor segments 142B, 145, and 148B also intersects active region structures 86 and 88. In some embodiments, active region structures 82 and 86 are PMOS active region structures, and active region structures 84 and 88 are NMOS active region structures. Because there are four active region structures 82, 84, 86 and 88, two rows of PMOS transistors and two rows of NMOS transistors are implemented in the circuit unit.

[0056] Figure 8B This is a schematic diagram of an integrated circuit, which is based on some embodiments. Figure 8A The transformation of integrated circuits in China. Figure 8B The integrated circuit in the middle is from Figure 8A It is derived from the modification of integrated circuits, by adding it to the interlayer dielectric ILD0 (e.g.) Figure 4CA power line 60 extends in the X direction within a first metal layer (e.g., metal layer M0) of the interlayer dielectric (ILD0). The power line 60 intersects gate conductor segments 122C and 128C, terminal conductor segments 142C and 148C, and dummy gate conductor segments 101C and 109C. In some embodiments, the power line 60 is connected to the terminal conductor segment 145 via a through-hole connector. Figure 8A The circuit units in the middle are similar. Figure 8B The circuit units also include two rows of PMOS transistors and two rows of NMOS transistors.

[0057] Figure 9A This is a flowchart of a method 900A for manufacturing an integrated circuit according to some embodiments. Figure 9A The order of operations described in Method 900A is for illustrative purposes only; the operations of Method 900A can be performed in conjunction with... Figure 9A The different orders described herein shall be executed in order. It should be understood that additional operations may be performed... Figure 9A The methods described herein are performed before, during, and / or after 900A, and some other processes may be described only briefly here.

[0058] In operation 910 of method 900A, a first-type active region structure and a second-type active region structure extending along the X direction are fabricated on a substrate. The channel region, source region, and drain region of at least one first-type transistor are formed by the first-type active region structure. The channel region, source region, and drain region of at least one second-type transistor are formed by the second-type active region structure. In some embodiments, the first-type active region structure is a PMOS active region structure, and the second-type active region structure is an NMOS active region structure. In some embodiments, the first-type active region structure is an NMOS active region structure, and the second-type active region structure is a PMOS active region structure. Figure 1B and Figures 2A-2E In this embodiment, the PMOS active region structure 50p and the NMOS active region structure 50n are fabricated on the substrate 30.

[0059] In operation 920 of method 900A, a gate conductor extending along the Y direction is formed. Then, in operation 930 of method 900A, at least one gate conductor is etched to form a column of gate conductor segments. Figure 1B and Figures 2A-2E In the example embodiment, two gate conductors are formed intersecting with the PMOS active region structure 50p and the NMOS active region structure 50n. Each of the two gate conductors is formed by layout patterns 122M and 128M (e.g., ...). Figure 1AOne of the following is specified (as shown). Then, the gate conductors specified by the layout pattern 122M are etched to form gate conductor segments 122A, 122C and 122B aligned along the Y direction in the first column, and the gate conductors specified by the layout pattern 128M are etched to form gate conductor segments 128A, 128C and 128B aligned along the Y direction in the second column.

[0060] In operation 940 of method 900A, a terminal conductor extending along the Y direction is formed. Then, in operation 950 of method 900A, at least one terminal conductor is etched to form a row of terminal conductor segments. Figure 1B and Figures 2A-2E In this embodiment, three terminal conductors are formed that intersect with the PMOS active region structure 50p and the NMOS active region structure 50n. Each of the two terminal conductors is formed by layout patterns 142M, 145M, and 148M (e.g., Figure 1A One of the terminal conductors specified in the diagram is then etched to form terminal conductor segments 142A, 142C and 142B aligned along the Y direction in the first column, and terminal conductors specified in the layout pattern 148M are etched to form terminal conductor segments 148A, 148C and 148C aligned along the Y direction in the second column.

[0061] In operation 960 of method 900A, an interlayer dielectric layer is deposited to cover the columns of gate conductor segments and the columns of terminal conductor segments. Figure 1B and Figures 2A-2E In one embodiment, an interlayer dielectric ILD0 is deposited to cover gate conductor segments 122A-122C and 128A-128C, and terminal conductor segments 142A-142C and 148A-148C. After operation 960, the process proceeds to operation 970.

[0062] In operation 970 of method 900A, a first metal layer is deposited on the interlayer dielectric layer. Then, in operation 980 of method 900A, the first metal layer is etched to create a first power line and a second power line. Figure 1B and Figures 2A-2E In one embodiment, a metal layer M0 is deposited on an interlayer dielectric ILD0. Subsequently, the metal layer M0 is etched to create power lines 20 and 40 extending in the X direction.

[0063] Figure 9B This is a flowchart of a method 900B for manufacturing an integrated circuit according to some embodiments. Figure 9B The order of operations described in Method 900B is for illustrative purposes only; the operations of Method 900B can be combined with... Figure 9B The different orders described herein shall be executed in order. It should be understood that additional operations may be performed... Figure 9BThe methods described herein are performed before, during, and / or after 900B, and some other processes may be described only briefly here.

[0064] Figure 9B The flowchart in the middle is made by Figure 9A This is derived from a flowchart modification. The modification includes adding operation 965B between operations 960 and 970. The modification also includes using... Figure 9B Operation 980B replacement Figure 9A Operation 980. In Figure 9B In the process flow from operation 910 to operation 960 of method 900B, and... Figure 9A The process flow from operation 910 to operation 960 in method 900A is the same. In method 900B, the process flow after operation 960 is the same. Figure 9A The flow differs in method 900A. Specifically, in method 900B, after operation 960, the process proceeds to operation 965B.

[0065] In operation 965B of method 900B, one or more through-hole connectors are fabricated that pass through layers of interlayer dielectric. Figure 3B and Figures 4A-4E In this embodiment, a through-hole connector 495 is fabricated through the interlayer dielectric ILD0. After operation 965B, the process proceeds to operation 970.

[0066] In operation 970 of method 900B, a first metal layer is deposited on the interlayer dielectric layer. Then, in operation 980B of method 900B, the first metal layer is etched to create a first power line, a second power line, and a third power line. Figure 3B and Figures 4A-4E In this embodiment, a metal layer M0 is deposited on an interlayer dielectric ILD0. Subsequently, the metal layer M0 is etched to create power lines 20, 40, and 60 extending in the X direction. After power line 60 is fabricated, as shown... Figure 4C As shown, the through-hole connector 495 connects the power line 60 to the terminal conductor section 145.

[0067] Figure 10 This is a block diagram of an electronic design automation (EDA) system 1000 according to some embodiments.

[0068] In some embodiments, the EDA system 1000 includes an automatic placement and routing (APR) system. According to one or more embodiments, the design layout diagrams described herein represent wire routing arrangements that may be implemented, for example, using the EDA system 1000.

[0069] In some embodiments, the EDA system 1000 is a general-purpose computing device, including a hardware processor 1002 and a non-transitory computer-readable storage medium 1004. The computer-readable storage medium 1004 is specifically encoded with storage computer-programmed code 1006, i.e., a set of executable instructions. Execution of the computer-programmed code 1006 by the hardware processor 1002 represents (at least a portion) of an EDA tool, implementing some or all of the methods described herein according to one or more embodiments (the processes and / or methods mentioned below).

[0070] Processor 1002 is electrically coupled to computer-readable storage medium 1004 via bus 1008. Processor 1002 is also electrically coupled to I / O interface 1010 via bus 1008. Network interface 1012 is also electrically connected to processor 1002 via bus 1008. Network interface 1012 is connected to network 1014, enabling processor 1002 and computer-readable storage medium 1004 to be connected to external components via network 1014. Processor 1002 is configured to execute computer-programmed code 1006 in computer-readable storage medium 1004 to make system 1000 available for performing some or all of the aforementioned processes and / or methods. In one or more embodiments, processor 1002 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0071] In one or more embodiments, the computer-readable storage medium 1004 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1004 includes semiconductor or solid-state memory, magnetic magnetic tape, removable computer diskette, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disc. In one or more embodiments, the computer-readable storage medium 1004 includes optical disc read-only memory (CD-ROM), CD-R / W, and / or digital video disc (DVD).

[0072] In one or more embodiments, computer-readable storage medium 1004 stores computer-programmed code 1006 configured to enable system 1000 (where such execution representation (at least partially) of an EDA tool) to perform some or all of the mentioned processes and / or methods. In one or more embodiments, computer-readable storage medium 1004 also stores information conducive to performing some or all of the mentioned processes and / or methods. In one or more embodiments, computer-readable storage medium 1004 stores a standard cell library 1007 including such standard cells disclosed herein. In one or more embodiments, computer-readable storage medium 1004 stores one or more layout diagrams 1009 corresponding to one or more layouts disclosed herein.

[0073] EDA system 1000 includes an I / O interface 1010. The I / O interface 1010 is coupled to external circuitry. In one or more embodiments, the I / O interface 1010 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 1002.

[0074] EDA system 1000 also includes a network interface 1012 coupled to processor 1002. Network interface 1012 allows system 1000 to communicate with network 1014 and connect to one or more other computer systems. Network interface 1012 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more systems 1000.

[0075] System 1000 is configured to receive information to I / O interface 1010. The information received through I / O interface 1010 includes one or more of the following: instructions, data, design rules, standard unit libraries, and / or other parameters processed by processor 1002. The information is transmitted to processor 1002 via bus 1008. EDA system 1000 is configured to receive information related to the user interface (UI) through I / O interface 1010. The information is stored in computer-readable storage medium 1004 as a user interface 1042.

[0076] In some embodiments, some or all of the mentioned processes and / or methods are implemented by a processor-executed standalone software application. In some embodiments, some or all of the mentioned processes and / or methods are implemented by a processor-executed standalone software application that is part of an additional software application. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a plug-in to a processor-executed standalone software application. In some embodiments, at least one of the processes and / or methods is implemented by a processor-executed standalone software application that is part of an EDA tool. In some embodiments, some or all of the mentioned processes and / or methods are implemented by a processor-executed standalone software application that is a software application used by EDA system 1000. In some embodiments, applications such as those available from Cadence Design Systems, Inc. are used. Use system design platforms or other suitable layout generation tools to generate layout diagrams that include standard cells.

[0077] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as optical discs, such as DVDs; magnetic disks, such as hard disks; semiconductor memories, such as ROMs, RAMs, memory cards, etc.

[0078] Figure 11 This is a block diagram of an integrated circuit (IC) manufacturing system 1100 and associated IC manufacturing processes according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 1100 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0079] exist Figure 11In this IC manufacturing system 1100, entities such as a design house 1120, a mask house 1130, and IC manufacturers / fabrication plants (e.g., semiconductor fabs) 1150 interact with each other in the design, development, and manufacturing cycles and / or services associated with manufacturing IC devices 1160. The entities in system 1100 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is multiple different networks, such as intranets and the internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design house 1120, mask house 1130, and IC semiconductor fab 1150 are owned by a larger enterprise. In some embodiments, two or more of the design house 1120, mask house 1130, and IC semiconductor fab 1150 coexist in a shared facility and use shared resources.

[0080] Design studio 1120 (or design team) generates IC design layout 1122. IC design layout 1122 includes various geometric patterns for designing IC device 1160. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 1160 to be manufactured. These layers combine to form various IC features. For example, portions of IC design layout 1122 include various IC features to be formed in a semiconductor substrate (e.g., a silicon wafer), such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, openings for bonding pads, and various material layers disposed on the substrate semiconductor. Design studio 1120 performs appropriate design processes to form IC design layout 1122. These design processes include logic design, physical design, or place and route. IC design layout 1122 is presented in one or more files containing information about the geometric patterns. For example, IC design layout 1122 may be represented in GDSII or DFII file format.

[0081] Mask chamber 1130 includes data preparation 1132 and mask fabrication 1144. Mask chamber 1130 uses IC design layout 1122 to fabricate one or more masks 1145 for fabricating various layers of IC device 160 according to IC design layout 1122.

[0082] Mask chamber 1130 performs mask data preparation 1132, in which the IC design layout 1122 is converted into a representative data file (RDF). Mask data preparation 1132 provides the RDF to mask fabrication 1144. Mask fabrication 1144 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as mask 1145 (master photomask, reticle) or semiconductor wafer 1153. The IC design layout 1122 is manipulated by mask data preparation 1132 to conform to the specific characteristics of the mask writer and / or the requirements of the IC semiconductor fabrication plant 1150. Figure 11 In this embodiment, mask data preparation 1132 and mask manufacturing 1144 are shown as separate elements. In some embodiments, mask data preparation 1132 and mask manufacturing 1144 may be collectively referred to as mask data preparation.

[0083] In some embodiments, mask data preparation 1132 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout diagram 1122. In some embodiments, mask data preparation 1132 also includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, and similar or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0084] In some embodiments, mask data preparation 1132 includes a mask rule checker (MRC) that checks the IC design layout 1122, which has already undergone processes in the OPC, using a set of mask creation rules. These rules include certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1122 to compensate for the effects of photolithography implementation during mask fabrication 1144, which may undo portions of the modifications performed by the OPC to satisfy the mask building rules.

[0085] In some embodiments, mask preparation 1132 includes a lithography process check (LPC), which simulates a process performed by an IC semiconductor manufacturing plant 1150 to manufacture an IC device 1160. The LPC simulates this process based on an IC design layout 1122, creating a simulated manufactured device, such as IC device 1160. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar or combinations thereof. In some embodiments, after creating the simulated manufactured device via LPC, if the simulated device shape is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1122.

[0086] It should be understood that the above description of mask data preparation 1132 has been simplified for clarity. In some embodiments, data preparation 1132 may also include additional features, such as logic operations (LOPs), to modify the IC design layout 1122 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1122 during data preparation 1132 may be performed in various different sequences.

[0087] Following mask data preparation 1132 and during mask fabrication 1144, a mask 1145 or a set of masks 1145 is fabricated based on the modified IC design layout 1122. In some embodiments, mask fabrication 1144 includes performing one or more photolithographic exposures based on the IC design layout 1122. In some embodiments, an electron beam or multiple electron beam apparatus forms a pattern on the mask 1145 (photomask or master photomask, reticle) based on the modified IC design layout 1122. The mask 1145 can be formed using a variety of techniques. In some embodiments, the mask 1145 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. The image-sensitive material layer (e.g., photoresist) coated on the wafer is exposed with a radiation beam (e.g., an ultraviolet (UV) beam), wherein the radiation beam is blocked by the opaque areas and passes through the transparent areas. In one example, the binary mask version of mask 1145 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in opaque regions of the binary mask. In another example, mask 1145 is formed using a phase-shifting technique. In the phase-shifting mask (PSM) version of mask 1145, various features in the pattern formed on the phase-shifting mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase-shifting mask can be attenuated PSM or alternating PSM. The mask generated by mask fabrication 1144 is used in various processes. For example, such a mask is used in ion implantation processes to form various doped regions in semiconductor wafer 1153, in etching processes to form various etched regions in semiconductor wafer 1153, and / or in other suitable processes.

[0088] IC semiconductor manufacturing plant 1150 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC semiconductor manufacturing plant 1150 is a semiconductor foundry. For example, there may be a first manufacturing plant that can be used for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, while a second manufacturing plant may provide back-end final manufacturing (back-end process (BEOL) manufacturing) for the interconnection and packaging of IC products, and a third manufacturing plant may provide other services for foundry operations.

[0089] IC semiconductor manufacturing plant 1150 includes manufacturing tools 1152 configured to perform various manufacturing operations on semiconductor wafer 1153, thereby manufacturing IC device 1160 according to a mask (e.g., mask 1145). In various embodiments, manufacturing tools 1152 include one or more of the following: wafer stepper, ion implanter, photoresist coater, process chamber such as a CVD chamber or LPCVD furnace, CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more manufacturing processes.

[0090] IC semiconductor manufacturing plant 1150 uses a mask 1145, fabricated in mask chamber 1130, to manufacture IC device 1160. Therefore, IC semiconductor manufacturing plant 1150 uses IC design layout 1122 at least indirectly to manufacture IC device 1160. In some embodiments, IC semiconductor manufacturing plant 1150 uses mask 1145 to fabricate semiconductor wafer 1153 to form IC device 1160. In some embodiments, IC fabrication includes performing one or more photolithographic exposures at least indirectly based on IC design layout 1122. Semiconductor wafer 1153 includes a silicon substrate or other suitable substrate on which material layers are formed. Semiconductor wafer 1153 also includes one or more of various doped regions, dielectric features, multilayer interconnects, and the like (formed in subsequent manufacturing steps).

[0091] In some embodiments, an integrated circuit includes: a first type active region structure and a second type active region structure extending along a first direction; a first power line and a second power line extending along the first direction; and a column of three gate conductor segments aligned along a second direction and bounded by the first power line and the second power line, wherein the three gate conductor segments include an intermediate gate conductor segment located between the first gate conductor segment and the second gate conductor segment, the first gate conductor segment intersecting the first type active region structure at a channel region of a first type transistor, and the second gate conductor segment intersecting the second type active region structure at a channel region of a second type transistor, and wherein the second direction is perpendicular to the first direction.

[0092] In some embodiments, the system further includes: a third power line extending in the second direction, the third power line intersecting the intermediate gate conductor segment. In some embodiments, the system further includes: a column of three terminal conductor segments aligned along the second direction and bounded by the first power line and the second power line, wherein the three terminal conductor segments include an intermediate terminal conductor segment between the first terminal conductor segment and the second terminal conductor segment, the first terminal conductor segment intersecting the first type active region structure at a terminal region of the first type transistor, wherein the second terminal conductor segment intersecting the second type active region structure at a terminal region of the second type transistor, and wherein each terminal region is a source region or a drain region. In some embodiments, the system further includes: a third power line extending in the second direction, the third power line intersecting each of the intermediate terminal conductor segment and the intermediate gate conductor segment. In some embodiments, the system further includes: a column of two terminal conductor segments aligned along the second direction and bounded by the first power line and the second power line, wherein the column of two terminal conductor segments includes a first terminal conductor segment intersecting the first type active region structure at the terminal region of the first type transistor, and wherein the column of two terminal conductor segments includes a second terminal conductor segment intersecting the second type active region structure at the terminal region of the second type transistor. In some embodiments, the system further includes: a third power line extending along the second direction and intersecting the first terminal conductor segment; and a through-hole connector connecting the third power line and the first terminal conductor segment. In some embodiments, the system further includes: a terminal conductor segment extending along the second direction and bounded by the first power line and the second power line, wherein the terminal conductor segment intersects the first type active region structure and the second type active region structure. In some embodiments, the system further includes: a third power line extending along the second direction between the first power line and the second power line; and a through-hole connector connecting the third power line and the terminal conductor segment.

[0093] In some embodiments, an integrated circuit includes: a first type of active region structure and a second type of active region structure extending along a first direction; a first power line and a second power line extending along the first direction; and a circuit unit having a first horizontal unit boundary and a second horizontal unit boundary extending along the first direction, wherein the first horizontal unit boundary overlaps with the first power line and the second horizontal unit boundary overlaps with the second power line, and wherein the circuit unit includes: a column of three terminal conductor segments aligned along a second direction and bounded by the first horizontal unit boundary and the second horizontal unit boundary, the second direction being perpendicular to the first direction, wherein the three terminal conductor segments include an intermediate terminal conductor segment between the first terminal conductor segment and the second terminal conductor segment, wherein the first terminal conductor segment intersects the first type of active region structure at a terminal region of a first type of transistor, wherein the second terminal conductor segment intersects the second type of active region structure at a terminal region of a second type of transistor, and wherein each terminal region is a source region or a drain region.

[0094] In some embodiments, the circuit further includes: a third power line extending along the second direction, the third power line intersecting the intermediate terminal conductor segment. In some embodiments, the circuit unit further includes: a column of three gate conductor segments aligned along the second direction and bounded by the first horizontal cell boundary and the second horizontal cell boundary, wherein the three gate conductor segments include an intermediate gate conductor segment between a first gate conductor segment and a second gate conductor segment, the first gate conductor segment intersecting the first type active region structure at the channel region of the first type transistor, and the second gate conductor segment intersecting the second type active region structure at the channel region of the second type transistor, and wherein the second direction is perpendicular to the first direction. In some embodiments, the circuit further includes: a third power line extending along the second direction, the third power line intersecting each of the intermediate terminal conductor segment and the intermediate gate conductor segment. In some embodiments, the circuit further includes: a first isolation region and a second isolation region located in the first type of active region structure; and a third isolation region and a fourth isolation region located in the second type of active region structure, wherein the third isolation region in the second type of active region structure and the first isolation region in the first type of active region structure are vertically aligned along a second direction and delineate a first vertical cell boundary of the circuit cell, and wherein the fourth isolation region in the second type of active region structure and the second isolation region in the first type of active region structure are vertically aligned along the second direction and delineate a second vertical cell boundary of the circuit cell; wherein the column of three gate conductor segments and the column of three terminal conductor segments are located between the first vertical cell boundary and the second vertical cell boundary. In some embodiments, the circuit cell further includes: a column of two gate conductor segments aligned along the second direction and bounded by the first horizontal cell boundary and the second horizontal cell boundary, wherein the column of two gate conductor segments includes a first gate conductor segment and a second gate conductor segment, wherein the first gate conductor segment intersects the first type of active region structure at the channel region of the first type of transistor, and wherein the second gate conductor segment intersects the second type of active region structure at the channel region of the second type of transistor. In some embodiments, the circuit unit further includes a gate conductor segment extending along the second direction and bounded by the first horizontal cell boundary and the second horizontal cell boundary, wherein the gate conductor segment intersects both the first type active region structure and the second type active region structure.

[0095] In some embodiments, a method of forming an integrated circuit includes: forming a first type active region structure and a second type active region structure extending along a first direction on a substrate; forming a gate conductor extending along a second direction perpendicular to the first direction; forming a column of three gate conductor segments from the gate conductor, wherein the column of three gate conductors includes an intermediate gate conductor segment between the first gate conductor segment and the second gate conductor segment, the first gate conductor segment intersecting the first type active region structure at a channel region of a first type transistor, and the second gate conductor segment intersecting the second type active region structure at a channel region of a second type transistor; depositing an interlayer dielectric layer to cover the column of three gate conductor segments, the first type active region structure, and the second type active region structure; depositing a first metal layer on the interlayer dielectric layer; and forming a first power line and a second power line extending along the first direction in the first metal layer, wherein the column of three gate conductor segments is bounded by the first power line and the second power line.

[0096] In some embodiments, the method further includes: forming a third power line extending along the first direction in the first metal layer, wherein the third power line intersects the intermediate gate conductor segment. In some embodiments, the method further includes: forming a terminal conductor extending along the second direction; and forming a column of three terminal conductor segments by the terminal conductor, wherein the column of three terminal conductor segments includes an intermediate terminal conductor segment between a first terminal conductor segment and a second terminal conductor segment, the first terminal conductor segment intersecting a first-type active region structure at a terminal region of the first-type transistor, and the second terminal conductor segment intersecting a second-type active region structure at a terminal region of the second-type transistor. In some embodiments, the method further includes: forming a third power line extending along the first direction in the first metal layer, wherein the third power line intersects both the intermediate gate conductor segment and the intermediate terminal conductor segment. In some embodiments, the method further includes: forming a terminal conductor extending along the second direction; forming a column of two terminal conductor segments from the terminal conductor, wherein the column of two terminal conductor segments includes a first terminal conductor segment and a second terminal conductor segment, the first terminal conductor segment intersecting the first type active region structure at the terminal region of the first type transistor, and the second terminal conductor segment intersecting the second active region structure at the terminal region of the second type transistor; and forming a third power line extending along the first direction in the first metal layer, wherein the third power line intersects the intermediate gate conductor segment and the first terminal conductor segment.

[0097] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this invention. Those skilled in the art should understand that this invention can be used as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this invention.

Claims

1. An integrated circuit, characterized in that, include: The first type of active region structure and the second type of active region structure extend along the first direction; The first power line and the second power line extend along the first direction; as well as A column of three gate conductor segments, aligned along a second direction and bounded by the first power line and the second power line, wherein the three gate conductor segments include an intermediate gate conductor segment located between the first gate conductor segment and the second gate conductor segment, the first gate conductor segment intersecting the first type active region structure at the channel region of the first type transistor, and the second gate conductor segment intersecting the second type active region structure at the channel region of the second type transistor, wherein the second direction is perpendicular to the first direction.

2. The integrated circuit according to claim 1, characterized in that, Also includes: A third power line extends in the second direction and intersects with the intermediate gate conductor segment.

3. The integrated circuit according to claim 1, characterized in that, Also includes: A column of three terminal conductor segments, aligned along the second direction and bounded by the first power line and the second power line, wherein the three terminal conductor segments include an intermediate terminal conductor segment between the first terminal conductor segment and the second terminal conductor segment, the first terminal conductor segment intersecting the first type active region structure at the terminal region of the first type transistor, wherein the second terminal conductor segment intersecting the second type active region structure at the terminal region of the second type transistor, and wherein each terminal region is a source region or a drain region.

4. The integrated circuit according to claim 3, characterized in that, Also includes: A third power line extends along the second direction and intersects each of the intermediate terminal conductor segment and the intermediate gate conductor segment.

5. The integrated circuit according to claim 1, characterized in that, Also includes: The column of two terminal conductor segments is aligned along the second direction and bounded by the first power line and the second power line, wherein the column of two terminal conductor segments includes a first terminal conductor segment that intersects with the first type active region structure at the terminal region of the first type transistor, and wherein the column of two terminal conductor segments includes a second terminal conductor segment that intersects with the second type active region structure at the terminal region of the second type transistor.

6. The integrated circuit according to claim 1, characterized in that, Also includes: A terminal conductor segment extends along the second direction and is bounded by the first power line and the second power line, wherein the terminal conductor segment intersects with the first type active region structure and the second type active region structure.

7. An integrated circuit, characterized in that, include: The first type of active region structure and the second type of active region structure extend along the first direction; The first power line and the second power line extend along the first direction; as well as A circuit unit has a first horizontal unit boundary and a second horizontal unit boundary extending along the first direction, wherein the first horizontal unit boundary overlaps with the first power line and the second horizontal unit boundary overlaps with the second power line, and wherein the circuit unit includes: A column of three terminal conductor segments, aligned along a second direction and bounded by the first horizontal cell boundary and the second horizontal cell boundary, the second direction being perpendicular to the first direction, wherein the three terminal conductor segments include an intermediate terminal conductor segment between a first terminal conductor segment and a second terminal conductor segment, wherein the first terminal conductor segment intersects with the first type active region structure at the terminal region of the first type transistor, wherein the second terminal conductor segment intersects with the second type active region structure at the terminal region of the second type transistor, and wherein each terminal region is a source region or a drain region.

8. The integrated circuit according to claim 7, characterized in that, Also includes: A third power line extends along the second direction and intersects with the intermediate terminal conductor segment.

9. The integrated circuit according to claim 7, characterized in that, The circuit unit further includes: A column of three gate conductor segments, aligned along a second direction and bounded by the first horizontal cell boundary and the second horizontal cell boundary, wherein the three gate conductor segments include an intermediate gate conductor segment between a first gate conductor segment and a second gate conductor segment, the first gate conductor segment intersecting the first type active region structure at the channel region of the first type transistor, and the second gate conductor segment intersecting the second type active region structure at the channel region of the second type transistor, and wherein the second direction is perpendicular to the first direction.

10. The integrated circuit according to claim 9, characterized in that, Also includes: The first isolation zone and the second isolation zone are located in the first type of active region structure; as well as The third and fourth isolation regions are located in the second type of active region structure, wherein the third isolation region in the second type of active region structure and the first isolation region in the first type of active region structure are vertically aligned along the second direction and depict the first vertical unit boundary of the circuit cell, and wherein the fourth isolation region in the second type of active region structure and the second isolation region in the first type of active region structure are vertically aligned along the second direction and depict the second vertical unit boundary of the circuit cell; The columns of the three gate conductor segments and the columns of the three terminal conductor segments are located between the first vertical cell boundary and the second vertical cell boundary.

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