Semiconductor structure

Abstract

The semiconductor structure includes a circuit region, a seal ring region, and at least one alignment mark. The seal ring region surrounds the circuit region and includes a seal ring corner region. A seal ring is disposed in the seal ring region and includes a corner seal ring portion in the seal ring corner region. The corner seal ring portion divides the seal ring corner region into a plurality of sub-regions, and the at least one alignment mark is disposed in at least one of the sub-regions of the seal ring corner region.

Description

Technical Field

[0001] This utility model relates to a semiconductor structure. Background Technology

[0002] In recent years, the semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, improvements in integration density stem from the continuous reduction in the minimum feature size, which allows more components to be integrated into a given area.

[0003] These smaller electronic components also require smaller packages that occupy less area than previous packages. Examples of semiconductor package types include quad flat packs (QFP), pin grid arrays (PGA), ball grid arrays (BGA), flip chips (FC), three-dimensional integrated circuits (3DIC), wafer-level packages (WLP), and package-on-package (PoP) devices. Some 3DICs are fabricated by placing chips on top of each other on a semiconductor wafer level. 3DICs offer improved integration density and other advantages, such as faster speeds and higher bandwidth, due to the reduced length of interconnects between stacked chips. However, many challenges remain associated with 3DICs. Utility Model Content

[0004] The semiconductor structure of this embodiment includes a circuit region, a sealing ring region, and at least one alignment mark. The sealing ring region surrounds the circuit region and includes a sealing ring corner region. The sealing ring is disposed in the sealing ring region and includes a corner sealing ring portion in the corner sealing ring region. The corner sealing ring portion divides the corner sealing ring region into a plurality of sub-regions, and at least one alignment mark is disposed in at least one sub-region of the corner sealing ring region.

[0005] The semiconductor structure of this embodiment includes a circuit region, a sealing ring, and at least one alignment mark. The sealing ring surrounds the circuit region. The alignment mark is disposed at an inner corner of the sealing ring and is separated from the sealing ring, wherein the at least one alignment mark has an axis of symmetry substantially perpendicular to the surface of the at least one alignment mark.

[0006] The semiconductor structure of this embodiment includes a circuit region, a first sealing ring, and a plurality of alignment marks. The first sealing ring surrounds the circuit region. The plurality of alignment marks are disposed at the inner corners of the first sealing ring, wherein the alignment marks are separated from each other by the first sealing ring therebetween. Attached Figure Description

[0007] This disclosure can be better understood when read in conjunction with the accompanying drawings in the following detailed description. It should be emphasized that, in accordance with industry standard practice, the features are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the features may be increased or decreased arbitrarily.

[0008] Figure 1 This is a cross-sectional view of a semiconductor structure according to some embodiments.

[0009] Figure 2A This is a simplified top view of a semiconductor structure according to some embodiments. Figure 2B yes Figure 2A A magnified view of a region of a semiconductor structure. Figure 2C yes Figure 2B A three-dimensional view of the alignment mark.

[0010] Figures 3A to 3F These are schematic top views of alignment marks according to some embodiments.

[0011] Figures 4A to 4G These are schematic top views of alignment marks according to some embodiments.

[0012] Figures 5A to 5C They are Figure 2A An enlarged view of a region of a semiconductor structure.

[0013] Figures 6A to 6E This is a schematic cross-sectional view of the various stages in a method for forming a semiconductor structure according to some embodiments.

[0014] Figures 7A to 7E This is a simplified top view of the various stages in a method for forming a semiconductor structure according to some embodiments.

[0015] Figure 8 This is a cross-sectional view of a semiconductor structure according to some embodiments. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features may be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be reused in various instances throughout this disclosure. This reuse is for the sake of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Additionally, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0018] Other features and processes may also be included. For example, test structures may be included to aid in verification testing of 3D packaged or three-dimensional integrated circuit devices. These test structures may include, for example, test pads formed in redistribution layers or on a substrate, to enable testing of 3D packaged or three-dimensional integrated circuits, use of probes and / or probe cards, and similar operations. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods including intermediate verification of known good dies to improve yield and reduce costs.

[0019] Figure 1 This is a cross-sectional view of a semiconductor structure according to some embodiments. Figure 2A This is a simplified top view of a semiconductor structure according to some embodiments. Figure 2B yes Figure 2A A magnified view of region A of the semiconductor structure. Figure 2C yes Figure 2B A three-dimensional view of the alignment mark.

[0020] Reference Figure 1 and Figure 2AThe semiconductor structure includes an integrated circuit 100. The integrated circuit 100 includes a circuit region 102 and a sealing ring region 104 surrounding the circuit region 102. The integrated circuit 100 may be a wafer-level structure (e.g., before dicing) or a chip-level structure (e.g., after dicing). The circuit region 102 and the sealing ring region 104 constitute a die region or a chip region of the integrated circuit 100. For example, as... Figure 2A As shown, a dicing line region 105 surrounds a sealing ring region 104, and the integrated circuit 100 is diced (or cut) along a dicing line 105a of the dicing line region 105. The sealing ring region 104 remains intact during the dicing process and provides sealing and protection for the circuit region 102. In some embodiments, the sealing ring region 104 includes four sealing ring corner regions 106 at its corners. The sealing ring corner regions 106 may be triangular or substantially triangular. For example, the periphery of the sealing ring corner region 106 may be substantially a right triangle or an isosceles right triangle. In some embodiments, one sealing ring region 104 surrounds one circuit region 102. In alternative embodiments (not shown), one sealing ring region 104 surrounds multiple circuit regions 102.

[0021] Integrated circuit 100 can be a die, such as an application-specific integrated circuit (ASIC) chip, analog chip, sensor chip, wireless radio frequency chip, voltage regulator chip, or memory chip. For example... Figure 1 As shown, integrated circuit 100 may include semiconductor substrate 120, component 122, interconnect structure 124, sealing ring structure SR, and alignment mark AM. Semiconductor substrate 120 and interconnect structure 124 are stacked along direction D1. Direction D1 is a vertical direction (e.g., the Z direction), direction D2, which is substantially perpendicular to direction D1, is a horizontal direction (e.g., the X direction), and direction D3, which is substantially perpendicular to both direction D1 and direction D2, is a horizontal direction (e.g., the X direction). Figure 2A The direction shown is also horizontal (e.g., the Y direction). Semiconductor substrate 120 may be a semiconductor substrate, such as a silicon substrate, a doped or undoped active layer of a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 120 may contain other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer substrates or gradient substrates, may also be used. Semiconductor substrate 120 has a first side and a second side opposite to the first side. For example, the first side is the front side (e.g., in...). Figure 1The middle side faces upward), and the second side is the dorsal side (for example, in...). Figure 1 (Middle side down).

[0022] In some embodiments, the semiconductor substrate 120 includes an isolation structure (not shown) defining at least one active region, and a component layer is disposed on or within the active region. The component layer may include various components 122. Components 122 are, for example, transistors, capacitors, resistors, diodes, photodiodes, fuses, or other similar components. In some embodiments, component 122 includes a gate structure, source / drain regions, spacers, and the like.

[0023] Interconnect structure 124 is disposed over a first side (e.g., the front side) of semiconductor substrate 120. Specifically, interconnect structure 124 is electrically connected to a component layer within circuit region 102. In some embodiments, interconnect structure 124 includes at least one dielectric layer 126 and a plurality of conductive features 128. For example, conductive features 128 are disposed in dielectric layer 126 and electrically connected to each other. Some conductive features 128, such as top conductive feature 128a, are exposed to dielectric layer 126. In some embodiments, dielectric layer 126 includes an interlayer dielectric (ILD) layer on semiconductor substrate 120 and at least one intermetallic dielectric (IMD) layer on the interlayer dielectric layer. In some embodiments, dielectric layer 126 includes silicon oxide, silicon oxynitride, silicon nitride, a low-k material, or a combination thereof. Dielectric layer 126 may be a single-layer or multi-layer structure. In some embodiments, conductive features 128 include plugs and wires. Plugs may include contacts formed in the interlayer dielectric layer and vias formed in the intermetallic dielectric layer. Contacts are formed between and contact the bottom metal line and the component layer. Vias are formed between and contact the two metal lines. The conductive feature 128 may include tungsten (W), copper (Cu), copper alloy, aluminum (Al), aluminum alloy, or combinations thereof. In some embodiments, a barrier layer (not shown) may be disposed between the conductive feature 128 and the dielectric layer 126 to prevent material migration of the conductive feature 128 to the component layer. For example, the barrier layer includes Ta, TaN, Ti, TiN, CoW, or combinations thereof. In some embodiments, the interconnect structure 124 is formed by multiple single damascene processes, dual damascene processes, electroplating processes, or similar processes.

[0024] In some embodiments, such as Figure 1As shown, a bonding structure 170 is disposed below the interconnect structure 124 within the circuit region 102. In some embodiments, the bonding structure 170 includes at least one bonding dielectric layer 172 and a plurality of bonding conductive features. In some embodiments, the bonding dielectric layer 172 includes silicon oxide, silicon nitride, a polymer, or a combination thereof. The bonding conductive features are disposed in the bonding dielectric layer 172 and electrically connected to each other. In some embodiments, the bonding conductive features include a bonding via 174 electrically connected to the interconnect structure 124 and a bonding pad 176 electrically connected to the bonding via 174. The bonding conductive features may include tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, or a combination thereof. In some embodiments, the bonding via 174 further extends through the semiconductor substrate 120. Therefore, the bonding via 174 is also referred to as a through-silicon via (TSV) or a semiconductor via (also called a TSV). In some embodiments, a barrier layer (not shown) is disposed between the bonding conductive features and the bonding dielectric layer 172. For example, the barrier layer includes Ta, TaN, Ti, TiN, CoW, or a combination thereof. In some embodiments, the bonding structure 170 is formed by multiple single inlay processes, dual inlay processes, electroplating processes, or similar processes.

[0025] In some embodiments, the integrated circuit 100 includes a plurality of conductive pads 180 in a dielectric layer 182. For example, an interconnect structure 124 is disposed between a semiconductor substrate 120 and the conductive pads 180, and the semiconductor substrate 120 is disposed between a bonding structure 170 and the interconnect structure 124. The conductive pads 180 may be disposed near a top conductive feature 128a and an alignment mark AM. The conductive pads 180 are, for example, aluminum pads.

[0026] like Figure 2B As shown, the sealing ring structure SR includes sealing rings 130 and 150 on a first side (e.g., the front side) of the semiconductor substrate 120. Specifically, the sealing rings 130 and 150 are disposed on and electrically insulated from the underlying component layer and are located on one side of the interconnect structure 124 within the sealing ring region 104. In some embodiments, such as Figure 1 As shown, sealing rings 130 and 150 are formed during the formation of interconnect structure 124. Sealing rings 130 and 150 may include a stack of virtual conductive features 131, such as virtual wires and / or virtual vias.

[0027] Here, when components are described as "substantially at the same height," these components are formed at substantially the same height in the same layer or have the same position embedded in the same layer. In some embodiments, components at substantially the same height are formed from the same material through the same process steps. In some embodiments, the tops of components at substantially the same height are substantially coplanar. For example, as... Figure 1As shown, the sealing rings 130 and 150 are substantially at the same height as the interconnect structure 124. Specifically, the surfaces (e.g., top surfaces) S2 of the sealing rings 130 and 150 are substantially coplanar with the surfaces (e.g., top surfaces) S1 of the top conductive features 128a of the interconnect structure 124.

[0028] Reference Figure 2B The sealing ring 130 includes a main portion 132 and four corner sealing ring portions 140 located at the four interior corners of the main portion 132. The sealing ring 130 is disposed in the sealing ring region 104, and the four corner sealing ring portions 140 are disposed in the sealing ring corner region 106. In some embodiments, the main portion 132 is a rectangular ring or substantially rectangular ring, and the inner and outer contours of the main portion 132 respectively form substantially rectangular peripheries. For example, the main portion 132 includes a first portion 132a extending in direction D2, a second portion 132b extending in direction D3, and a third portion 132c between the first portion 132a and the second portion 132b. The third portion 132c is, for example, an inclined portion. In the illustrated embodiment, the inner contour (or inner boundary) of the sealing ring 130 is octagonal or substantially octagonal.

[0029] In some embodiments, the corner sealing ring portion 140 includes a bridging segment 142 and an L-shaped segment 144. The bridging segment 142 may include a continuous linear feature and extends between a first side (e.g., first portion 132a) and a second side (e.g., second portion 132b) of the sealing ring 130 (e.g., the main portion 132). For example, a first connection portion is formed between the bridging segment 142 and the first portion 132a of the main portion 132, and a second connection portion is formed between the bridging segment 142 and the second portion 132b of the main portion 132. The L-shaped segment 144 may also extend between the first side (e.g., first portion 132a) and the second side (e.g., second portion 132b) of the sealing ring 130 (e.g., the main portion 132). For example, a third connection portion is formed between the L-shaped segment 144 and the first portion 132a of the main portion 132, and a fourth connection portion is formed between the L-shaped segment 144 and the second portion 132b of the main portion 132. The third connecting portion is disposed between the third portion 132c of the main portion 132 and the first connecting portion, and the fourth connecting portion is disposed between the third portion 132c of the main portion 132 and the second connecting portion. An L-shaped segment 144 is disposed, for example, between the sealing ring 130 (e.g., the main portion 132) and the bridging segment 142. The L-shaped segment 144 has an "L" shape. For example, in Figure 2BIn the L-shaped segment 144, there is a first portion 144a extending along direction D2, a second portion 144b extending along direction D3, and a third portion 144c between the first portion 144a and the second portion 144b. The third portion 144c is, for example, an inclined portion and has the smallest distance from the bridging segment 142.

[0030] In some embodiments, bridging segment 142 and L-shaped segment 144 are separate from each other. However, this disclosure is not limited thereto. Bridging segment 142 and L-shaped segment 144 may be interconnected by a third portion 144c. In some embodiments, both L-shaped segment 144 and bridging segment 142 are connected to sealing ring 130 (e.g., main portion 132). In alternative embodiments, at least one of L-shaped segment 144 and bridging segment 142 is not connected to sealing ring 130 (e.g., main portion 132). Corner sealing ring portions 140 may provide various mechanical benefits to sealing ring 130 (e.g., main portion 132), such as preventing layer peeling at die corners during the cutting process. In some embodiments, the main portion 132, bridging segment 142, and L-shaped segment 144 of sealing ring 130 are formed during the formation of interconnect structure 124. The main portion 132, bridging segment 142, and L-shaped segment 144 may include a stack of virtual wires and / or virtual vias. For example, the main portion 132, bridging segment 142, and L-shaped segment 144 of the sealing ring 130 are substantially at the same level as the interconnect structure 124. Specifically, the surfaces (e.g., the top surfaces) of the main portion 132, bridging segment 142, and L-shaped segment 144 of the sealing ring 130 are substantially coplanar with the top surface S1 of the top conductive feature 128a of the interconnect structure 124.

[0031] like Figure 2B As shown, the corner region 106 of the sealing ring is, for example, triangular or substantially triangular. The periphery of each corner region 106 of the sealing ring may be substantially a right triangle or an isosceles right triangle. The corner sealing ring portion 140 divides the corner region 106 of the sealing ring into a plurality of sub-regions 108, 110. For example, sub-region 108 is disposed between the sealing ring 130 (e.g., the main portion 132) and the L-shaped segment 144, and sub-region 110 is disposed between the L-shaped segment 144 and the bridging segment 142.

[0032] In some embodiments, a sealing ring 150 is configured in a sealing ring region 104 to surround a sealing ring 130. Therefore, the sealing ring 130 may also be referred to as an inner sealing ring (e.g., the innermost sealing ring). The sealing rings 130 and 150 are, for example, concentric with each other. Having multiple sealing rings 130, 150 ensures that at least the inner sealing ring is protected from breakage during cutting (e.g., die sawing). For example, the sealing ring 150 protects the sealing ring 130 from damage that may occur during cutting. In the illustrated embodiment, similar to the sealing ring 130, the sealing ring 150 includes a main portion 152, which is a rectangular or substantially rectangular ring, and the inner and outer contours of the main portion 152 respectively form substantially rectangular peripheries. The main portion 152 of the sealing ring 150 may also include a first portion 152a and a second portion 152b, and a third portion (e.g., an inclined portion) 152c between the first and second portions 152a and 152b. The first, second, and third portions 152a, 152b, and 152c of the sealing ring 150 may be substantially parallel to the first, second, and third portions 132a, 132b, and 132c of the sealing ring 130, respectively. The main portion 132 of the sealing ring 130 is disposed, for example, between the corner sealing ring portion 140 and the sealing ring 150. In some embodiments, the sealing ring 150 includes two segments 154 and a segment 156 disposed between the two segments 154. Segment 154 may also be referred to as a dummy metal segment, and segment 156 may also be referred to as an aluminum pad segment. In alternative embodiments, the sealing ring 150 includes segment 156 and one segment 154 disposed between the sealing ring 130 and segment 156, or the sealing ring 150 includes only segment 156. Segment 156 and dummy metal segment 154 each include first and second portions and a third portion (e.g., a sloped portion) between the first and second portions.

[0033] like Figure 1 As shown, the alignment mark AM is disposed on a first side (e.g., the front side) of the semiconductor substrate 120. Specifically, the alignment mark AM is disposed on and electrically insulated from the component layer, and is located within the corner sealing ring portion 140 and adjacent to the top conductive feature 128a of the interconnect structure 124. In some embodiments, the alignment mark AM is at a floating potential. In some embodiments, the alignment mark AM is formed during the formation of the top conductive feature 128a. For example, the alignment mark AM is substantially at the same height as the top conductive feature 128a. Specifically, as Figure 1 As shown, the surface (e.g., top surface) S of the alignment mark AM is substantially coplanar with the top surface S1 of the top conductive feature 128a of the interconnect structure 124 and the top surface S2 of the sealing ring 130. In some embodiments, the alignment mark AM comprises a metal, such as copper.

[0034] In some embodiments, such as Figure 2BAs shown, the alignment mark AM is disposed in at least one of the sub-regions 108, 110 of the corner region 106 of the sealing ring. For example, the alignment mark AM is disposed in sub-region 108. In some embodiments, the alignment mark AM is spaced apart from the sealing ring 130 (e.g., the corner sealing ring portion 140) by a distance d. In other words, from a top view, the alignment mark AM does not overlap with the corner sealing ring portion 140, for example. The distance d is greater than about 1.3 μm. From a top view, the alignment mark AM is circular (e.g., ...). Figure 2B As shown), cross-shaped (as shown) Figure 3A As shown), polygons (e.g., triangles (as shown) Figure 3B As shown), rectangle (as shown) Figure 3C As shown), pentagon (as shown) Figure 3D (as shown) and hexagons (such as) Figure 3E As shown), flower-shaped (as shown) Figure 3F (as shown) or similar shapes. The alignment mark AM includes circles (such as...) Figure 2B In embodiments shown (or substantially circular), the size of the alignment mark AM (e.g., diameter Dt1) is approximately 5 μm to approximately 100 μm. Figures 3A to 3F When the alignment mark AM is cross-shaped or polygonal, its dimensions (e.g., vertical length V1 and horizontal length H1) are approximately 5 μm to approximately 100 μm. If the dimensions of the alignment mark AM (e.g., diameter Dt1, vertical length V1, and horizontal length H1) are equal to or greater than 40 μm, alignment accuracy may be improved. Conversely, if the dimensions of the alignment mark AM (e.g., diameter Dt1, vertical length V1, and horizontal length H1) are less than 40 μm, alignment accuracy may be reduced.

[0035] The alignment mark AM may include a symmetrical shape with an axis of symmetry (e.g., the alignment mark AM is symmetrical with respect to the axis of symmetry) or an asymmetrical shape. Here, the axis of symmetry is an axis passing through the center of symmetry of the symmetrical shape. The axis of symmetry is, for example, substantially perpendicular to the surface of the alignment mark AM. In some embodiments, such as Figure 2B and Figure 2C As shown, the alignment mark AM comprises a circular or other symmetrical shape, and the alignment mark AM has an axis of symmetry SA1. The axis of symmetry SA1 passes through the center of symmetry SC1 of the alignment mark AM and is substantially perpendicular to the surface S1 of the alignment mark AM, and the alignment mark AM is symmetrical, for example, with respect to the axis of symmetry SA1. In some embodiments, such as Figure 2C As shown, the axis of symmetry SA1 extends substantially parallel to the stacking direction of the semiconductor substrate 120 and the interconnect structure 124 (e.g., direction D1 (e.g., the Z direction)), and the axis of symmetry SA1 is substantially perpendicular to the surface S1 of the alignment mark AM (e.g., extending along directions D2 and D3 (e.g., the XY plane)). Figure 1As shown, the surface S1 of the alignment mark AM is substantially coplanar with the surface S2 of the top conductive feature 128a of the interconnect structure 124. Figures 3A to 3F As shown, the alignment mark AM includes symmetrical shapes such as regular polygons and flower shapes, therefore the alignment mark AM has a symmetry axis SA1 passing through the center of symmetry SC1. In the illustrated... Figures 3A to 3F (as well as Figure 2B In the diagram, the direction of the axis of symmetry SA1 is the direction of entry and exit from the paper. The alignment mark AM includes, for example... Figures 3A to 3F In some embodiments of the symmetrical shape shown, the vertical length V1 and horizontal length H1 of the alignment mark AM are substantially the same. In alternative embodiments, the alignment mark AM has an asymmetrical shape such as an irregular polygon, and the vertical length V1 and horizontal length H1 of the alignment mark AM are different. In some embodiments, such as Figure 3F As shown, the alignment mark AM includes multiple portions P1, P2, P3 having the same symmetrical shape (such as a circle or a regular polygon), and from a top view, portions P1, P2, P3 partially overlap and partially do not overlap. For example, the partially overlapping portions P1, P2, P3 form the alignment mark AM and have an axis of symmetry SA1. In this embodiment, the alignment mark AM may have a groove (e.g., hollow or open) SL therein. Depending on the size of the groove SL and / or the filling capacity of the material, the groove SL may be unfilled, partially filled, or fully filled with appropriate material during and / or after the formation process of the alignment mark AM. For example, the groove SL is partially or fully filled by the dielectric layer 126 of the interconnect structure 124, and a dielectric pattern (not shown) is formed within the alignment mark AM. In some embodiments, such as Figure 2C As shown, the alignment mark AM may include at least two axes of symmetry SA3 and SA4 of the surface S1 parallel to the alignment mark AM. Similarly, Figures 3A to 3F Or similar shapes may include at least two axes of symmetry (not shown) parallel to the alignment mark AM on the surface S1.

[0036] In some embodiments, the alignment mark AM is a solid pattern. However, this disclosure is not limited thereto. The alignment mark AM may be annular, i.e., the alignment mark AM includes a groove (e.g., a hollow or open) SL. Viewed from a top view, as... Figures 4A to 4F As shown, the alignment mark AM includes a groove (e.g., hollow or open) SL. The groove SL is circular (e.g., ... Figure 4A As shown), polygons such as cross shapes (e.g.) Figure 4B As shown), polygons (e.g., triangles (as shown) Figure 4C As shown), rectangle (as shown) Figure 4D As shown), pentagon (as shown) Figure 4E (as shown) and hexagons (such as) Figure 4F (as shown) or similar shapes. The groove SL is circular (e.g.) Figure 4AIn embodiments shown (or substantially circular), the size of the groove SL (e.g., diameter Dt2) is smaller than the size of the alignment mark AM (e.g., diameter Dt1), and this size (e.g., diameter Dt2) is approximately 5 μm to approximately 100 μm. Figures 4B to 4F When the groove SL is cross-shaped or polygonal, the dimensions of the groove SL (e.g., vertical length V2 and horizontal length H2) are smaller than the dimensions of the alignment mark AM (e.g., vertical length V1 and horizontal length H1), and the dimensions of the groove SL (e.g., vertical length V2 and horizontal length H2) are approximately 5 μm to approximately 100 μm. In some embodiments, the groove SL includes a symmetrical shape with an axis of symmetry SA2 (e.g., the groove SL is symmetrical with respect to the axis of symmetry SA2) or an asymmetrical shape. Figures 4A to 4F As shown, the groove SL is circular or a regular polygon, therefore the groove SL has an axis of symmetry SA2 passing through the center of symmetry SC2. For example, the axis of symmetry SA2 overlaps with the axis of symmetry SA1, and the center of symmetry SC2 overlaps with the center of symmetry SC1. In some embodiments, such as Figures 4B to 4F As shown, the slot SL has a symmetrical shape such as a regular polygon, and the vertical length V2 and horizontal length H2 of the slot SL are the same. In an alternative embodiment, the slot SL has an asymmetrical shape such as an irregular polygon, and the vertical length V2 and horizontal length H2 of the slot SL are different. In some embodiments, the shape of the slot SL is the same as or similar to the shape (e.g., the outer contour) of the alignment mark AM. In an alternative embodiment, as... Figure 4G As shown, the shape of the slot SL differs from the shape (e.g., outer contour) of the alignment mark AM. For example, the alignment mark AM is circular, while the slot SL is rectangular. In these embodiments, the axis of symmetry SA2 of the slot SL may or may not overlap with the axis of symmetry SA1 of the alignment mark AM.

[0037] The groove SL may be unfilled, partially filled, or fully filled with appropriate material during and / or after the formation process of the alignment mark AM, depending on the size of the groove SL and / or the filling capacity of the material. For example, Figures 4A to 4G As shown, the trench SL is partially or completely filled by the dielectric layer 126 of the interconnect structure 124, and a dielectric pattern DP is formed within the alignment mark AM. The dielectric pattern DP has the same shape as the trench SL, and the alignment mark AM may surround the dielectric pattern DP.

[0038] In some embodiments, only one alignment mark AM is shown in the corner region 106 of the sealing ring. However, this disclosure is not limited thereto. Multiple alignment marks AM may be present in the corner region 106 of the sealing ring, and multiple alignment marks AM may be present in a sub-region 108, 110 of the corner region 106 of the sealing ring. In some embodiments, such as Figure 5AAs shown, alignment marks AMa and AMb are respectively disposed in sub-regions 108 and 110, and are separated from each other by sealing ring 130. For example, alignment mark AMa is disposed in sub-region 108, alignment mark AMb is disposed in sub-region 110, and alignment marks AMa and AMb are separated by an L-shaped segment 144 therebetween. In some embodiments, such as Figure 5B and Figure 5C As shown, multiple alignment marks AMa, AMb, and AMc are arranged in the corner region 106 of the sealing ring, and the alignment marks AMa, AMb, and AMc are separated from each other by the sealing ring 130 (e.g., L-shaped segment 144). Figure 5B and Figure 5C As shown, an alignment mark AMa is configured in subregion 108, and at least two alignment marks AMb and AMc are configured in subregion 110. In some embodiments, the alignment marks AMa, AMb, and AMc are arranged such that the distance between alignment marks AMa and AMb is substantially equal to the distance between alignment marks AMa and AMc. For example, the distance d1 between the centers of alignment marks AMa and AMb is substantially equal to the distance d2 between alignment marks AMa and AMc. Although Figure 5B and Figure 5C The alignment marks AMa, AMb, and AMc are depicted as having the same shape, but the alignment marks AMa, AMb, and AMc may have different shapes, sizes, arrangements, or similar features.

[0039] In some embodiments, a structure (not shown) is disposed at the outer corner of the sealing ring SR. For example, the structure is disposed at the outer corner of the outermost sealing ring 150 and is separate from the sealing ring 150. The structure may be configured as a third portion (e.g., a ramp portion) adjacent to the sealing ring 150.

[0040] In some embodiments, alignment marks are used to improve alignment accuracy (e.g., pick-up and placement accuracy). For example, alignment marks are detected using an imaging device mounted on an alignment apparatus prior to the bonding process between a die and carrier with alignment marks, or between a top die and a bottom die with alignment marks. Specifically, alignment marks can be used to improve alignment accuracy when two layers, two components, or two dies are bonded together. For example, the reference position (e.g., physical center) of the integrated circuit can be determined by the axis of symmetry of the alignment marks. Alignment accuracy can then be calculated based on the reference position (e.g., physical center) of the integrated circuit. Thus, overlap offset can be avoided and / or predicted. However, this disclosure is not limited thereto. Alignment accuracy can be determined by any other suitable method based on the alignment marks of integrated circuit 100, depending on the detection method and / or the algorithm used by the detection apparatus. In some embodiments, obtaining more axes of symmetry from the alignment marks can improve alignment accuracy. In some embodiments, alignment marks can be detected using an imaging device mounted on an exposure apparatus prior to the exposure process of a photoresist layer for defining a pattern. In these embodiments, alignment marks are also referred to as overlap marks.

[0041] Figures 6A to 6E This is a schematic cross-sectional view of various stages in a method for forming a semiconductor structure according to some embodiments. Figures 7A to 7E A simplified top view is provided for each stage of a method for forming a semiconductor structure according to some embodiments. For clarity, in Figures 7A to 7E Some components have been omitted.

[0042] Reference Figure 6A and Figure 7A The semiconductor structure is cut along the dicing line 105a of the dicing line region 105 to form multiple integrated circuits 100'. Figure 7A and Figure 2B Similar to, therefore its detailed description is omitted here. In some embodiments, the structure of integrated circuit 100' is similar to... Figure 1 The integrated circuit 100' has a similar structure, with the main difference being that the bonding structure 170 is not yet fully formed in the integrated circuit 100' (e.g., the bonding pad 176 is not yet formed). In some embodiments, the integrated circuit 100' includes a bonding via 174 in a semiconductor substrate 120 and a bonding dielectric layer 172 on the semiconductor substrate 120. For example, the top surface of the bonding via 174 is covered by the bonding dielectric layer 172. In some embodiments, the bonding via 174 is embedded in the semiconductor substrate 120, and then a thinning process is performed on the semiconductor substrate 120 to expose the bonding via 174. Then, the semiconductor substrate 120 is etched to form a groove, and some portions of the bonding via 174 (the top portion shown in the figure) are... Figure 6AThe via 174 protrudes beyond the semiconductor substrate 120. A bonding dielectric layer 172 is then formed to cover the bonding via 174, such that the bonding via 174 is embedded, for example, in the bonding dielectric layer 172. However, this disclosure is not limited thereto. In an alternative embodiment, the bonding dielectric layer 172 is not formed after the thinning process, so the bonding via 174 is exposed by protruding from or substantially coplanar with the semiconductor substrate 120. In an alternative embodiment, a planarization process is further performed on the bonding dielectric layer 172 until the bonding via 174 is exposed, so that the top surface of the bonding via 174 is substantially coplanar with the bonding dielectric layer 172.

[0043] In some embodiments, a monomerization process is performed on the semiconductor structure along dicing line 105a. The monomerization process may include plasma dicing, sawing, etching, similar methods, or combinations thereof. In some embodiments, alignment markers (AMs) may be used to improve accuracy during the monomerization process.

[0044] Reference Figure 6B and Figure 7BThe integrated circuit 100' is bonded to the carrier 300. For example, a carrier 300 is provided, and a release layer 310 is formed on the carrier 300. In some embodiments, the carrier 300 is a monolithic carrier wafer, which may be a glass carrier, ceramic carrier, organic carrier, or the like, for use in methods of manufacturing semiconductor wafers or reconstituted wafers for packaging structures. The release layer 310 may include a dielectric material (e.g., a buried oxide layer), a polymer-based material (e.g., a light-to-heat conversion (LTHC) material that can decompose under high-energy photothermal conditions), an epoxy-based heat-releasing material, or the like. In some embodiments, the release layer 310 is dispensed and cured in liquid form. In other embodiments, the release layer 310 is a thin film and laminated onto the carrier 300. The top surface of the release layer 310 may be flat and have a high degree of coplanarity. The release layer 310 may include a plurality of alignment marks 312a, 312b to improve alignment control. Alignment marks 312a and 312b are formed by creating openings in the release layer 310, for example, using a laser process or photolithography. In other embodiments, a dielectric layer is further formed on the release layer 310. The dielectric layer may include one or more layers of photo-patternable dielectric materials and / or non-photo-patternable dielectric materials. The photo-patternable dielectric material may be polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or the like, and may be formed using a spin-coating process or similar methods. Similar to photoresist materials, these photo-patternable dielectric materials can be easily patterned using photolithography. Non-photographically patternable dielectric materials can be silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like, and can be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating processes, similar methods, or combinations thereof.

[0045] Integrated circuit 100' can be bonded to carrier 300 via a pick-and-place process using a pick-and-place device. In some embodiments, carrier 300 includes a plurality of integrated circuit bonding regions 302 and dicing regions 305 located between the integrated circuit bonding regions 302. In some embodiments, alignment marks 312a, 312b are arranged in the dicing regions 305. For example, integrated circuit 100' is bonded to each of the integrated circuit bonding regions 302. The dicing regions 305 surround the integrated circuit bonding regions 302, and therefore surround the bonded integrated circuit 100'. In other words, alignment marks 312a, 312b are arranged along the periphery of integrated circuit 100'. In some embodiments, integrated circuit 100' and carrier 300 can be bonded by fusion bonding. For example, dielectric layer 126 of integrated circuit 100' and release layer 310 on carrier 300 are bonded by fusion bonding. If a dielectric layer is disposed between integrated circuit 100' and release layer 310, a fusion bonding can be formed between dielectric layer 126 of integrated circuit 100' and the dielectric layer. In other embodiments, the integrated circuit 100' is bonded to the carrier 300 via an adhesive layer, such as an LTHC material, UV adhesive, die-attach film, or the like.

[0046] In some embodiments, alignment marks 312a and 312b surround integrated circuit 100'. For example, alignment mark 312a is disposed at a corner of integrated circuit 100', and alignment mark 312b is disposed on a side of integrated circuit 100'. Alignment marks 312a and alignment marks 312b may have the same or different shapes. In some embodiments, the size of alignment mark 312a is smaller than the size of alignment mark 312b. However, this disclosure is not limited thereto. In some embodiments, a pick-and-place device uses alignment mark 312a to properly align integrated circuit 100' and carrier 300 during a pick-and-place process. Alignment mark 312a can be used for alignment accuracy (e.g., pick-and-place accuracy), and therefore alignment mark 312a is also referred to as a pick-and-place alignment mark. Alignment mark 312b can be detected by a stacking monitor to perform stacking measurements after bonding, and therefore alignment mark 312b is also referred to as a stacking alignment mark.

[0047] In some embodiments, the alignment mark AM of integrated circuit 100' is also used to improve alignment accuracy (e.g., pick-and-place accuracy). The pick-and-place device can use the alignment mark AM of integrated circuit 100' to properly align integrated circuit 100' and carrier 300 during the pick-and-place process. For example, alignment mark 312a is detected to determine a reference location of integrated circuit bonding region 302 (e.g., a pick-and-place center considered by the pick-and-place device), and alignment mark AM is detected to determine a reference location of integrated circuit 100' (e.g., a physical center). Alignment accuracy can then be calculated based on the difference between the determined reference location (e.g., pick-and-place center) of integrated circuit bonding region 302 and the determined reference location (e.g., physical center) of integrated circuit 100'. Therefore, overlay misalignment can be avoided, reduced, and / or predicted. However, this disclosure is not limited thereto. Alignment accuracy can be determined based on the alignment mark AM of integrated circuit 100' by any other suitable method, depending on the detection method and / or the algorithm used by the detection device. In some embodiments, undesirable misalignment of integrated circuit 100' can be reduced or avoided by using alignment mark AM and / or alignment mark 312a. In addition, it can reduce or avoid damage to integrated circuit 100' caused by misalignment.

[0048] Reference Figure 6C and Figure 7C Multiple bonding pads 176 are formed on bonding vias 174. In some embodiments, during the formation of bonding pads 176, alignment marks AM of integrated circuit 100' are used to align the formed bonding pads 176 with the bonding vias 174 of integrated circuit 100'. For example, multiple openings 171 are formed in bonding dielectric layer 172 by a patterning process including an exposure process, and then bonding pads 176 are formed in the openings 171 of bonding dielectric layer 172. An imaging device mounted on an exposure apparatus used during the exposure process can detect the alignment marks AM of integrated circuit 100'. The bonding pads 176 can then be formed in the pattern 171 by a deposition process or a similar process. However, this disclosure is not limited thereto. The bonding pads 176 can be formed by using the alignment marks AM of integrated circuit 100' with any suitable process.

[0049] In some embodiments, such as Figure 6CAs shown, the bonding pad 176 is aligned with the bonding via 174 beneath it, thus electrically connecting the bonding pad 176 to the bonding via 174. For example, the centerline of the bonding pad 176 is aligned with the centerline of the respective bonding via 174. In some embodiments, the alignment mark AM of the integrated circuit 100' is also referred to as a nesting mark. In some embodiments, by using the alignment mark AM during the bonding process of the integrated circuit 100' and the carrier 300 and / or during the formation of the bonding pad 176 of the integrated circuit 100', undesirable misalignment can be reduced or avoided. Furthermore, damage such as electrical connection failure due to misalignment between the bonding via 174 and the bonding pad 176 can be reduced or avoided. In some embodiments, the integrated circuit 100 is formed after the bonding pad 176 is formed.

[0050] Reference Figure 6D and Figure 7D Integrated circuit 200 is coupled to integrated circuit 100. Integrated circuit 200 may be a die, such as an application-specific integrated circuit (ASIC) chip, analog chip, sensor chip, wireless and radio frequency chip, voltage regulator chip, or memory chip. Integrated circuit 200 and integrated circuit 100 may be the same type of die or different types of dies. In some embodiments, integrated circuit 200 may be an active component or a passive component.

[0051] In some embodiments, integrated circuit 200 is similar to integrated circuit 100. Similarly, integrated circuit 200 includes a circuit region 202 and a sealing ring region 204 surrounding the circuit region 202. Integrated circuit 200 includes a semiconductor substrate 220, a component 222, an interconnect structure 224, a sealing ring structure SR' including sealing rings 230 and 250, an alignment mark AM', and a bonding structure 270. In some embodiments, the semiconductor substrate 220, component 222, interconnect structure 224, sealing ring structure SR including sealing rings 230 and 250, alignment mark AM', and bonding structure 270 are respectively similar to the semiconductor substrate 120, component 122, interconnect structure 124, sealing rings 130 and 150, alignment mark AM, and bonding structure 170 of integrated circuit 100, and therefore their detailed descriptions are omitted here.

[0052] In some embodiments, interconnect structure 224 includes at least one insulating layer 226 and a plurality of conductive features 228. In some embodiments, bonding structure 270 includes at least one bonding dielectric layer 272 and a plurality of bonding conductive features. The bonding conductive features are disposed in the bonding dielectric layer 272 and electrically connected to each other. In some embodiments, the bonding conductive features include bonding vias 274 electrically connected to interconnect structure 224 and bonding pads 276 electrically connected to bonding vias 274. Sealing rings 230, 250 may include a stack of dummy conductive features 231, such as dummy wires and / or dummy vias. In some embodiments, the shape of alignment mark AM' may be the same as or different from that of alignment mark AM. The shape and configuration of alignment mark AM' may be similar to or the same as that of alignment mark AM, and therefore its detailed description is omitted here. In some embodiments, the surface of alignment mark AM' (e.g., the bottom surface) is substantially coplanar with the surface of the top conductive feature 228a and the sealing ring 230 (e.g., the bottom surface). In some embodiments, integrated circuit 200 and integrated circuit 100 are bonded face-to-face via bonding structure 170 and bonding structure 270. In some embodiments, the integrated circuit 200 includes a plurality of conductive pads 280 in the dielectric layer 226. For example, an interconnect structure 224 is disposed between the semiconductor substrate 220 and the conductive pads 280, and the conductive pads 280 are disposed between the bonding structure 270 and the interconnect structure 224. The conductive pads 280 may be disposed near the top conductive feature 228a and the alignment mark AM'. The conductive pads 280 are, for example, aluminum pads.

[0053] In some embodiments, prior to bonding the integrated circuit 200 to the integrated circuit 100, bonding structures 170 and 270 are aligned through an alignment process, such that bonding pad 276 bonds to bonding pad 176 and bonding dielectric layer 272 bonds to bonding dielectric layer 172. In some embodiments, the alignment process is performed using alignment marks AM, AM'. After the alignment process is completed, bonding structures 170 and 270 are bonded using a hybrid bonding method including metal-to-metal bonding and dielectric-to-dielectric bonding.

[0054] In some embodiments, integrated circuit 200 is bonded to integrated circuit 100 using a pick and place process with a pick and place device. In some embodiments, alignment marks AM and AM' of integrated circuits 100 and 200 are used to improve the alignment accuracy (e.g., pick and place accuracy) of the alignment process. The alignment marks AM and AM' of integrated circuits 100 and 200 may be used by the pick and place device during the pick and place process to properly align integrated circuits 100 and 200. For example, prior to the bonding process between integrated circuits 100 and 200, the alignment mark AM of integrated circuit 100 (e.g., bottom die) is detected to determine the reference position of integrated circuit 100 (e.g., the pick and place center as perceived by the pick and place device), and the alignment mark AM' of integrated circuit 200 (e.g., top die) is detected to determine the reference position (e.g., physical center) of integrated circuit 200. Alignment accuracy can then be calculated based on the difference between a determined reference position (e.g., pick and place center) of integrated circuit 100 (e.g., bottom die) and a determined reference position (e.g., physical center) of integrated circuit 200 (e.g., top die). Therefore, overlay offset can be avoided, reduced, and / or predicted. However, this disclosure is not limited thereto. Alignment accuracy can be determined using any other suitable method based on alignment marks AM, AM' of integrated circuits 100 and 200, according to an algorithm used by the detection method and / or detection device. In some embodiments, by using alignment marks AM, AM', undesirable offset between integrated circuit 200 and integrated circuit 100 can be reduced or avoided. Furthermore, damage due to misalignment can be reduced or avoided.

[0055] In some embodiments, alignment marks 312a of the carrier 300 may also be used during the bonding process of integrated circuit 200 and integrated circuit 100. For example, similar to the bonding between integrated circuit 100' and carrier 300 described above, alignment marks 312a of carrier 300 are used to improve alignment accuracy (e.g., pick and place accuracy). For example, alignment marks 312a are detected to determine a reference position of integrated circuit bonding region 302 (e.g., a pick and place center as perceived by the pick and place device), and alignment mark AM' is detected to determine a reference position of integrated circuit 200 (e.g., a physical center). Alignment accuracy can then be calculated based on the difference between the determined reference position (e.g., pick and place center) of integrated circuit bonding region 302 and the determined reference position (e.g., physical center) of integrated circuit 200. Thus, overlay offset can be avoided, reduced, and / or predicted. However, this disclosure is not limited thereto. Alignment accuracy can be determined based on alignment mark AM' of integrated circuit 200 using any other suitable method, depending on the algorithm used by the detection method and / or detection device. In some embodiments, undesirable offsets of the integrated circuit 200 can be reduced or avoided by using alignment mark AM' and / or alignment mark 312a. Furthermore, damage to the integrated circuit 200 due to misalignment can be reduced or avoided.

[0056] Reference Figure 6E and Figure 7EAfter the integrated circuits 100 and 200 are bonded, a redistribution layer structure 290 is formed over the integrated circuits 100 and 200. The redistribution layer structure 290 includes at least one dielectric layer 292 and at least one conductive layer 294 alternately stacked. For example, the redistribution layer structure 290 is electrically connected to the interconnect structure 224 through silicon vias (not shown) in the semiconductor substrate 220 of the integrated circuit 200. In some embodiments, the dielectric layer 292 includes a photosensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), combinations thereof, or the like. In some embodiments, the conductive layer 294 includes copper, nickel, titanium, combinations thereof, or the like. A pad 296 is disposed over the redistribution layer structure 290. In some embodiments, the pad 296 is an under-bump metallization (UBM) pad for mounting conductive connectors 299, such as metal pillars, microbumps, or the like. Pad 296 comprises a metal or metal alloy. Pad 296 comprises aluminum, copper, nickel, or alloys thereof. Passivation layer 298 covers the edge portions of dielectric layer 292 and pad 296, and exposes the central portion of pad 296. In some embodiments, passivation layer 298 comprises silicon oxide, silicon nitride, benzocyclobutene (BCB) polymer, polyimide (PI), polybenzoxazole (PBO), or combinations thereof.

[0057] In some embodiments, the formed structure detaches from the carrier 300. For example, laser light can be projected onto the release layer 310, causing the release layer 310 to decompose and release the structure thereon. The formed structure is then flipped over and placed on another carrier or tape (not shown), and a cutting process is performed. In some embodiments, conductive pads 180 are exposed and then electrically connected to interconnect structures 410 via a plurality of conductive connectors 412 to form a package 400. Package 400 includes an integrated circuit 100 and an integrated circuit 200 bonded to the integrated circuit 100. The interconnect structure 410 may be a redistribution layer structure, another package, an interposer, a package substrate, a printed circuit board, or the like, while the conductive connectors 412 may be conductive pads, conductive pillars, balls, the like, or combinations thereof. The interconnect structure 410 may include conductive connectors 414. Conductive connectors 414 may include solder bumps and / or may include metal pillars (e.g., copper pillars), solder caps formed on the metal pillars, and / or the like.

[0058] In the illustrated embodiment, package 400 includes an integrated circuit 100 and an integrated circuit 200. However, this disclosure is not limited thereto. In alternative embodiments, package 400 may include multiple integrated circuits 100 and / or integrated circuits 200. For example, as Figure 8As shown, one integrated circuit 200 is bonded to two integrated circuits 100, and adjacent bonding pads 276 of integrated circuit 200 are bonded to bonding pads 176 of different integrated circuits 100. In some embodiments, an encapsulation 330 is formed to encapsulate integrated circuit 100, and an encapsulation 340 is formed to encapsulate integrated circuit 200. Through-holes 342 may be formed in the encapsulation 340 for electrical connection to the redistribution layer structure 290 and integrated circuit 100. In these embodiments, alignment marks AM, AM' are also used in the bonding process of integrated circuits 100 and 200 to improve alignment accuracy (e.g., pick-and-place accuracy).

[0059] In some embodiments, alignment accuracy (e.g., pick-and-place accuracy) between two components can be improved by using one or more alignment marks formed between the sealing rings in the corner regions of the sealing rings. For example, alignment accuracy for placing an integrated circuit onto a carrier or placing a top integrated circuit onto a bottom integrated circuit can be improved by using one or more alignment marks disposed near the L-shaped segment and the bridging segment. Therefore, damage to the integrated circuit due to misalignment can be reduced or avoided, and the yield and performance of the integrated circuit and the package containing it can be improved.

[0060] According to some embodiments of this disclosure, a semiconductor structure includes a circuit region, a sealing ring region, and at least one alignment mark. The sealing ring region surrounds the circuit region and includes a sealing ring corner region. A sealing ring is disposed in the sealing ring region and includes a corner sealing ring portion in the corner sealing ring region. The corner sealing ring portion divides the corner sealing ring region into a plurality of sub-regions, and at least one alignment mark is disposed in at least one sub-region of the corner sealing ring region.

[0061] In some embodiments, the at least one alignment mark is separated from the corner sealing ring portion.

[0062] In some embodiments, the at least one alignment mark includes a plurality of alignment marks, and the alignment marks are respectively configured in the sub-region.

[0063] In some embodiments, the at least one alignment mark includes a plurality of alignment marks, and at least two of the alignment marks are configured in the same sub-region of the sub-region.

[0064] In some embodiments, the sealing ring includes a main portion forming a substantially rectangular periphery, and the corner sealing ring portion includes: a bridging segment extending between a first edge and a second edge of the main portion; and an L-shaped segment disposed between the main portion and the bridging segment, extending between the first edge and the second edge of the main portion.

[0065] In some embodiments, the sub-region includes: a first sub-region located between the main portion and the L-shaped segment; and a second sub-region located between the L-shaped segment and the bridging segment.

[0066] In some embodiments, an additional sealing ring is further included, surrounding the sealing ring and forming an additional substantially rectangular periphery, wherein the main portion of the sealing ring is disposed between the corner sealing ring portion and the additional sealing ring.

[0067] In some embodiments, the shape of the at least one alignment mark includes a circle, a cross, a rectangle, a pentagon, a hexagon, a flower, or a combination thereof.

[0068] According to some embodiments of this disclosure, a semiconductor structure includes a circuit region, a sealing ring, and at least one alignment mark. The sealing ring surrounds the circuit region. The alignment mark is disposed at an inner corner of the sealing ring and is separated from the sealing ring, wherein the at least one alignment mark has an axis of symmetry substantially perpendicular to the surface of the at least one alignment mark.

[0069] In some embodiments, the shape of the at least one alignment mark includes a circle, a cross, a regular polygon with at least three sides, or a combination thereof.

[0070] In some embodiments, the sealing ring includes an L-shaped segment separate from the at least one alignment mark.

[0071] In some embodiments, the at least one alignment mark includes a plurality of alignment marks, and the alignment marks are separated from each other by the sealing ring.

[0072] In some embodiments, the at least one alignment mark includes a dielectric pattern therein.

[0073] In some embodiments, the at least one alignment mark includes a first alignment mark, a second alignment mark, and a third alignment mark, and the distance between the first alignment mark and the second alignment mark is substantially equal to the distance between the first alignment mark and the third alignment mark.

[0074] In some embodiments, the at least one alignment mark includes a plurality of alignment marks, and the alignment marks have the same shape.

[0075] According to some embodiments of this disclosure, a semiconductor structure includes a circuit region, a first sealing ring, and a plurality of alignment marks. The first sealing ring surrounds the circuit region. The plurality of alignment marks are disposed at the inner corners of the first sealing ring, wherein the alignment marks are separated from each other by the first sealing ring therebetween.

[0076] In some embodiments, the first sealing ring includes an L-shaped segment, and the alignment marks are separated from each other by the L-shaped segment therebetween.

[0077] In some embodiments, a second sealing ring is further included surrounding the first sealing ring.

[0078] In some embodiments, the circuit region includes a semiconductor substrate, an interconnect structure, and a bonding structure, and the alignment mark is disposed above the semiconductor substrate and the bonding structure, and adjacent to the interconnect structure.

[0079] The features of the above embodiments are beneficial for those skilled in the art to understand this utility model. Those skilled in the art should understand that this utility model can be used as a basis to design and modify other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of this utility model, and changes, substitutions, or modifications can be made without departing from the spirit and scope of this utility model.

Claims

1. A semiconductor structure, characterized in that... include: Circuit area; A sealing ring region surrounds the circuit region and includes a sealing ring corner region; A sealing ring, disposed in the sealing ring region, including a corner sealing ring portion located in the corner region of the sealing ring; as well as At least one alignment mark, wherein the corner sealing ring portion divides the corner region of the sealing ring into a plurality of sub-regions, and the at least one alignment mark is disposed in at least one sub-region of the corner region of the sealing ring.

2. The semiconductor structure according to claim 1, characterized in that... The at least one alignment mark is separated from the corner sealing ring portion.

3. The semiconductor structure according to claim 1, characterized in that... The at least one alignment mark includes a plurality of alignment marks, and the alignment marks are respectively disposed in the sub-region.

4. The semiconductor structure according to claim 1, characterized in that... The at least one alignment mark includes a plurality of alignment marks, and at least two of the alignment marks are configured in the same sub-region of the sub-region.

5. The semiconductor structure according to claim 1, characterized in that... The sealing ring includes a main portion forming a rectangular perimeter, and the corner sealing ring portion includes: A bridging segment extends between the first and second edges of the main portion; and An L-shaped segment is disposed between the main portion and the bridging segment, and extends between the first edge and the second edge of the main portion.

6. The semiconductor structure according to claim 1, characterized in that... The shape of the at least one alignment mark includes a circle, a cross, a rectangle, a pentagon, a hexagon, a flower, or a combination thereof.

7. A semiconductor structure, characterized in that... include: Circuit area; A sealing ring surrounds the circuit area; as well as At least one alignment mark is disposed at an inner corner of the sealing ring and separated from the sealing ring, wherein the at least one alignment mark has an axis of symmetry perpendicular to the surface of the at least one alignment mark.

8. The semiconductor structure according to claim 7, characterized in that... The surface of the at least one alignment mark is coplanar with the surface of the interconnect structure in the circuit region and the surface of the sealing ring.

9. A semiconductor structure, characterized in that... include: Circuit area; A first sealing ring surrounds the circuit area; as well as Multiple alignment marks are disposed at the inner corners of the first sealing ring, wherein the alignment marks are separated from each other by the first sealing ring therebetween.

10. The semiconductor structure according to claim 9, characterized in that... The first sealing ring includes an L-shaped segment, and the alignment marks are separated from each other by the L-shaped segment therebetween.

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