Build-up structure of fcbga glass substrate and package substrate
Patent Information
- Application Number
- CN202522046411.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-23
- Publication Date
- 2026-09-15
- Estimated Expiration
- 2035-09-23
AI Technical Summary
为此，本实用新型的目的在于提出一种FCBGA玻璃基板的增层结构及封装基板，解决传统结构中ABF增层表面起伏导致的真空吸附不良问题，提升RDL制作精度及产品良率
[0008]According to the present invention, an additive layer structure for an FCBGA glass substrate is provided. By filling the outermost circuit layer of the additive layer structure with an ABF layer, the ABF layer is made to be flush with the circuit height of the outermost circuit layer, that is, their outer surfaces are coplanar. This avoids problems such as vacuum adsorption failure, alignment difficulties, and dimensional deviations caused by surface undulations of the substrate, thereby improving the RDL fabrication accuracy and product yield. High-precision RDL fabrication can be performed to meet the requirements of high-density interconnection.
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Figure CN224760612U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of advanced packaging technology, and in particular to an add-on structure and packaging substrate for an FCBGA glass substrate. Background Technology
[0002] Glass-based FCBGA packaging substrates are widely used in high-density chip interconnect applications due to their low coefficient of thermal expansion, high flatness, and excellent electrical properties. In traditional processes, after the glass-based FCBGA board completes the ABF (Ajinomoto Build-up Film) layering, the RDL (Redistribution Layer) is directly fabricated for interconnection with the chip. However, the unevenness of the ABF layer pattern leads to surface irregularities on the substrate. During RDL fabrication, processes such as coating, photolithography, and PVD (Physical Vapor Deposition) require vacuum adsorption to fix the substrate. Surface irregularities can easily cause poor adsorption, leading to substrate displacement, impacts on the process chamber, damage to precision components, and even board rework or scrap, significantly increasing production costs. Therefore, there is an urgent need for a structure that can achieve surface planarization of glass-based FCBGAs to reduce process complexity and improve yield. Utility Model Content
[0003] This invention aims to at least partially solve one of the technical problems in the aforementioned technologies. Therefore, the purpose of this invention is to propose an upscaling structure and encapsulation substrate for FCBGA glass substrates, solving the problem of poor vacuum adsorption caused by surface undulations in ABF upscaling in traditional structures, thereby improving RDL fabrication accuracy and product yield.
[0004] To achieve the above objectives, this utility model proposes an add-on structure for an FCBGA glass substrate, comprising:
[0005] A glass core plate having opposing first and second surfaces, and at least one conductive through-hole connecting the first and second surfaces;
[0006] A first circuit layer is disposed on the first surface and the second surface and is electrically connected to the conductive via.
[0007] Two add-in structures are disposed on two first circuit layers in a one-to-one correspondence. Each add-in structure includes at least one first ABF layer formed on the first circuit layer, at least one second circuit layer disposed on the first ABF layer and electrically connected to the first circuit layer, and a second ABF layer filling the line spacing of the second circuit layer. The surface of the second ABF layer away from the first ABF layer is coplanar with the surface of the second circuit layer.
[0008] According to the present invention, an additive layer structure for an FCBGA glass substrate is provided. By filling the outermost circuit layer of the additive layer structure with an ABF layer, the ABF layer is made to be flush with the circuit height of the outermost circuit layer, that is, their outer surfaces are coplanar. This avoids problems such as vacuum adsorption failure, alignment difficulties, and dimensional deviations caused by surface undulations of the substrate, thereby improving the RDL fabrication accuracy and product yield. High-precision RDL fabrication can be performed to meet the requirements of high-density interconnection.
[0009] In addition, the above-mentioned layered structure of the FCBGA glass substrate proposed in this utility model may also have the following additional technical features:
[0010] Optionally, the second ABF layer is removed by laminating it onto the second circuit layer, ICP etching, and mechanical polishing to expose the second circuit layer, so that the surface of the second ABF layer away from the first ABF layer forms a coplanar shape with the surface of the second circuit layer.
[0011] Optionally, the layered structure includes at least two first ABF layers stacked on the first line layer, each first ABF layer having a second line layer, adjacent second line layers being electrically connected, the innermost second line layer being electrically connected to the first line layer, and the outermost second line layer being filled with a second ABF layer.
[0012] To achieve the above objectives, a second aspect of this utility model provides a packaging substrate, comprising:
[0013] The aforementioned build-up structure of the FCBGA glass substrate further includes:
[0014] A first wiring structure is disposed on the added layer structure of the first surface. The first wiring structure includes at least one first photosensitive dielectric layer and at least one third circuit layer. The first photosensitive dielectric layer is disposed on the coplanar plane of the second ABF layer and the second circuit layer. The third circuit layer is disposed on the first photosensitive dielectric layer and is electrically connected to the second circuit layer.
[0015] According to the packaging substrate of this utility model, by filling the outermost circuit layer with an ABF layer through the above-mentioned layer-addition structure, the ABF layer is flush with the circuit height of the outermost circuit layer, that is, their outer surfaces form a coplanar plane. This avoids problems such as inability to vacuum adsorption, alignment difficulties, and dimensional deviations caused by surface undulations of the substrate, thereby improving the RDL manufacturing accuracy and product yield. High-precision RDL manufacturing can be performed to meet the requirements of high-density interconnection.
[0016] In addition, the packaging substrate proposed above according to this utility model may also have the following additional technical features:
[0017] Optionally, the line width / spacing of the third line layer is less than or equal to the line width / spacing of the second line layer.
[0018] Optionally, it also includes:
[0019] A second wiring structure is disposed on the first wiring structure. The second wiring structure includes at least one second photosensitive dielectric layer and at least one fourth circuit layer. The second photosensitive dielectric layer is disposed on the third circuit layer. The fourth circuit layer is disposed on the second photosensitive dielectric layer and is electrically connected to the third circuit layer. The line width / line spacing of the fourth circuit layer is smaller than the line width / line spacing of the second circuit layer.
[0020] Furthermore, the line width / spacing of the fourth line layer is smaller than that of the third line layer.
[0021] Furthermore, it also includes at least two conductive posts, which are disposed on the second rewiring structure and electrically connected to the external pads of the fourth circuit layer.
[0022] Optionally, it also includes a solder mask layer and solder balls, wherein the solder mask layer is disposed on the augmentation structure of the second surface, and the solder balls are disposed on the solder mask layer and electrically connected to the second circuit layer. Attached Figure Description
[0023] Figure 1 This is a schematic diagram of the packaging substrate according to an embodiment of the present invention;
[0024] Figures 2-9 This is a cross-sectional schematic diagram of the substrate for each step of manufacturing the packaging substrate according to an embodiment of the present invention.
[0025] Label Explanation:
[0026] Glass core plate 100, first surface 100a, second surface 100b, TGV hole 110;
[0027] Conductive via 200;
[0028] First line layer 300;
[0029] Add-layer structure 400, first ABF layer 410, second line layer 420, second ABF layer 430;
[0030] First wiring structure 500, first photosensitive medium layer 510, third circuit layer 520;
[0031] Second wiring structure 600, second photosensitive medium layer 610, fourth circuit layer 620;
[0032] Conductive post 700;
[0033] Solder mask 810, solder ball 820. Detailed Implementation
[0034] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this utility model, and should not be construed as limiting this utility model.
[0035] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.
[0036] Example 1
[0037] Please refer to Figure 7 , Figure 7 This is a schematic diagram of the structure of an add-on structure for an FCBGA glass substrate according to an embodiment of the present invention. The add-on structure of the FCBGA glass substrate includes: a glass core plate 100 having a first surface 100a and a second surface 100b opposite to each other, and at least one conductive via 200 connecting the first surface 100a and the second surface 100b; a first circuit layer 300 disposed on the first surface 100a and the second surface 100b and electrically connected to the conductive via 200; and two add-on structures 400 disposed on the two first circuit layers 300 respectively. Each add-on structure 400 includes at least one first ABF layer 410 formed on the first circuit layer 300, at least one second circuit layer 420 disposed on the first ABF layer 410 and electrically connected to the first circuit layer 300, and a second ABF layer 430 filled in the line spacing of the second circuit layer 420. The surface of the second ABF layer 430 away from the first ABF layer 410 is coplanar with the surface of the second circuit layer 420.
[0038] In other words, in this embodiment, the line gaps (i.e. line spacing) of the outermost line (second line layer 420) of the layered structure 400 on both sides of the glass core board 100 are filled with an ABF layer, so that the outer surface of the layered structure 400 is free of undulations, thereby improving the manufacturing accuracy and yield of the RDL after the layered structure.
[0039] Therefore, according to the additive layer structure of the FCBGA glass substrate of this utility model, by filling the outermost circuit layer of the additive layer structure 400 with an ABF layer, the ABF layer is made to be flush with the circuit height of the outermost circuit layer, that is, their outer surfaces are coplanar. This avoids problems such as inability to vacuum adsorption, alignment difficulties, and dimensional deviations caused by surface undulations of the substrate, improves the RDL fabrication accuracy and product yield, and enables high-precision RDL fabrication to meet the requirements of high-density interconnection.
[0040] As an example, the second ABF layer 430 is removed by laminating it onto the second circuit layer 420, followed by ICP etching and mechanical polishing to expose the second ABF layer 430 on the second circuit layer 420, so that the surface of the second ABF layer 430 away from the first ABF layer 410 is coplanar with the surface of the second circuit layer 420. In other words, the second ABF layer 430 fills the line spacing of the second circuit layer 420. This can be achieved by first laminating a second ABF layer 430 onto the second circuit layer 420, and then processing the second ABF layer 430 by ICP etching and mechanical polishing to smooth it out so that its surface is flush with the line height of the second circuit layer 420.
[0041] As an example, the add-in structure 400 includes at least two first ABF layers 410 stacked on the first circuit layer 300. Each first ABF layer 410 has a second circuit layer 420. Adjacent second circuit layers 420 are electrically connected. The innermost second circuit layer 420 is electrically connected to the first circuit layer 300, and the outermost second circuit layer 420 is filled with a second ABF layer 430. It can be understood that the add-in structure 400 can be multiple first ABF layers 410 and multiple second circuit layers 420, and the number of layers can be designed according to actual needs, for example... Figure 7 In the process, the added-layer structure 400 includes multiple first ABF layers 410 and multiple second circuit layers 420. Each first ABF layer 410 is provided with a second circuit layer 420. Adjacent second circuit layers 420 are electrically connected through vias embedded in the first ABF layer 410 between them. The innermost second circuit layer 420 (that is, the second circuit layer 420 on the side closer to the glass core board 100) is electrically connected to the first circuit layer 300. The outermost second circuit layer 420 (that is, the second circuit layer 420 on the side of the added-layer structure 400 away from the glass core board 100) is filled with a second ABF layer 430.
[0042] Example 2
[0043] Please refer to Figure 1 , Figure 1This is a schematic diagram of the structure of a packaging substrate provided in an embodiment of the present invention. The packaging substrate includes an add-on structure of the FCBGA glass substrate of Embodiment 1, and also includes a first redistribution structure 500 disposed on the add-on structure 400 on the first surface 100a. The first redistribution structure 500 includes at least one first photosensitive dielectric layer 510 and at least one third circuit layer 520. The first photosensitive dielectric layer 510 is disposed on the coplanar plane of the second ABF layer 430 and the second circuit layer 420. The third circuit layer 520 is disposed on the first photosensitive dielectric layer 510 and is electrically connected to the second circuit layer 420.
[0044] In other words, the packaging substrate fills the outermost circuit layer with an ABF layer through the above-mentioned layer-addition structure 400, so that the ABF layer is flush with the circuit height of the outermost circuit layer, that is, their outer surfaces form a coplanar plane. Thus, in the process of manufacturing the first wiring structure 500, problems such as inability to vacuum adsorption, alignment difficulties, and dimensional deviations caused by surface undulations of the substrate can be avoided, thereby improving the manufacturing accuracy and product yield of RDL (first wiring structure 500) and enabling high-precision RDL manufacturing to meet the requirements of high-density interconnection.
[0045] As an example, the linewidth / spacing of the third line layer 520 is less than or equal to the linewidth / spacing of the second line layer 420, thus enabling high-density interconnect requirements. For instance, the linewidth / spacing of the third line layer 520 is 5 / 5 μm, and the linewidth / spacing of the second line layer 420 is 5 / 5 μm to 9 / 12 μm.
[0046] As an example, the first wiring structure 500 may include at least two first photosensitive dielectric layers 510 and at least two third circuit layers 520. That is, the first wiring structure 500 may be multiple layers of first photosensitive dielectric layers 510 and multiple layers of third circuit layers 520, and the number of layers can be designed according to actual needs. Each first photosensitive dielectric layer 510 is provided with a third circuit layer 520, wherein adjacent third circuit layers 520 are electrically connected through vias embedded in the first photosensitive dielectric layers 510 between them; the innermost third circuit layer 520 is electrically connected to the second circuit layer 420.
[0047] Furthermore, the packaging substrate also includes a second rewiring structure 600 disposed on the first rewiring structure 500. The second rewiring structure 600 includes at least one second photosensitive dielectric layer 610 and at least one fourth circuit layer 620. The second photosensitive dielectric layer 610 is disposed on the third circuit layer 520, and the fourth circuit layer 620 is disposed on the second photosensitive dielectric layer 610 and electrically connected to the third circuit layer 520. The linewidth / spacing of the fourth circuit layer 620 is smaller than that of the second circuit layer 520. In other words, by setting up the rewiring second rewiring structure 600 on the first rewiring structure 500, high-density interconnect requirements can be achieved. For example, the linewidth / spacing of the fourth circuit layer 620 is smaller than that of the third circuit layer 520. Specifically, the linewidth / spacing of the fourth circuit layer 620 is 2 / 2 μm.
[0048] It is understood that, in this embodiment, the line width / spacing of the fourth line layer 620 is less than the line width / spacing of the third line layer 520, which is less than the line width / spacing of the second line layer 420.
[0049] Similarly, the second wiring structure 600 may include at least two second photosensitive dielectric layers 610 and at least two fourth circuit layers 620. That is, the second wiring structure 600 may be multiple layers of second photosensitive dielectric layers 610 and multiple layers of fourth circuit layers 620, and the number of layers can be designed according to actual needs. Each second photosensitive dielectric layer 610 is provided with a fourth circuit layer 620, wherein adjacent fourth circuit layers 620 are electrically connected through vias embedded in the second photosensitive dielectric layers 610 between them; the innermost fourth circuit layer 620 is electrically connected to the third circuit layer 520.
[0050] As an example, the packaging substrate also includes at least two conductive pillars 700, which are disposed on the second rewiring structure 600 and electrically connected to the external pads of the fourth circuit layer 620. The conductive pillars 700 enable flip-chip bonding.
[0051] In addition, the packaging substrate also includes a solder mask layer 810 and solder balls 820. The solder mask layer 810 is disposed on the add-on structure 400 of the second surface 100b, and the solder balls 820 are disposed on the solder mask layer 810 and electrically connected to the second circuit layer 420. The solder balls 820 enable the connection between the packaging substrate and the circuit board.
[0052] The following is an example illustrating the fabrication process of the aforementioned packaging substrate:
[0053] First, refer to Figure 2 First, a glass core board 100 is fabricated. Specifically, a glass plate is prepared as the core board material, and the glass core board 100 has a first surface 100a and a second surface 100b. As an example, the thickness of the glass core board 100 is 0.4-1.2 mm.
[0054] Based on the aforementioned glass core board 100, such as Figure 3 As shown, the TGV hole 110 is fabricated using methods such as plasma etching, laser ablation, laser-induced etching, and focused discharge. The TGV hole 110 penetrates the glass core plate 100, and the diameter of the TGV hole 110 is greater than 40 μm.
[0055] Based on the glass core plate 100 that forms the TGV hole 110 as described above, such as Figure 4 As shown, the first circuit layer 300 can be fabricated using a subtractive method, and the TGV via 110 can be metallized to form a conductive via 200. For example, a seed copper layer can be deposited inside the TGV via and on the surface of the glass core board 100 using methods such as physical vapor deposition (PVDP) or chemical vapor deposition (PTH). The vias are then filled using methods such as electroplating or conductive metal adhesive. Subsequently, the seed copper layer and the over-plated copper layer are etched away using methods such as excimer laser etching or plasma etching to form the conductive via 200 on the glass core board 100. Then, the first circuit layer 300, electrically connected to the conductive via 200, is formed on the glass core board 100 using methods such as pattern transfer (dry film application → exposure → development → etching → film removal).
[0056] Next, refer to Figure 5 Based on the glass core board 100 that forms the first circuit layer 300, a first ABF layer 410 is laminated on both sides of the glass core board 100, and the addition layer is fabricated using a semi-additive process. The process includes ABF film lamination → laser drilling → Desmear + PTH → dry film lamination → exposure → development → VCP → film removal → flash etching to fabricate the second circuit layer 420 (and the addition layer) on the top and bottom surfaces of the glass core board 100, thus forming the addition layer structure 400 on the top and bottom surfaces of the glass core board 100.
[0057] Subsequently, as Figure 6As shown, a second ABF layer 430 is laminated on the outermost second circuit layer 420 of the layer-addition structure 400. The ABF layer is then etched using ICP until the second circuit layer 420 is exposed. The main etching gases are CF4, SF6, CHF3, O2, and Ar, with a gas ratio of fluorine-based gas:O2 = 4:1-10:1. The Ar flow rate can account for 20%-50% of the total flow rate, and the total gas flow rate is controlled at 10-100 sccm. The ICP power is 500-2500W, the bias power is 10-200W, and the pressure is 10-30 mTorr. Subsequently, CMP is used to smooth the surface, making the second ABF layer 430 and the second circuit layer 4200 have the same height. During grinding, the pressure should be 1-5 psi, the disc speed 30-100 rpm, and the slurry flow rate 100-300 mL / min. Dilute with DI water at a ratio of 1:1-1:3 before use. During grinding, end-point detection should be performed using an optical or friction sensor to avoid over-polishing or erosion. In this way, a product can be obtained as follows: Figure 7 As shown, the surface of the second ABF layer 430 and the surface of the second circuit layer 420 form a coplanar additive structure 400.
[0058] Then, refer to Figure 8 After grinding, the first rewiring structure 500 and the second rewiring structure 600 are fabricated on the top layer structure 400. The rewiring structure can be fabricated by sequentially coating a photosensitive medium layer, pattern transfer, metallization, electroplating, flash etching and etching Ti processes to complete the fabrication of the third circuit layer 520 and the fourth circuit layer 620.
[0059] Subsequently, as Figure 9 As shown, conductive pillars 700, i.e., copper pillar bumps, are fabricated on the second rewiring structure 600, and a solder mask layer 810 and BGA solder balls 820 are fabricated on the bottom layer layer structure 400. The fabrication of the conductive pillars 700, solder mask layer 810 and BGA solder balls 820 can be carried out using existing technology, and will not be described in detail here.
[0060] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.
[0061] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.
[0062] In this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.
[0063] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0064] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0065] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.
Claims
1. A layering structure for an FCBGA glass substrate, characterized in that, include: A glass core plate having opposing first and second surfaces, and at least one conductive through-hole connecting the first and second surfaces; A first circuit layer is disposed on the first surface and the second surface and is electrically connected to the conductive via. Two add-in structures are disposed on two first circuit layers in a one-to-one correspondence. Each add-in structure includes at least one first ABF layer formed on the first circuit layer, at least one second circuit layer disposed on the first ABF layer and electrically connected to the first circuit layer, and a second ABF layer filling the line spacing of the second circuit layer. The surface of the second ABF layer away from the first ABF layer is coplanar with the surface of the second circuit layer.
2. The add-layer structure of the FCBGA glass substrate as described in claim 1, characterized in that, The second ABF layer is removed by laminating it onto the second circuit layer, ICP etching, and mechanical polishing to expose the second circuit layer, so that the surface of the second ABF layer away from the first ABF layer is coplanar with the surface of the second circuit layer.
3. The add-layer structure of the FCBGA glass substrate as described in claim 1, characterized in that, The layered structure includes at least two first ABF layers stacked on the first line layer, each first ABF layer having a second line layer, adjacent second line layers being electrically connected, the innermost second line layer being electrically connected to the first line layer, and the outermost second line layer being filled with a second ABF layer.
4. A packaging substrate, characterized in that, The build-up structure of the FCBGA glass substrate according to any one of claims 1-3 further includes: A first wiring structure is disposed on the added layer structure of the first surface. The first wiring structure includes at least one first photosensitive dielectric layer and at least one third circuit layer. The first photosensitive dielectric layer is disposed on the coplanar plane of the second ABF layer and the second circuit layer. The third circuit layer is disposed on the first photosensitive dielectric layer and is electrically connected to the second circuit layer.
5. The packaging substrate as described in claim 4, characterized in that, The line width / spacing of the third line layer is less than or equal to the line width / spacing of the second line layer.
6. The packaging substrate as described in claim 4, characterized in that, Also includes: A second wiring structure is disposed on the first wiring structure. The second wiring structure includes at least one second photosensitive dielectric layer and at least one fourth circuit layer. The second photosensitive dielectric layer is disposed on the third circuit layer. The fourth circuit layer is disposed on the second photosensitive dielectric layer and is electrically connected to the third circuit layer. The line width / line spacing of the fourth circuit layer is smaller than the line width / line spacing of the second circuit layer.
7. The packaging substrate as described in claim 6, characterized in that, The line width / spacing of the fourth line layer is less than that of the third line layer.
8. The packaging substrate as described in claim 6, characterized in that, It also includes at least two conductive posts, which are disposed on the second rewiring structure and electrically connected to the external pads of the fourth circuit layer.
9. The packaging substrate as described in claim 4, characterized in that, It also includes a solder mask layer and solder balls, wherein the solder mask layer is disposed on the augmentation structure of the second surface, and the solder balls are disposed on the solder mask layer and electrically connected to the second circuit layer.