Semiconductor structure, semiconductor device and electronic device

Abstract

The present disclosure relates to a semiconductor structure, a semiconductor device and an electronic device, the semiconductor structure comprising a chip assembly and an interposer; the chip assembly comprising at least one chip, the chip and the interposer being connected by a hybrid bonding structure. A first bonding layer is formed on the chip of the chip assembly; a second bonding layer is formed on the interposer, the first bonding layer and the second bonding layer being hybrid bonded to connect the chip and the interposer by the hybrid bonding structure, the semiconductor structure being capable of providing higher IO density and having better thermal performance.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, semiconductor device, and electronic device. Background Technology

[0002] Packaging technology is a very important part of the semiconductor field. In 2.5D packaging technology, multiple chips are connected to the circuit board through an interposer. The chips and the interposer are electrically connected through microbumps, and material is filled between the chips and the interposer to protect the microbumps. Utility Model Content

[0003] The purpose of this disclosure is to provide a semiconductor structure, semiconductor device, and electronic device that can provide higher I / O density and better thermal performance.

[0004] To achieve the above objectives, according to a first aspect of this disclosure, a semiconductor structure is provided, including a chip assembly and an interposer; the chip assembly includes at least one chip, and the chip and the interposer are connected by a hybrid bonding structure.

[0005] Optionally, the chip assembly includes a system chip; The system chip is connected to the intermediate connection board via a hybrid bonding structure.

[0006] Optionally, the chip assembly further includes a memory chip and an interface chip; The memory chip and the interface chip are respectively connected to the intermediate connection board through a hybrid bonding structure.

[0007] Optionally, the memory chips are located on opposite sides of the system chip in a first direction; The interface chip is located on opposite sides of the system chip in a second direction perpendicular to the first direction.

[0008] Optionally, the semiconductor structure further includes a filler chip connected to the interfacing board and located at the junction of the memory chip and the interface chip.

[0009] Optionally, the semiconductor structure further includes a packaging material layer for encapsulating the chip assembly and the interposer.

[0010] Optionally, the hybrid bonding structure includes a first bonding layer disposed on the chip and a second bonding layer disposed on the interposer, wherein the first bonding layer and the second bonding layer are bonded together.

[0011] Optionally, both the first bonding layer and the second bonding layer include a dielectric material portion and a metal portion.

[0012] According to a second aspect of this disclosure, a semiconductor device is provided, comprising the semiconductor structure described above.

[0013] According to a third aspect of this disclosure, an electronic device is also provided, comprising the semiconductor structure described above or comprising the semiconductor device described above.

[0014] Through the above technical solution, in the semiconductor structure disclosed herein, at least one chip is connected to the interposer via a hybrid bonding structure, thereby providing a higher I / O density between the chip and the interposer. At the same time, there is no need to add filler material, resulting in better thermal performance of the semiconductor structure.

[0015] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a top view of a semiconductor structure in related technologies; Figure 2 Based on Figure 1 AA section view in the middle; Figure 3 Based on Figure 1 BB section view in the middle; Figure 4 This is a top view of a semiconductor structure provided in some embodiments of this disclosure; Figure 5 Based on Figure 4 CC section view in the middle; Figure 6 Based on Figure 4 DD section view in the middle; Figure 7 This is a flowchart of a method for fabricating a semiconductor structure provided in some embodiments of this disclosure; Figure 8 This is a schematic diagram of the formation of a first bonding layer between a system chip and a memory chip in some embodiments of this disclosure; Figure 9 This is a schematic diagram of the formation of a first bonding layer on the system chip and the interface chip in some embodiments of this disclosure; Figure 10 This is a schematic diagram of a second bonding layer formed in an intermediate bonding plate in some embodiments of this disclosure.

[0017] Explanation of reference numerals in the attached figures 110 - System chip; 120 - Memory chip; 130 - Interface chip; 140 - Filler chip; 200-Intermediate Connector Plate; 310 - Microbump; 320 - Filler material; 330 - Hybrid bonding structure; 331 - First bonding layer; 3311 - First dielectric material portion; 3312 - First metal portion; 332 - Second bonding layer; 3321 - Second dielectric material portion; 3322 - Second metal portion; 400 - Encapsulation material layer. Detailed Implementation

[0018] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0019] In this disclosure, unless otherwise stated, directional terms such as "upper," "lower," "left," and "right" generally refer to upper, lower, left, and right relative to the figures; "inner" and "outer" refer to the inner and outer contours of the corresponding components; and "far" and "near" refer to the corresponding structure or component being away from or near another structure or component. In the figures of this disclosure, X indicates a first direction, i.e., the signal transmission direction of the signal line; Y indicates a second direction; and Z indicates the thickness direction of the intermediate connecting plate. Furthermore, the terms "first," "second," etc., used in this disclosure are for distinguishing one element from another and do not have sequential or importance implications. In addition, in the following description, when referring to the figures, unless otherwise explained, the same reference numerals in different figures denote the same or similar elements. The above definitions are for explanation and illustration only and should not be construed as limiting this disclosure.

[0020] like Figures 1 to 3 As shown, in the current CoWoS (Chip-on-Wafer-on-Substrate) package, the top chips, such as SOC (System on Chip, 110), HBM (High Bandwidth Memory, i.e., memory chip 120) and IO Die (interface chip 130), are connected to the top of the interposer 200 via microbumps 310. With the development of technology and the demand for smaller semiconductor sizes, the IO (Input / Output) density is limited, and the filling material 320 between the chip and the interposer 200 is not conducive to heat dissipation.

[0021] The purpose of this disclosure is to provide a semiconductor structure, semiconductor device, and electronic device that can provide higher IO (input / output) density and better thermal performance.

[0022] To achieve the above objectives, such as Figures 4 to 10 As shown, according to a first aspect of this disclosure, a semiconductor structure is provided, including a chip assembly and an interposer 200; the chip assembly includes at least one chip, and the chip and the interposer 200 are connected via a hybrid bonding structure 330.

[0023] Through the above technical solution, in the semiconductor structure disclosed herein, at least one chip is connected to the interposer 200 via a hybrid bonding structure 330, thereby providing a higher I / O density, i.e., a higher input / output density, between the chip and the interposer 200; at the same time, there is no need to provide filler material 320, resulting in better thermal performance of the semiconductor structure.

[0024] It should be noted that the hybrid bonding structure 330 is a packaging technology that combines the characteristics of inter-chip bonding and intra-chip bonding. It replaces traditional bump or solder ball interconnects with direct metal-to-metal (e.g., copper-to-copper) connections, enabling ultra-fine pitch stacking and packaging in a very small space.

[0025] Hybrid bonding enables high-density interconnects, allowing more connection points to be placed in a smaller area, significantly increasing the data communication bandwidth between chips. Furthermore, the direct copper-to-copper connection in hybrid bonding results in lower resistance, reducing energy loss during signal transmission and minimizing signal propagation time delay. Hybrid bonding offers better heat dissipation; its compact structure and direct conductive paths contribute to improved thermal management and reduced heat generation. Hybrid bonding also enables chips to be vertically stacked, significantly reducing the size of the final product and improving overall system performance.

[0026] It should be noted that the chip assembly of this disclosure, including at least one chip, can be understood as including one or more chips. In other words, the semiconductor structure can be a 2.5D package, with the one or more chips arranged side by side and connected to the interposer 200 using a hybrid bonding structure 330. That is, the 2.5D package structure uses a hybrid bonding structure 330 to achieve electrical connection between the chip and the interposer 200. Compared with the connection method using microbumps 310 in related technologies, this disclosure can provide higher input / output density, and since the filler material 320 is eliminated, it is more conducive to heat dissipation of the chip and the interposer 200.

[0027] like Figure 8 , Figure 9 and Figure 10As shown, in some embodiments, the hybrid bonding structure 330 includes a first bonding layer 331 disposed on the chip and a second bonding layer 332 disposed on the interposer 200, wherein the first bonding layer 331 and the second bonding layer 332 are bonded together.

[0028] The first bonding layer 331 is disposed on the surface of the chip, and its main function is to realize the electrical interconnection between the chip and the external interposer 200. The second bonding layer 332 is disposed on the surface of the interposer 200 and corresponds to the first bonding layer 331 to realize the bonding connection between the chip and the interposer 200.

[0029] It should be noted that the surfaces of the first bonding layer 331 and the second bonding layer 332 need to be finely processed to ensure good contact and bonding effect with the second bonding layer 332.

[0030] The thicknesses of the first bonding layer 331 and the second bonding layer 332 can be determined according to specific applications and design requirements. In some embodiments, the thicknesses of the first bonding layer 331 and the second bonding layer 332 can be between 1 micrometer and 10 micrometers. The second bonding layer 332 matches the first bonding layer 331 to achieve uniform bonding pressure distribution and good contact effect. Furthermore, the layout and size design of the first bonding layer 331 and the second bonding layer 332 must consider the wiring requirements of the chip and the interposer 200 and the chip alignment accuracy to ensure smooth bonding process and reliability of the final product.

[0031] To achieve hybrid bonding, in some embodiments, both the first bonding layer 331 and the second bonding layer 332 include a dielectric material portion and a metal portion. Specifically, the first bonding layer 331 may include a first dielectric material portion 3311 and a first metal portion 3312. The first metal portion 3312 may be copper, aluminum, or other suitable conductive materials for transmitting electrical signals; the first dielectric material portion 3311 serves as insulation and protection, preventing signal interference and short circuits. For example, the first dielectric material portion 3311 may be made of a non-conductive material such as silicon dioxide.

[0032] Similarly, the second bonding layer 332 may also include a second dielectric material portion 3321 and a second metal portion 3322, corresponding respectively to the first dielectric material portion 3311 and the first metal portion 3312 on the chip. The second metal portion 3322 may be copper, aluminum, or other suitable conductive material for transmitting electrical signals; the second dielectric material portion 3321 serves as insulation and protection, preventing signal interference and short circuits. For example, the second dielectric material portion 3321 may be made of a non-conductive material such as silicon dioxide.

[0033] The bonding connection between the first bonding layer 331 and the second bonding layer 332 is the core component of the hybrid bonding structure 330, and its quality and performance directly affect the reliability and electrical performance of the entire chip package. Bonding connections are typically achieved through processes such as thermocompression bonding, ultrasonic bonding, or direct metal bonding. In thermocompression bonding, appropriate temperature and pressure are applied to induce atomic diffusion between the metal layers, forming a strong bond. Ultrasonic bonding utilizes ultrasonic energy to activate the metal surface, promoting bonding between metals. Direct metal bonding, under specific conditions, allows the metal layers to directly form chemical or metallic bonds.

[0034] The embodiments of this disclosure combine hybrid bonding structure 330 technology with 2.5D packaging technology. The chip is connected to the intermediate connection board 200 through the hybrid bonding structure 330. Other functional chips or circuits, such as memory and power management circuits, can also be integrated on the intermediate connection board 200 to achieve high system integration and miniaturization.

[0035] First, it achieves high-density interconnection between the chip and the interposer board 200, providing more electrical connection points within a limited space to meet the data transmission bandwidth and connection quantity requirements of high-performance chips. Second, the hybrid bonding structure 330 has low resistance and inductance, reducing energy loss and time delay during signal transmission and improving the overall system performance. Furthermore, the hybrid bonding structure 330 also has good heat dissipation performance, effectively managing the heat generated by the chip during operation and ensuring chip stability and reliability.

[0036] The chip assembly may include one or more chips. In some embodiments, the chip assembly may include a system chip 110, which is connected to an interposer 200 via a hybrid bonding structure 330. A first bonding layer 331 is provided on one side of the system chip 110, and a second bonding layer 332 corresponding to the first bonding layer 331 is provided on the interposer 200. The hybrid bonding structure 330 between the system chip 110 and the interposer 200 provides high-density interconnection, thereby improving data transmission rate and overall system performance.

[0037] like Figure 4 , Figure 5 and Figure 6 As shown, in some embodiments, the chip assembly includes a system chip 110, a memory chip 120, and an interface chip 130. The system chip 110, the memory chip 120, and the interface chip 130 are connected to the intermediate connection board 200 via a hybrid bonding structure 330.

[0038] The chip assembly includes a system chip 110, a memory chip 120, and an interface chip 130. The system chip 110 is primarily responsible for handling core computing tasks, the memory chip 120 is used for data storage, and the interface chip 130 is used for communication and data exchange with other external devices or systems. The system chip 110, memory chip 120, and interface chip 130 are connected to the intermediate connection board 200 via a hybrid bonding structure 330.

[0039] The system chip 110 is connected to the intermediary connection board 200 through a hybrid bonding structure 330. The system chip 110 is provided with a first bonding layer 331, and the intermediary connection board 200 is provided with a second bonding layer 332 corresponding to the first bonding layer 331. The hybrid bonding structure 330 between the system chip 110 and the intermediary connection board 200 can provide high-density interconnection, thereby improving the data transmission rate and the overall system performance.

[0040] The memory chip 120 is also connected to the intermediate interconnect 200 via a hybrid bonding structure 330, similar to that of the system chip 110. This connection includes a first bonding layer 331 on the memory chip 120 and a second bonding layer 332 on the intermediate interconnect 200 corresponding to the first bonding layer 331, enabling high-density electrical interconnection between the memory chip 120 and the intermediate interconnect 200. This connection method ensures rapid data exchange between the memory chip 120 and the system chip 110, improving the system's storage and retrieval efficiency.

[0041] The interface chip 130 is also connected to the intermediate connection board 200 via a hybrid bonding structure 330. This hybrid bonding structure 330 also encapsulates the first bonding layer 331 of the interface chip 130 and the second bonding layer 332 of the intermediate connection board 200, corresponding to the first bonding layer 331 of the interface chip 130, to achieve a reliable electrical connection between the interface chip 130 and the intermediate connection board 200. Through this high-density interconnection method, the interface chip 130 can perform efficient data communication with other external devices or systems, thereby expanding the functionality and application range of the chip assembly.

[0042] Through the hybrid bonding structure 330 described above, the system chip 110, the memory chip 120, and the interface chip 130 can be tightly integrated together to form a high-performance chip assembly, meeting the needs of modern electronic devices for high integration, high data transmission rate, and multifunctionality.

[0043] like Figure 4As shown, in some embodiments, the memory chip 120 is located on opposite sides of the system chip 110 in a first direction; the interface chip 130 is located on opposite sides of the system chip 110 in a second direction perpendicular to the first direction. Multiple memory chips 120 may be present, each located on opposite sides of the system chip 110 in the first direction, and all connected to the bottom intermediate connection plate 200 via a hybrid bonding structure 330. Similarly, multiple interface chips 130 may be present, each located on opposite sides of the system chip 110 in the second direction, and also connected to the bottom intermediate connection plate 200 via a hybrid bonding structure 330. The first direction is perpendicular to the second direction.

[0044] In some embodiments, the semiconductor structure further includes a filler chip 140, which is connected to the interposer 200 and located at the junction of the memory chip 120 and the interface chip 130. By placing the filler chip 140 at the junction of the memory chip 120 and the interface chip 130, the overall structure, heat dissipation, or package size requirements can be balanced. The filler chip 140 can be a non-functional silicon block or a simple chip.

[0045] like Figure 4 As shown, there are four memory chips 120 (e.g., HBM). In the first direction, two memory chips 120 are located on one side of the system chip 110 and arranged along the side length of the system chip 110, roughly equivalent to the side length of the system chip 110. The other two memory chips 120 are located on the other side of the system chip 110, also arranged along the side length of the system chip 110, roughly equivalent to the side length of the system chip 110. That is, the memory chips 120 on opposite sides of the system chip 110 are arranged symmetrically. There are two interface chips 130 (IO Dies). In the second direction, one interface chip 130 is located on one side of the system chip 110, and the other interface chip 130 is located on the opposite side of the system chip 110. The lengths of the two interface chips 130 are roughly equivalent to the side length of the system chip 110 on the corresponding side. Both the memory chips 120 and the interface chips 130 are connected to the bottom intermediate connection board 200 through a hybrid bonding structure 330. Dummy chips 140 can be placed at the four corners of the system chip 110 to improve overall stability and prevent warping caused by uneven stress.

[0046] like Figure 6 As shown, optionally, the semiconductor structure also includes a packaging material layer 400, which is used to package the chip assembly and the interposer 200. In the semiconductor structure, the packaging material layer 400 is an indispensable and important component, tightly wrapping the chip assembly and the interposer 200 to form a complete protective shell.

[0047] In some embodiments, the encapsulation material layer 400 can encapsulate the system chip 110, the memory chip 120, and the interface chip 130 on the upper surface of the interposer board, forming an encapsulation structure. The encapsulation material layer 400 is typically composed of multiple layers of materials, including but not limited to molding compounds, ceramics, and metals. Through its dense structure and excellent insulation properties, the encapsulation material layer 400 can block the intrusion of moisture and gas, preventing the chip from getting damp and causing short circuits or corrosion. Simultaneously, the hardness and strength of the encapsulation material layer 400 are sufficient to withstand physical impacts and mechanical vibrations, reducing the risk of chip damage due to external forces during use. Furthermore, the encapsulation material layer 400 can also shield against external electromagnetic interference, ensuring stable and reliable electrical signal transmission within the chip, thereby improving the performance and reliability of the entire semiconductor structure.

[0048] like Figure 7 As shown, this disclosure also provides a method for fabricating a semiconductor structure, the method comprising steps S100 to S300.

[0049] In step S100, a first bonding layer 331 is formed on the chip of the chip assembly.

[0050] In step S200, a second bonding layer 332 is formed on the intermediate connection plate 200.

[0051] In step S300, the first bonding layer 331 of the chip and the second bonding layer 332 of the intermediate connection board 200 are mixed and bonded together.

[0052] A first bonding layer 331 is formed on the chip, and a second bonding layer 332 is formed on the interposer 200. A hybrid bonding structure 330 is formed by connecting the first bonding layer 331 and the second bonding layer 332 to connect the chip of the chip assembly to the interposer 200. Compared with the microbump 310 connection method in related technologies, the hybrid bonding connection enables high-density interconnection between the chip and the interposer 200, allowing for more connection points to be arranged within a limited chip area. This improves the chip's integration and functional complexity, providing strong support for the design and manufacturing of high-performance chips and meeting the requirements of modern electronic devices for chip performance and miniaturization. It also enhances the mechanical stability between the chip and the interposer 200. Simultaneously, the hybrid bonding connection helps improve the chip's heat dissipation performance. Because the bonding layer material has good thermal conductivity, it can effectively conduct the heat generated by the chip to the interposer 200 and external heat dissipation structures, reducing the chip's operating temperature, improving its stability and lifespan, and ensuring its reliability under high-power operating conditions.

[0053] like Figure 8 and Figure 9As shown, a first bonding layer 331 is formed on the chip of the chip assembly. Specific operations may include: firstly, cleaning and pre-treating the chip surface to remove impurities and oxides to ensure good adhesion of the bonding layer. Then, using processes such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), a first dielectric material portion 3311 and a first metal portion 3312 (such as copper, gold, etc.) are deposited to form a first bonding layer 331 of uniform thickness. The thickness of this bonding layer should be controlled within the micrometer range to ensure the strength and electrical performance of subsequent bonding.

[0054] like Figure 10 As shown, a second bonding layer 332 is also formed on the interposer 200. Specifically, the process may include first cleaning and pre-treating the surface of the interposer 200. Then, using a deposition process similar to that on a chip, a second dielectric material portion 3321 and a second metal portion 3322 are deposited to form the second bonding layer 332. The thickness of this bonding layer should also be controlled within the micrometer range, and its material and thickness should match those of the first bonding layer 331 to ensure good bonding compatibility.

[0055] The metal part is used to realize signal connection, and its material can be copper, gold, etc.; the dielectric material part is used for isolation and insulation, and its material can be SiO2, etc.

[0056] After the first bonding layer 331 and the second bonding layer 332 are both prepared, the first bonding layer 331 of the chip and the second bonding layer 332 of the intermediate connection plate 200 are mixed-bonded together. This connection process is usually carried out under high temperature and high pressure. Through techniques such as thermosetting bonding, the atoms in the first bonding layer 331 and the second bonding layer 332 diffuse and fuse with each other to form a strong chemical bond. After the mixed-bonding connection, a highly reliable physical and electrical connection is achieved between the chip and the intermediate connection plate 200. From the perspective of physical connection, the two are tightly combined to form a stable integral structure with good mechanical strength, which can effectively resist various external impacts that may be subjected to during chip use, ensuring the structural stability of the chip assembly. From the perspective of electrical connection, the mixed-bonding connection greatly reduces the contact resistance between the chip and the intermediate connection plate 200, realizes near-lossless electrical signal transmission, significantly improves the data transmission speed and processing efficiency of the chip assembly, and enables the entire chip system to operate in a high-performance and high-stability state.

[0057] In some embodiments, the chip includes a system chip 110, a memory chip 120, and an interface chip 130. The step of forming a first bonding layer 331 on the chip includes forming the first bonding layer 331 on the system chip 110, the memory chip 120, and the interface chip 130, respectively. Specifically, the first bonding layer 331 is formed on the system chip 110, the memory chip 120, and the interface chip 130. The specific structures of the first bonding layers 331 on the three chips can be the same or different, depending on their actual electrical connection requirements.

[0058] The step of connecting the first bonding layer 331 of the chip and the second bonding layer 332 of the interposer 200 by hybrid bonding includes: connecting the first bonding layer 331 of the system chip 110 to the second bonding layer 332 of the interposer 200; connecting the first bonding layer 331 of the memory chip 120 to the second bonding layer 332 of the interposer 200; and connecting the first bonding layer 331 of the interface chip 130 to the second bonding layer 332 of the interposer 200.

[0059] Corresponding to the first bonding layer 331 of the system chip 110, memory chip 120, and interface chip 130, a second bonding layer 332 corresponding to the first bonding layer 331 of the system chip 110, the first bonding layer 331 of the memory chip 120, and the first bonding layer 331 of the interface chip 130 needs to be formed on the interposer 200. The second bonding layer 332 includes three bonding regions, respectively corresponding to the first bonding layer 331 of the system chip 110, the first bonding layer 331 of the memory chip 120, and the first bonding layer 331 of the interface chip 130. It can form a hybrid bonding structure 330 between the chip and the interposer 200 through a hybrid bonding process to connect the chip and the interposer 200.

[0060] In some embodiments, the method further includes encapsulating the system chip 110, the memory chip 120, and the interface chip 130 with the intermediate connection board 200 using an encapsulation material, thereby encapsulating the system chip 110, the memory chip 120, and the interface chip 130 in the intermediate connection board 200 through an encapsulation material layer 400.

[0061] By encapsulating the aforementioned chip and intermediate interconnect board 200 with encapsulation materials, the chip assembly can be provided with excellent physical protection, effectively preventing external environmental factors such as dust, moisture, and mechanical shock from corroding and damaging the chip inside the encapsulation structure, thereby significantly improving the reliability and stability of the chipset. The encapsulated chipset can better adapt to various complex application scenarios, extend its service life, and provide strong support for the stable operation of electronic devices.

[0062] According to a second aspect of this disclosure, a semiconductor device is provided, comprising the semiconductor structure described above. Therefore, this semiconductor device also possesses all the advantages of the semiconductor structure. The semiconductor device further includes a packaging substrate, wherein an intermediate connection plate 200 is electrically connected to the packaging substrate on the side opposite to the chip assembly to enable signal or power transmission.

[0063] According to a third aspect of this disclosure, an electronic device is also provided, comprising the semiconductor structure described above or comprising the semiconductor device described above. Therefore, the electronic device also has all the advantages of the semiconductor structure and semiconductor device described above, which will not be repeated here.

[0064] This electronic device includes, but is not limited to, mobile phones, smartwatches, tablets, laptops, microcontrollers, servers, etc.

[0065] Semiconductor structures, semiconductor devices, and electronic devices, wherein the semiconductor structure includes a chip assembly having one or more chips, the one or more chips being connected to an interposer 200 via a hybrid bonding structure 330, thereby providing higher I / O density between the chips and the interposer 200, while eliminating the need for additional filler material 320, resulting in better thermal performance of the semiconductor structure.

[0066] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0067] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0068] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A semiconductor structure, characterized in that, It includes a chip assembly and an interfacing board; the chip assembly includes at least one chip, and the chip and the interfacing board are connected by a hybrid bonding structure.

2. The semiconductor structure according to claim 1, characterized in that, The chip assembly includes a system chip; The system chip is connected to the intermediate connection board via a hybrid bonding structure.

3. The semiconductor structure according to claim 2, characterized in that, The chip assembly also includes a memory chip and an interface chip; The memory chip and the interface chip are respectively connected to the intermediate connection board through a hybrid bonding structure.

4. The semiconductor structure according to claim 3, characterized in that, The memory chips are located on opposite sides of the system chip in a first direction; The interface chip is located on opposite sides of the system chip in a second direction perpendicular to the first direction.

5. The semiconductor structure according to claim 3 or 4, characterized in that, The semiconductor structure also includes a filler chip, which is connected to the interfacing board and located at the junction of the memory chip and the interface chip.

6. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes a packaging material layer for encapsulating the chip assembly and the interposer.

7. The semiconductor structure according to claim 1, characterized in that, The hybrid bonding structure includes a first bonding layer disposed on the chip and a second bonding layer disposed on the interposer, wherein the first bonding layer and the second bonding layer are bonded together.

8. The semiconductor structure according to claim 7, characterized in that, Both the first bonding layer and the second bonding layer include a dielectric material portion and a metal portion.

9. A semiconductor device, characterized in that, Includes the semiconductor structure described in any one of claims 1-8.

10. An electronic device, characterized in that, It includes the semiconductor structure described in any one of claims 1-8 or the semiconductor device described in claim 9.

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