Semiconductor device

Abstract

The utility model provides a kind of semiconductor device, including first conductive pad, first dielectric layer, wire structure, second dielectric layer and second conductive pad.First dielectric layer is on first conductive pad.Wire structure is on first dielectric layer and penetrates first dielectric layer and is electrically connected to first conductive pad.Second dielectric layer is on wire structure and first dielectric layer, and second dielectric layer has opening.Second conductive pad is in the opening of second dielectric layer on wire structure, wherein the sidewall of second conductive pad contacts the sidewall of the opening of second dielectric layer, and the top surface of second conductive pad is lower than the top surface of second dielectric layer.The conductive pad formed by the utility model has higher structural stability to improve wire bonding quality.

Description

Technical Field

[0001] Some embodiments of this utility model relate to semiconductor devices. Background Technology

[0002] In semiconductor manufacturing, redistribution layers (RDLs) are used to add additional metal layers to the surface of a wafer or die to redistribute and optimize circuit interconnect layout. However, modern redistribution layer process steps still need to be streamlined to further reduce process costs. Utility Model Content

[0003] Some embodiments of this utility model provide a semiconductor device comprising a first conductive pad, a first dielectric layer, a conductive wire structure, a second dielectric layer, and a second conductive pad. The first dielectric layer is on the first conductive pad. The conductive wire structure is on the first dielectric layer, penetrates the first dielectric layer, and is electrically connected to the first conductive pad. The second dielectric layer is on the conductive wire structure and the first dielectric layer, and the second dielectric layer has an opening. The second conductive pad is on the conductive wire structure and in the opening of the second dielectric layer, wherein the sidewall of the second conductive pad contacts the sidewall of the opening of the second dielectric layer, and the top surface of the second conductive pad is lower than the top surface of the second dielectric layer.

[0004] In some implementations, the width of the opening in the second dielectric layer decreases as it moves further away from the conductor structure.

[0005] In some implementations, the width of the opening in the second dielectric layer increases with distance from the conductor structure.

[0006] In some implementations, the width of the opening in the second dielectric layer is substantially the same from bottom to top.

[0007] In some implementations, the top surface of the second conductive pad does not contact the sidewall of the opening in the second dielectric layer.

[0008] In some implementations, a portion of the second conductive pad is directly above the first conductive pad.

[0009] In some embodiments, the semiconductor device further includes wire bonding electrically connected to a second conductive pad.

[0010] In some implementations, the width of the second conductive pad decreases as it moves further away from the wire structure.

[0011] In some implementations, the width of the second conductive pad increases with distance from the wire structure.

[0012] In some implementations, the width of the second conductive pad is substantially the same from bottom to top. Attached Figure Description

[0013] Figures 1 to 8A cross-sectional view of a semiconductor manufacturing apparatus according to some embodiments of the present invention is shown.

[0014] Figure 9 A cross-sectional view of a semiconductor device according to other embodiments of the present invention is shown.

[0015] Figure 10 A cross-sectional view of a semiconductor device according to other embodiments of the present invention is shown. Detailed Implementation

[0016] Figures 1 to 8 A semiconductor manufacturing apparatus 90A illustrating some embodiments of the present invention (shown on) Figure 8 A cross-sectional view of ( ). Reference Figure 1 A conductive pad 110, a passivation layer 120, and a sealing ring 130 may be formed on a substrate 100. The passivation layer 120 is formed on the conductive pad 110 and the sealing ring 130, exposing a first portion 110A of the conductive pad 110. The sealing ring 130 surrounds the semiconductor device. In some embodiments, the substrate 100 may be a carrier such as a wafer or interposer in which an integrated circuit is formed, and the conductive pad 110, the passivation layer 120, and the sealing ring 130 are formed in the fanout region of the wafer. In some embodiments, the conductive pad 110 may be made of a conductive material, such as a metal (e.g., aluminum). The passivation layer 120 may be made of a dielectric material. The sealing ring 130 may be made of a metal.

[0017] Next, a dielectric layer 140 is formed on the substrate 100, the conductive pad 110, and the passivation layer 120. The dielectric layer 140 covers the passivation layer 120 and the conductive pad 110, and exposes a second portion 110B of the first portion 110A of the conductive pad 110 and a portion of the passivation layer 120. In some embodiments, the dielectric layer 140 may be an organic layer, such as polyimide (PI) or polybenzoxazole (PBO).

[0018] refer to Figure 2A seed layer 150 is formed on the passivation layer 120 and the dielectric layer 140, and a seed layer 160 is formed on the seed layer 150. The seed layer 150 contacts the second portion 110B of the conductive pad 110. The seed layers 150 and 160 are formed of a conductor, such as a metal. In some embodiments, the seed layers 150 and 160 are formed of different materials. For example, the seed layer 150 may be formed of a material that has good adhesion to the dielectric layer 140, such as titanium-tungsten (TiW) or titanium (Ti). The seed layer 160 may be formed of a material more suitable for forming a wire, such as copper (Cu). In some embodiments, the thickness of the seed layer 150 is, for example, between 50 nanometers and 300 nanometers. The thickness of the seed layer 160 is, for example, between 100 nanometers and 600 nanometers.

[0019] refer to Figure 3 A patterned photoresist layer PR is formed on the seed layer 160, the patterned photoresist layer PR including an opening O1. The opening O1 is located at least directly above the second portion 110B of the conductive pad 110 and exposes the seed layer 160.

[0020] refer to Figure 4 A conductive layer 170 is formed on the seed layer 160 and in the opening O1. Specifically, electroplating can be used to form the conductive layer 170 in the opening O1. The formation location of the conductive layer 170 is limited by a patterned photoresist layer PR. The conductive layer 170 is electrically connected to the underlying conductive pad 110 through the seed layers 150 and 160. The conductive layer 170 can be made of a conductor, such as a metal. In some embodiments, the conductive layer 170 and the seed layer 160 are made of the same material, for example, both the conductive layer 170 and the seed layer 160 are made of copper or gold, and the conductive layer 170 and the seed layer 150 are made of different materials.

[0021] Next, refer to Figure 5 The patterned photoresist layer PR is removed. After removing the patterned photoresist layer PR, the conductive layer 170 remains on the seed layer 160. In some embodiments, the conductive layer 170 may serve as a redistribution layer (RDL). However, this invention is not limited thereto.

[0022] refer to Figure 6 Using the conductive layer 170 as a mask, seed layers 160 and 150 are etched. Specifically, a first wet etching process can be performed first to remove the seed layer 160 exposed by the conductive layer 170. In some embodiments, the conductive layer 170 and the seed layer 160 are made of the same material, so the first wet etching process for removing the seed layer 160 has substantially the same etching rate for both the conductive layer 170 and the seed layer 160, resulting in a simultaneous reduction in the thickness of both the conductive layer 170 and the seed layer 160.

[0023] Next, using the conductive layer 170 and the seed layer 160 as a mask, the seed layer 150 is etched. Specifically, a second wet etching process can be performed to remove the seed layer 150 exposed by the seed layer 160.

[0024] In some embodiments, after etching the seed layer 150, plasma treatment may be performed to remove metal residues on the dielectric layer 140. These metal residues may be byproducts of the etching of the seed layer 150, seed layer 160, and conductive layer 170 as described above. Removing these metal residues reduces the probability of leakage current in the conductive layer 170. In this invention, the seed layer 150, seed layer 160, and conductive layer 170 may be collectively referred to as "conductive structure 180." The conductive structure 180 is electrically connected to the conductive pad 110 on and through the dielectric layer 140.

[0025] refer to Figure 7 A dielectric layer 190 is formed on the conductor structure 180, the dielectric layer 140, and the passivation layer 120. The dielectric layer 190 has an opening O2 to expose a portion of the conductor structure 180. Due to the formation of the opening O2, the dielectric layer 190 has multiple sidewalls S1. Specifically, the opening O2 has a first portion O21 that is directly above both the conductive pad 110 and the passivation layer 120, and a second portion O22 that is only directly above the passivation layer 120. It should be noted that although... Figure 7 The first portion O21 and the second portion O22 of the opening O2 are shown separated from each other, but in some embodiments, the first portion O21 and the second portion O22 of the opening O2 are interconnected in the top view (not shown). In some embodiments, the width of the opening O2 of the dielectric layer 190 increases with distance from the conductor structure 180. In some embodiments, the dielectric layer 190 may be an organic layer, such as polyimide (PI) or polybenzoxazole (PBO). In some embodiments, the material of the dielectric layer 190 may be the same as or different from the material of the dielectric layer 140.

[0026] refer to Figure 8A conductive pad 200 is formed in the opening O2 of the dielectric layer 190 on the conductive structure 180. The sidewall S2 of the conductive pad 200 contacts the sidewall S1 of the dielectric layer 190 corresponding to the opening O2, and the top surface T2 of the conductive pad 200 is lower than the top surface T1 of the dielectric layer 190. In some embodiments, the conductive pad 200 is formed by chemical plating. In some embodiments, the conductive pad 200 is made of metal, such as a nickel-gold or nickel-silver alloy. In this invention, the position of the conductive pad 200 is directly defined by the opening O2 of the dielectric layer 190, and the dielectric layer 190 can be directly used to separate the conductive pad 200. That is, no additional photoresist layer is needed to define the position of the conductive pad 200, and the dielectric layer 190 does not need to be removed in subsequent processes. This can be used to reduce the number of process steps in a semiconductor device to reduce costs. After the conductive pad 200 is formed, wire bonding 210 can be provided on the conductive pad 200 to electrically connect the conductive pad 200 to other components. In some embodiments, the bonding wire 210 may be made of metal, such as copper, silver, or gold. In some embodiments, the bonding wire 210 is disposed only on the conductive pad 200 in the second portion O22 of the opening O2 of the dielectric layer 190, i.e., the bonding wire 210 and the conductive pad 110 do not overlap in the top view. In some embodiments, the conductive pad 200 in the first portion O21 of the opening O2 of the dielectric layer 190 may be used as a test metal pad for a test circuit.

[0027] Since the conductive pad 200 of this invention is formed after the dielectric layer 190 is formed, the top surface of the conductive pad 200 does not contact the sidewall of the opening O2 of the dielectric layer 190, and the shape of the conductive pad 200 inherits the shape of the opening O2 of the dielectric layer 190. For example, as Figure 8 As shown, the width of the conductive pad 200 increases with distance from the wire structure 180. Figure 8 In the embodiment, the surrounding portion of the conductive pad 200 (e.g. Figure 8 The region R shown can be supported by the dielectric layer 190, thus improving the structural stability of the conductive pad 200 and thereby improving the wire bonding quality.

[0028] Figure 9 A cross-sectional view of a semiconductor device 90B according to another embodiment of the present invention is shown. Figure 9 Semiconductor device 90B and Figure 8 Similar to semiconductor device 90A, the difference lies in that the width of the opening O2 of the dielectric layer 190 in semiconductor device 90B is substantially consistent from bottom to top. Since the shape of conductive pad 200 inherits the shape of the opening O2 of dielectric layer 190, the width of conductive pad 200 is also substantially consistent from bottom to top.

[0029] Figure 10 A cross-sectional view of a semiconductor device 90C according to other embodiments of the present invention is shown. Figure 10 Semiconductor device 90C and Figure 8 Similar to semiconductor device 90A, the difference lies in that the width of the opening O2 in the dielectric layer 190 of semiconductor device 90C decreases with increasing distance from the conductive structure 180. Since the shape of the conductive pad 200 inherits the shape of the opening O2 in the dielectric layer 190, the width of the conductive pad 200 also decreases with increasing distance from the conductive structure 180. Figure 10 In this embodiment, the bottom of the conductive pad 200 is wider, so the conductive pad 200 itself can provide sufficient stability, thereby improving the wire bonding quality.

[0030] In summary, the embodiments of this invention can be used to improve the process of redistribution structures. Specifically, the conductive pads for connecting wires in this invention can be directly defined by a dielectric layer that will not be subsequently removed. Therefore, process steps for redistribution structures can be saved, reducing process costs. The resulting conductive pads can also have higher structural stability, thus improving wire bonding quality.

[0031] The above description is only a partial embodiment of the present utility model, not all of the embodiments. Any equivalent changes to the technical solution of the present utility model made by those skilled in the art through reading the specification of the present utility model shall be covered by the claims of the present utility model.

[0032] [Symbol Explanation]

[0033] 90A, 90B, 90C: Semiconductor devices

[0034] 100: Substrate

[0035] 110, 200: Conductive pads

[0036] 110A, O21: Part 1

[0037] 110B, O22: Part Two

[0038] 120: Passivation layer

[0039] 130: Sealing ring

[0040] 140, 190: Dielectric layer

[0041] 150, 160: Seed layer

[0042] 170: Conductor Layer

[0043] 180: Conductor Structure

[0044] 210: Stringing

[0045] O1, O2: Openings

[0046] PR: Patterned photoresist layer

[0047] S1, S2: Sidewalls

[0048] R: Region

[0049] T1, T2: Top surface.

Claims

1. A semiconductor device, characterized in that, Include: First conductive pad; A first dielectric layer is on the first conductive pad; A wire structure is present on and extends through the first dielectric layer and is electrically connected to the first conductive pad; The second dielectric layer has an opening on the conductor structure and the first dielectric layer; A second conductive pad is in the opening of the second dielectric layer in the conductor structure, wherein the sidewall of the second conductive pad contacts the sidewall of the opening of the second dielectric layer, and the top surface of the second conductive pad is lower than the top surface of the second dielectric layer.

2. The semiconductor device according to claim 1, characterized in that, The width of the opening in the second dielectric layer decreases as it moves further away from the conductor structure.

3. The semiconductor device according to claim 1, characterized in that, The width of the opening in the second dielectric layer increases with distance from the conductor structure.

4. The semiconductor device according to claim 1, characterized in that, The width of the opening in the second dielectric layer is substantially the same from bottom to top.

5. The semiconductor device according to claim 1, characterized in that, The top surface of the second conductive pad does not contact the sidewall of the opening in the second dielectric layer.

6. The semiconductor device according to claim 1, characterized in that, A portion of the second conductive pad is directly above the first conductive pad.

7. The semiconductor device according to claim 1, characterized in that, Also includes: The wire is electrically connected to the second conductive pad.

8. The semiconductor device according to claim 1, characterized in that, The width of the second conductive pad decreases as it moves further away from the wire structure.

9. The semiconductor device according to claim 1, characterized in that, The width of the second conductive pad increases with distance from the conductor structure.

10. The semiconductor device according to claim 1, characterized in that, The width of the second conductive pad is substantially the same from bottom to top.

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