Fiber Channel (FC) package substrate

Abstract

The utility model discloses a FC packaging substrate, including outer layer circuit layer, outer layer circuit layer is equipped with outer layer circuit pattern, and still has the solder mask area that divides on outer layer circuit layer, is equipped with the electrophoresis insulating layer with window on the outer layer circuit pattern, and is plated and is equipped with the metal surface treatment layer on the area that exposes in the window outside on the outer layer circuit pattern, and still is equipped with the solder mask layer on outer layer circuit layer, and the solder mask layer and electrophoresis insulating layer cooperate and completely cover the solder mask area on outer layer circuit layer. This FC packaging substrate has simple structure, reasonable, high stability, product yield is high, is easy to processing and manufacturing, and processing efficiency is high, processing cost is low and so on advantage, very good satisfied the demand of FC packaging technology.

Description

Technical Field

[0001] This utility model relates to the field of packaging substrate technology, and in particular to an FC packaging substrate. Background Technology

[0002] Flip-chip technology, also known as FC packaging, is an advanced semiconductor packaging technology. It involves forming bumps at the chip's connection points, flipping the chip over, and then directly connecting the bumps to the packaging substrate. Compared to traditional packaging technologies, FC packaging offers advantages such as smaller size, better electrical performance, superior heat dissipation, stronger shock resistance, and lower cost, making it widely used in modern electronic products.

[0003] In FC packaging technology, the conventional manufacturing process of the packaging substrate is as follows: blanking → drilling → copper plating → electroplating → circuit fabrication → solder mask → surface treatment → molding → packaging; or blanking → drilling → copper plating → electroplating → inner layer circuit fabrication → lamination → drilling → copper plating → electroplating → outer layer circuit fabrication → solder mask → surface treatment → molding → packaging.

[0004] However, packaging substrates manufactured using the aforementioned conventional processes are prone to the following shortcomings: To meet the technical requirement that the height difference between the pads in the outer circuit pattern and the solder resist layer be <5μm, the uniformity of the solder resist layer and the surface treatment layer thickness is extremely important during the packaging substrate manufacturing process. Simultaneously, the solder resist layer thickness must be <15μm and the surface treatment layer thickness must reach 6–13μm. However, when the solder resist layer thickness is <15μm, it is very easy to cause false copper exposure (i.e., solder resist layer cracking), resulting in short circuits and a high product defect rate.

[0005] In view of the above, this utility model is hereby proposed. Summary of the Invention

[0006] To overcome the above-mentioned defects, this utility model provides an FC packaging substrate, which has the advantages of simple and reasonable structure, high stability, high product yield, easy processing and manufacturing, high processing efficiency and low processing cost, and well meets the needs of FC packaging technology.

[0007] The technical solution adopted by this utility model to solve its technical problem is: an FC packaging substrate, including an outer circuit layer, the outer circuit layer having an outer circuit pattern, and the outer circuit layer also having a solder resist area; an electrophoretic insulating layer with a window is covered on the outer circuit pattern, and a metal surface treatment layer is plated on the area of ​​the outer circuit pattern exposed outside the window; and a solder resist layer is also provided on the outer circuit layer, the solder resist layer and the electrophoretic insulating layer cooperating to completely cover the solder resist area on the outer circuit layer.

[0008] As a further improvement of this utility model, the outer circuit pattern is provided with an outer circuit body and an FC pad, and the electrophoretic insulating layer is covered on both the outer circuit body and the FC pad.

[0009] As a further improvement of this utility model, the thickness of the electrophoretic insulating layer is 10-12 μm.

[0010] As a further improvement of this utility model, the FC packaging substrate further includes an insulating intermediate layer, wherein at least one inner circuit layer is stacked on each of the opposite sides of the insulating intermediate layer, and an outer circuit layer is disposed on each of the two outermost inner circuit layers. In addition, the electrophoretic insulating layer is provided on at least one of the two outer circuit layers.

[0011] As a further improvement of this utility model, the FC packaging substrate further includes an insulating intermediate layer, and the outer circuit layer is respectively stacked on both opposite sides of the insulating intermediate layer. In addition, the electrophoretic insulating layer is provided on at least one of the two outer circuit layers.

[0012] As a further improvement of this utility model, the metal surface treatment layer is any one of nickel-gold layer, nickel-palladium-gold layer, nickel-silver layer, nickel-palladium-silver layer and tin layer, and the thickness of the metal surface treatment layer is the same as the thickness of the electrophoretic insulating layer.

[0013] As a further improvement of this utility model, the solder resist layer is a solder resist ink layer, and the thickness of the solder resist layer is 10-30μm.

[0014] The beneficial effects of this utility model are as follows: Compared with the prior art, this utility model innovates the structure of the FC packaging substrate by setting an electrophoretic insulating layer with stronger adhesion to the outer circuit pattern, and then using a solder resist layer to fill and cover the solder resist areas not covered by the electrophoretic insulating layer. On the one hand, the strong adhesion between the electrophoretic insulating layer and the outer circuit pattern can effectively avoid the cracking of the solder resist ink layer caused by abnormal thickness in the prior art, thereby significantly improving product quality. On the other hand, the strong adhesion between the electrophoretic insulating layer and the outer circuit pattern also effectively reduces the processing difficulty, such as allowing for more flexible control over the thickness of the electrophoretic insulating layer and the solder resist layer, and more flexible control over the line width and spacing of the outer circuit pattern. This effectively improves the processing convenience and efficiency of the FC packaging substrate, reduces processing costs, and facilitates production implementation. Attached Figure Description

[0015] Figure 1This is a cross-sectional view of the FC packaging substrate described in Embodiment 1 of this utility model; Figure 2 for Figure 1 A partial structural schematic diagram of the FC packaging substrate shown; Figure 3 This is a cross-sectional structural diagram of the FC packaging substrate described in Embodiment 2 of this utility model.

[0016] Referring to the accompanying drawings, the following explanations are provided: 1. Outer layer circuit pattern; 10. Outer layer circuit body; 11. FC pad; 12. Connecting copper body; 13. Connecting copper body A; 2. Electrophoretic insulation layer; 20. Window; 3. Metal surface treatment layer; 4. Solder mask layer; 5. Insulating intermediate layer; 6. Inner layer circuit layer; 7. Insulating reinforcement layer. Detailed Implementation

[0017] The preferred embodiments of this utility model will be described in detail below with reference to the accompanying drawings.

[0018] Example 1:

[0019] Please see the appendix Figure 1 and attached Figure 2 As shown, this embodiment 1 provides an FC packaging substrate, including an insulating intermediate layer 5 and outer circuit layers stacked on opposite sides of the insulating intermediate layer 5. That is, the FC packaging substrate provided in this embodiment 1 is a double-layer board. Each of the outer circuit layers is provided with an outer circuit pattern 1. It can be understood that the outer circuit pattern 1 is provided with an outer circuit body 10 and FC pads 11. Furthermore, each of the outer circuit layers is also divided into solder mask areas. The solder mask areas refer to the areas that do not need to be soldered during subsequent product assembly (such as the assembly of the FC packaging substrate with chips and other devices), that is, the areas that need to be protected.

[0020] Specifically, in this embodiment 1, an electrophoretic insulating layer 2 is provided on at least one of the two outer circuit layers. Specifically, in this embodiment 1, an electrophoretic insulating layer 2 with a window 20 is deposited on the outer circuit pattern 1 of the outer circuit layer using electrophoretic deposition technology. Furthermore, based on the electrophoretic insulating layer 2, in this embodiment 1, a metal surface treatment layer 3 is also deposited on the area of ​​the outer circuit pattern 1 that is exposed outside the window 20. Additionally, a solder resist layer 4 is provided on the outer circuit layer that can cooperate with the electrophoretic insulating layer 2 to completely cover the solder resist area on the outer circuit layer. Understandably, in this embodiment 1, an electrophoretic insulating layer 2 with stronger adhesion is applied to the outer circuit pattern 1 (it is known that both the inner and outer circuit patterns are made of copper), and then the solder resist layer 4 is used to fill and cover the solder resist areas not covered by the electrophoretic insulating layer 2. On the one hand, the strong adhesion between the electrophoretic insulating layer 2 and the outer circuit pattern 1 effectively avoids the phenomenon of solder resist layer cracking caused by abnormal thickness of the solder resist layer in the prior art, that is, it effectively avoids the phenomenon of false copper exposure, thereby significantly improving product quality. On the other hand, the strong adhesion between the electrophoretic insulating layer 2 and the outer circuit pattern 1 also effectively reduces the processing difficulty, such as making the thickness control of the electrophoretic insulating layer 2 and the solder resist layer 4 more flexible, and making the line width and line spacing control of the outer circuit pattern 1 more flexible. Thus, it can effectively improve the processing convenience and efficiency of the FC packaging substrate, reduce processing costs, and facilitate production implementation.

[0021] For further details, please refer to the appendix. Figure 1 and attached Figure 2 As shown, according to product design requirements, in this embodiment 1, an electrophoretic insulating layer 2 with a window 20 is provided on the outer circuit pattern 1 of one of the outer circuit layers. Specifically, the electrophoretic insulating layer 2 is provided on both the outer circuit body 10 and the FC pad 11 of the outer circuit pattern 1.

[0022] Furthermore, the material of the electrophoretic insulating layer 2 is electrophoretic resin (specifically, epoxy resin may be used, but is not limited to), and in order to meet the technical requirement that the height difference between the pads in the outer circuit pattern and the electrophoretic insulating layer 2 is <5μm, the thickness of the electrophoretic insulating layer 2 is preferably controlled to be 10-12μm.

[0023] For further details, please refer to the appendix. Figure 1 and attached Figure 2As shown, according to product design requirements, the metal surface treatment layer 3 can be any one of a nickel-gold layer, a nickel-palladium-gold layer, a nickel-silver layer, a nickel-palladium-silver layer, and a tin layer (preferably a nickel-gold layer or a nickel-palladium-gold layer), and the thickness of the metal surface treatment layer 3 is the same as the thickness of the electrophoretic insulating layer 2, which is also 10-12 μm. It is understood that the metal surface treatment layer 3 is the area that needs to be soldered during subsequent product assembly (such as the assembly of the FC packaging substrate with chips and other devices).

[0024] The solder resist layer 4 is a solder resist ink layer, and the thickness of the solder resist layer 4 is 10-30 μm. It is understood that in this embodiment 1, the selectable thickness range of the solder resist layer 4 is relatively large, which also indicates that this embodiment 1 can achieve more flexible control over the thickness of the solder resist layer 4.

[0025] The insulating intermediate layer 5 may be, but is not limited to, a prepreg. The thickness / number of layers of the insulating intermediate layer 5 may be determined according to the product design requirements. This embodiment 1 does not impose any restrictions.

[0026] As can be seen from the above, the FC packaging substrate provided in this embodiment 1 has the advantages of high structural stability, high product yield, easy processing and manufacturing, high processing efficiency and low processing cost, which well meet the needs of FC packaging technology.

[0027] Example 2:

[0028] This embodiment 2 also provides an FC packaging substrate, and compared with embodiment 1, the FC packaging substrate provided in this embodiment 2 has the following differences: ① The FC packaging substrate provided in this embodiment 2 is a multilayer board structure.

[0029] Specifically, regarding the above-mentioned differences ①.

[0030] Please see the appendix Figure 3 As shown, the FC packaging substrate provided in this embodiment 2 has the following structure: it includes an insulating intermediate layer 5, two inner circuit layers 6 respectively stacked on opposite sides of the insulating intermediate layer 5, two insulating reinforcement layers 7 respectively stacked on the two inner circuit layers 6, and two outer circuit layers respectively stacked on the two insulating reinforcement layers 7. That is, the FC packaging substrate provided in this embodiment 2 is a four-layer board structure; wherein; Both the insulating intermediate layer 5 and the insulating reinforcement layer 7 can be, but are not limited to, prepregs. The thickness / number of layers of the insulating intermediate layer 5 and the insulating reinforcement layer 7 can be determined according to the product design requirements. This embodiment 2 does not impose any restrictions.

[0031] Both inner circuit layers 6 are provided with inner circuit patterns, and the inner circuit patterns on the two inner circuit layers 6 are electrically connected through connecting copper bodies 12.

[0032] In the two outer circuit layers, each outer circuit layer is provided with an outer circuit pattern 1 (the outer circuit pattern 1 is provided with an outer circuit body 10 and an FC pad 11), and each outer circuit pattern 1 is electrically connected to the adjacent inner circuit pattern through a connecting copper body A13; in addition, each outer circuit layer is also divided into a solder mask area.

[0033] In particular, in this embodiment 2, an electrophoretic insulating layer 2 with a window 20 is also provided on the outer circuit pattern 1 of one of the outer circuit layers, and a metal surface treatment layer 3 is plated on the area of ​​the outer circuit pattern 1 that is exposed outside the window 20. In addition, a solder resist layer 4 is also provided on the outer circuit layer, which can cooperate with the electrophoretic insulating layer 2 to completely cover the solder resist area on the outer circuit layer.

[0034] Understandably, the FC packaging substrate provided in this embodiment 2 also has the advantages of high structural stability, high product yield, easy processing and manufacturing, high processing efficiency and low processing cost, which well meet the needs of FC packaging technology.

[0035] In addition, in the FC packaging substrate provided in this embodiment 2, the material and thickness of the electrophoretic insulating layer 2, the material and thickness of the metal surface treatment layer 3, and the material and thickness of the solder resist layer 4 can all adopt the same technical means as in the above embodiment 1, so they will not be described in detail here.

[0036] Furthermore, the suffixes "A" in the component names in this specification (such as connecting copper body A) are only for clarity of description and are not intended to limit the scope of this utility model patent.

[0037] Many specific details have been set forth in the above description to provide a full understanding of this utility model. However, the above description is only a preferred embodiment of this utility model, and this utility model can be implemented in many other ways different from those described herein. Therefore, this utility model is not limited to the specific embodiments disclosed above. Furthermore, any person skilled in the art can make many possible variations and modifications to the technical solution of this utility model using the methods and techniques disclosed above, or modify it into equivalent embodiments with equivalent changes, without departing from the scope of the technical solution of this utility model. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this utility model, without departing from the content of the technical solution of this utility model, shall still fall within the protection scope of the technical solution of this utility model.

Claims

1. An FC packaging substrate, comprising an outer circuit layer, wherein the outer circuit layer is provided with an outer circuit pattern (1), and wherein a solder resist area is further defined on the outer circuit layer; characterized in that: An electrophoretic insulating layer (2) with a window (20) is provided on the outer circuit pattern (1), and a metal surface treatment layer (3) is plated on the area of ​​the outer circuit pattern (1) exposed outside the window (20). A solder resist layer (4) is also provided on the outer circuit layer. The solder resist layer (4) and the electrophoretic insulating layer (2) work together to completely cover the solder resist area on the outer circuit layer.

2. The FC packaging substrate according to claim 1, characterized in that: The outer circuit pattern (1) has an outer circuit body (10) and an FC pad (11), and the electrophoretic insulating layer (2) is covered on both the outer circuit body (10) and the FC pad (11).

3. The FC packaging substrate according to claim 2, characterized in that: The thickness of the electrophoretic insulating layer (2) is 10-12 μm.

4. The FC packaging substrate according to claim 2, characterized in that: The FC packaging substrate also includes an insulating intermediate layer (5), on which at least one inner circuit layer (6) is stacked on each of the opposite sides of the insulating intermediate layer (5), and on each of the two outermost inner circuit layers (6) is an outer circuit layer. In addition, the electrophoretic insulating layer (2) is provided on at least one of the two outer circuit layers.

5. The FC packaging substrate according to claim 2, characterized in that: The FC package substrate also includes an insulating intermediate layer (5), and the outer circuit layer is stacked on both sides of the insulating intermediate layer (5); In addition, the electrophoretic insulating layer (2) is provided on at least one of the two outer circuit layers.

6. The FC packaging substrate according to claim 1, characterized in that: The metal surface treatment layer (3) is any one of nickel-gold layer, nickel-palladium-gold layer, nickel-silver layer, nickel-palladium-silver layer and tin layer, and the thickness of the metal surface treatment layer (3) is the same as the thickness of the electrophoretic insulating layer (2).

7. The FC packaging substrate according to claim 1, characterized in that: The solder resist layer (4) is a solder resist ink layer, and the thickness of the solder resist layer (4) is 10 to 30 μm.

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