Semiconductor package for surface mount devices

Abstract

A semiconductor package for a surface mount device is disclosed. The semiconductor package can include a metal housing having a main portion with a closed side and an open side, wherein a periphery is disposed at the open side. The semiconductor package can also include a semiconductor die disposed within the housing, wherein a first major surface of the semiconductor die is electrically coupled to the closed side of the metal housing. The semiconductor package can also include an external interposer disposed opposite a second major surface of the semiconductor die, wherein the external interposer and the periphery are arranged in a coplanar manner.

Description

Technical Field

[0001] The embodiments relate to the field of semiconductor devices, and particularly to the packaging of power semiconductor chips. Background Technology

[0002] Semiconductor device packages (or simply "semiconductor packages") (such as power modules or discrete packages) may include components such as semiconductor dies (chips), substrates, and connectors, the latter of which may include wires, clips, and other connectors. Particularly in power semiconductor packages, power chips such as thyristors, field-effect transistors (FETs), insulated-gate bipolar transistors (IGBTs), and auxiliary chips (including diodes) may be included. The primary purpose of clips is to electrically connect these chips to each other or to the substrate.

[0003] In some known packages, such as those for surface mount devices, external leads are attached to a semiconductor die. For example, in an overvoltage protection device, a first lead may be attached to a semiconductor die on a first main surface to connect to a first device terminal (such as an anode), while a second lead is attached to a semiconductor die on a second main surface to connect to a second terminal (such as a cathode). The lead and die assembly may be encapsulated in a housing that can be overmolded around the chip and a portion of the leads. The leads may then extend outside the housing for mounting to external components, such as printed circuit boards (PCBs). However, this known packaging method requires the use of a molding process to form the housing around the chip. Furthermore, the chip is relatively thermally insulated within the housing, making heat dissipation during operation potentially undesirable.

[0004] In view of the above, this embodiment is provided. Utility Model Content

[0005] In one embodiment, a semiconductor package for a surface-mount device is provided. The semiconductor package may include a metal housing having a closed side and an open side on a major portion, with a periphery disposed on the open side. The semiconductor package may further include a semiconductor die disposed within the housing, wherein a first major surface of the semiconductor die is electrically coupled to the closed side of the metal housing. The semiconductor package may further include an outer insert disposed opposite a second major surface of the semiconductor die, wherein the outer insert and the periphery are arranged coplanarly. The closed side of the metal housing has an imprinted structure, wherein a solder layer is disposed between the semiconductor die and the closed side. The semiconductor die includes a TVS diode having a first major terminal extending on the first major surface and a second major terminal extending on the second major surface.

[0006] In another embodiment, another semiconductor package for surface mount devices is provided. The semiconductor package may include a metal housing having a closed side and an open side on a major portion, with a periphery disposed on the open side. The semiconductor package may include a semiconductor die having an overvoltage protection device disposed within the housing, wherein a first major surface of the semiconductor die is electrically coupled to the closed side of the metal housing. The semiconductor package may further include an external insert disposed opposite a second major surface of the semiconductor die, wherein the external insert and the periphery are arranged coplanarly. The overvoltage protection device is a transient voltage suppression device or a Sidactor device. The semiconductor package further includes an internal insert disposed between the first major surface of the semiconductor die and the closed side of the metal housing. The semiconductor package further includes: a first solder layer disposed between the internal insert and the closed side of the metal housing; a second solder layer disposed between the internal insert and the semiconductor die; and a third solder layer disposed between the semiconductor die and the external insert. The closed side of the metal housing has an imprinted structure, wherein the solder layer is disposed between the semiconductor die and the closed side. Attached Figure Description

[0007] Figure 1A A bottom plan view of a semiconductor package according to an embodiment of the present disclosure is shown;

[0008] Figure 1B It shows Figure 1A A side cross-sectional view of a semiconductor package;

[0009] Figure 1C It shows Figure 1A An end cross-sectional view of a semiconductor package;

[0010] Figure 1D It shows Figure 1A Top isometric view of a semiconductor package;

[0011] Figure 1E It shows Figure 1A Bottom isometric view of the semiconductor package;

[0012] Figure 1F It shows Figure 1A The semiconductor package is in an end cross-sectional view in a configuration attached to a substrate;

[0013] Figure 2A A bottom plan view of another semiconductor package according to an embodiment of the present disclosure is shown;

[0014] Figure 2B It shows Figure 2A A side cross-sectional view of a semiconductor package;

[0015] Figure 2CIt shows Figure 2A An end cross-sectional view of a semiconductor package;

[0016] Figure 3A A bottom plan view of an additional semiconductor package according to an embodiment of the present disclosure is shown;

[0017] Figure 3B It shows Figure 3A A side cross-sectional view of a semiconductor package;

[0018] Figure 3C It shows Figure 3A An end cross-sectional view of a semiconductor package;

[0019] Figure 4A A bottom plan view of another semiconductor package according to an embodiment of the present disclosure is shown;

[0020] Figure 4B It shows Figure 4A A side cross-sectional view of a semiconductor package;

[0021] Figure 4C It shows Figure 4A An end cross-sectional view of a semiconductor package;

[0022] Figure 5A A bottom plan view of yet another semiconductor package according to an embodiment of the present disclosure is shown;

[0023] Figure 5B It shows Figure 5A A side cross-sectional view of a semiconductor package;

[0024] Figure 5C It shows Figure 5A An end cross-sectional view of a semiconductor package;

[0025] Figure 6A A bottom plan view of yet another semiconductor package according to an embodiment of the present disclosure is shown;

[0026] Figure 6B It shows Figure 6A A side cross-sectional view of a semiconductor package; and

[0027] Figure 6C It shows Figure 6A An end cross-sectional view of a semiconductor package. Detailed Implementation

[0028] This embodiment will now be described more fully below with reference to the accompanying drawings, in which exemplary embodiments are illustrated. The embodiments should not be construed as limiting oneself to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey its scope to those skilled in the art. In the drawings, similar numerals consistently refer to similar elements.

[0029] In the following description and / or claims, the terms “on,” “over,” “set on,” and “above” may be used in the following description and claims. “On,” “over,” “set on,” and “above” may be used to indicate that two or more elements are in direct physical contact with each other. Furthermore, the terms “on,” “over,” “set on,” and “above” may mean that two or more elements are not in direct contact with each other. For example, “above” may mean that one element is on top of another element without contacting each other, and there may be one or more other elements between the two elements. Additionally, the term “and / or” may mean “and,” it may mean “or,” it may mean “exclusive,” it may mean “one,” it may mean “some, but not all,” it may mean “neither,” and / or it may mean “both,” although the scope of the claimed subject matter is not limited in this respect.

[0030] In various embodiments, a novel method for packaging and assembling semiconductor devices is provided. As described below, the semiconductor device package includes novel combinations of package housings and inserts, for example, for SMD device technology. As used herein, SMD can refer to surface mount devices for applications such as mounting on a suitable substrate (e.g., a printed circuit board (PCB)).

[0031] Figure 1A A bottom plan view of a semiconductor package 100 according to an embodiment of the present disclosure is shown. The semiconductor package 100 can be used for SMD devices, such as applications in which the semiconductor package 100 is attached to a substrate such as a PCB. The semiconductor package 100 may include a metal housing, shown as housing 102. Housing 102 may be, in particular, an electrical conductor and a high thermal conductor. In this embodiment and subsequent similar embodiments, housing 102 may include a main portion 103 having a closed side 102A and an open side 102B, wherein a periphery 112 is disposed on or around the open side 102B. Thus, the main portion 103 of housing 102 defines a cavity or recess to accommodate various components, particularly such as Figure 1B , Figure 1C , Figure 1E and Figure 1F As best shown.

[0032] The housing 102 may include a first tab 114A extending from the rim 112 along a first edge of the main portion 103 of the housing 102, and may also include a second tab 114B extending from the rim 112 along a second edge of the main portion 103 of the housing 102. These tabs may be used as lead structures for attachment to external circuitry.

[0033] The semiconductor package 100 may further include a semiconductor die 104 disposed within a housing 102, wherein a first main surface of the semiconductor die 104 is electrically coupled to a closed side 102A of the housing 102. In some non-limiting embodiments, the semiconductor die 104 may be a transient voltage suppression (TVS) diode or Sidexor® (Sidexor is a trademark of Littelfuse Inc.). The semiconductor package 100 may further include an external insert 106 disposed opposite to a second main surface of the semiconductor die 104, wherein the external insert 106 and the periphery 112 are arranged in a coplanar manner, such as... Figure 1B and Figure 1C As best shown in the diagram. Therefore, the semiconductor package 100 can be conveniently mounted on the substrate 105, such as Figure 1F As shown. In Figures 1A to 1F In a specific embodiment, the first tab 114A and the second tab 114B are arranged coplanarly with the external insert 106, such as... Figure 1C and Figure 1F As best illustrated in the diagram. Therefore, when the semiconductor package 100 is mounted on the substrate 105, these tabs act as leads that can be easily coupled to electrical connections on the substrate 105. Furthermore, since the first tab 114A and the second tab 114B are arranged coplanarly with the external plug 106, these structures can be easily attached to the same surface of the substrate 105.

[0034] exist Figures 1A to 1FIn a particular embodiment, the semiconductor package 100 further includes an inner insert 108 disposed between a first main surface of the semiconductor die 104 and a closed side 102A of the housing 102. In this and other embodiments, the inserts (such as the inner insert 108 and the outer insert 106) can be sheet-like or block-like suitable metallic materials, such as copper blocks. The inserts can act as both electrical and thermal conductors. Thus, for example, the inner insert 108 can be a copper block that connects a first terminal of the semiconductor die 104 on the first main surface (the surface facing the closed side 102A) to the housing 102. The inner insert 108 can serve as a good thermal conductor to conduct heat away from the semiconductor die 104 during operation, where heat can be more easily dissipated through the housing 102 to the external environment. Similarly, the outer insert 106 can be a copper block that connects a second terminal of the semiconductor die 104 on the second main surface (the surface facing the open side 102B) to external circuitry in the substrate 105. The external plug 106 can also serve as a good thermal conductor to conduct heat away from the semiconductor die 104 during operation, where the heat can be more easily dissipated into the substrate 105.

[0035] Note that, according to various embodiments of this disclosure, the thickness of the outer insert 106 and / or the thickness of the inner insert 108 can be adjusted according to the thickness of the semiconductor die 104 so that the outer surface of the outer insert 106 remains coplanar with the first tab 114A and the second tab 114B. Therefore, for example, for two different packages where the semiconductor die in the first package is thicker than the semiconductor die in the second package, the thickness of the outer insert in the first package can be less than the thickness of the outer insert in the second package.

[0036] In various embodiments, components within housing 102 may be mechanically and electrically coupled to each other using a set of suitable bonding layers, such as solder layers. These layers are shown as layer 110A bonding the outer insert 106 to the semiconductor die 104, layer 110B bonding the semiconductor die 104 to the inner insert 108, and layer 110C bonding the inner insert 108 to the closed side 102A of housing 102. Each of these layers may be formed, for example, by providing solder material on the relevant surface and by heat-treating the solder.

[0037] Figure 2AA bottom plan view of a semiconductor package 120 according to an embodiment of the present disclosure is shown. The semiconductor package 120 can be used in SMD devices, such as applications where the semiconductor package 100 is attached to a substrate such as a PCB. The semiconductor package 120 may include components similar to those in the semiconductor package 100, wherein similar components are labeled as identical and can perform the same function. In this embodiment, the semiconductor package 120 may include additional components including a second semiconductor die (shown as semiconductor die 122) disposed between a first semiconductor die (i.e., semiconductor die 104) and an internal insert 108, and an intermediate insert 124 disposed between semiconductor die 104 and semiconductor die 122. Figure 2B and Figure 2C As best shown, the package may also include a series of interface layers (such as solder) to bond the various components of the semiconductor package to each other, providing electrical coupling and good thermal coupling between the components. These layers are shown as layer 130A for bonding the outer insert 106 to the semiconductor die 104; layer 130B for bonding the semiconductor die 104 to the intermediate insert 124; layer 130C for bonding the intermediate insert 124 to the semiconductor die 122; layer 130D for bonding the inner insert 108 to the semiconductor die 122; and layer 130E for bonding the inner insert 108 to the closed side 102A of the housing 102.

[0038] exist Figures 2A to 2C In this configuration, two semiconductor dies are housed within a housing 102. In one example, semiconductor dies 104 and 122 each form a TVS diode device, which may be arranged in a cathode-to-anode manner, such that the breakdown voltage increases based on the sum of the individual breakdown voltages of the two different semiconductor dies. In other embodiments, the semiconductor package including the housing 102 or a similar housing may comprise three or more stacked semiconductor dies.

[0039] In another embodiment of this disclosure, the semiconductor die may be arranged in a housing having a plurality of inserts, one of which has a different thickness than at least one of the other inserts. Figures 3A to 3C An embodiment of this is shown in detail, illustrated as a semiconductor package 140, in which a single semiconductor die is sandwiched between two inserts, similar to... Figures 1A to 1FThe configuration of the semiconductor package 100 differs from that of the semiconductor package 140 in that an outer insert 146 is provided, which has a greater thickness than the inner insert 108. This arrangement can help adjust the thermal conduction between the semiconductor die 104 and the external substrate, the heat capacity for absorbing generated heat, and / or the electrical conduction, and also helps adjust the electrical / thermal conduction between the semiconductor die 104 and the housing 102. However, in other embodiments, depending on the target operation of the package, an inner insert with a greater thickness than the outer insert may be used.

[0040] In the above embodiments, the housing is provided with a pair of tabs that can be used as leads for coupling to circuitry in external components, such as PCBs. However, in other embodiments, the tabs can be omitted, where the periphery 112 is sufficient to form an external electrical connection. Figures 4A to 4C An embodiment of this is illustrated in detail, shown as a semiconductor package 160, which provides a housing 162 similar to housing 102, but differing in that no tabs are provided along the periphery 112. Compared to housing 102, this housing may have the advantage of being relatively easy to manufacture.

[0041] exist Figure 1A , Figure 2A and Figure 3A In the above embodiments, the housing is provided with a pair of tabs arranged along opposite edges of the periphery 112. Figures 5A to 5C Another embodiment, shown as semiconductor package 180, is presented, wherein the housing 182 includes a pair of tabs, shown as a first tab 114A and a second tab 184, arranged along adjacent edges of the periphery 112. This configuration can facilitate coupling to a specific configuration of circuitry within a substrate in which the housing 182 is to be mounted. Therefore, the different embodiments described above provide design flexibility, and particularly flexibility for different applications, depending on the different configurations of circuitry that may exist in different substrates.

[0042] In the above embodiments, a semiconductor package is provided, which includes an inner insert adjacent to the closed side of the housing. However, in another embodiment, the inner insert may be omitted, wherein the semiconductor die is arranged adjacent to the closed side. Figures 6A to 6C An embodiment shown in detail is a semiconductor package 190, in which a housing 192 similar to housing 102 is provided, but the difference is that the closed side 102A is provided with a coining structure 194, which does not include an internal insert. The housing 192 may have the same dimensions and overall shape as housing 102, but can be coined onto the closed side 102A, thus allowing the housing 192 to be in close contact with the semiconductor die 104 without the use of an internal insert. This method saves the cost of coupling the semiconductor chip to a metal housing using an internal insert.

[0043] In a variation of the above embodiments, the housing may be provided with a sealant in a cavity formed by the main portion of the housing, wherein the sealant is typically disposed between the semiconductor die and the housing to ensure that the devices formed in the semiconductor die maintain electrical isolation between their different terminals. In a particular embodiment, the sealant may be an epoxy resin sealant.

[0044] While this embodiment has been disclosed with reference to certain embodiments, numerous modifications, alterations, and changes are possible to the described embodiments without departing from the scope and domain of this disclosure as defined in the appended claims. Therefore, this embodiment is not limited to the described embodiments and may have the full scope defined by the language of the following claims and their equivalents.

Claims

1. A semiconductor package for surface mount devices, characterized in that, The semiconductor package includes: A metal housing comprising a main portion having a closed side and an open side, wherein a periphery is disposed on the open side; A semiconductor die, the semiconductor die being disposed within a housing, wherein a first main surface of the semiconductor die is electrically coupled to a closed side of the metal housing; and An external component is disposed opposite to the second main surface of the semiconductor die, wherein the external component and the periphery are arranged in a coplanar manner.

2. The semiconductor package according to claim 1, characterized in that, The semiconductor package further includes: An internal insert is disposed between the first main surface of the semiconductor die and the closed side of the metal housing.

3. The semiconductor package according to claim 2, characterized in that, The semiconductor die is a first semiconductor die, and the semiconductor package further includes: A second semiconductor die, the second semiconductor die being disposed between the first semiconductor die and the internal component; and An intermediate plug-in is disposed between the first semiconductor die and the second semiconductor die.

4. The semiconductor package according to claim 2, characterized in that, The outer insert has a first thickness, and the inner insert has a second thickness that is less than the first thickness.

5. The semiconductor package according to claim 1, characterized in that, The metal casing also includes: A first tab, the first tab extending from the periphery along a first edge of the main portion of the housing; and The second tab extends from the periphery along the second edge of the main portion of the housing, wherein the first tab and the second tab are arranged in a coplanar manner with the external plug.

6. The semiconductor package according to claim 5, characterized in that, The first edge is adjacent to the second edge.

7. The semiconductor package according to claim 1, characterized in that, The closed side of the metal casing has an embossed structure, wherein a solder layer is disposed between the semiconductor die and the closed side.

8. The semiconductor package according to claim 1, characterized in that, The external plug-in includes a copper block.

9. The semiconductor package according to claim 1, characterized in that, The semiconductor die includes a TVS diode having a first main terminal extending on the first main surface and a second main terminal extending on the second main surface.

10. The semiconductor package according to claim 1, characterized in that, The semiconductor package also includes a sealant disposed between the semiconductor die and the metal housing.

11. A semiconductor package for surface mount devices, characterized in that, The semiconductor package includes: A metal housing comprising a main portion having a closed side and an open side, wherein a periphery is disposed on the open side; A semiconductor die, the semiconductor die including an overvoltage protection device and disposed within a metal housing, wherein a first main surface of the semiconductor die is electrically coupled to a closed side of the metal housing; and An external component is disposed opposite to the second main surface of the semiconductor die, wherein the external component and the periphery are arranged in a coplanar manner.

12. The semiconductor package according to claim 11, characterized in that, The overvoltage protection device is a transient voltage suppression device or a Sidactor device.

13. The semiconductor package according to claim 11, characterized in that, The semiconductor package further includes: An internal insert is disposed between the first main surface of the semiconductor die and the closed side of the metal housing.

14. The semiconductor package according to claim 13, characterized in that, The semiconductor package further includes: A first solder layer is disposed between the inner insert and the closed side of the metal housing; A second solder layer is disposed between the internal component and the semiconductor die; and A third solder layer is disposed between the semiconductor die and the external component.

15. The semiconductor package according to claim 13, characterized in that, The semiconductor die is a first semiconductor die, and the semiconductor package further includes: A second semiconductor die, the second semiconductor die being disposed between the first semiconductor die and the internal component; and An intermediate plug-in is disposed between the first semiconductor die and the second semiconductor die.

16. The semiconductor package according to claim 13, characterized in that, The outer insert has a first thickness, and the inner insert has a second thickness that is less than the first thickness.

17. The semiconductor package according to claim 11, characterized in that, The metal casing also includes: A first tab, the first tab extending from the periphery along a first edge of the main portion of the housing; and The second tab extends from the periphery along the second edge of the main portion of the housing, wherein the first tab and the second tab are arranged in a coplanar manner with the external plug.

18. The semiconductor package according to claim 17, characterized in that, The first edge is adjacent to the second edge.

19. The semiconductor package according to claim 11, characterized in that, The closed side of the metal casing has an embossed structure, wherein a solder layer is disposed between the semiconductor die and the closed side.

20. The semiconductor package according to claim 11, characterized in that, The external plug-in includes a copper block.

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