A test board and power supply test system

Abstract

The utility model provides a kind of test board and power supply test system, applied to testing device technical field.In the utility model, on the basis of keeping original mainboard power supply environment, by test board is divided into main test board and power interface daughterboard, then setting a interboard connector on main test board and power interface daughterboard respectively, and then using interboard connector to connect main test board and interboard connector in pluggable mode, and then not only greatly improve the replaceability of test board, compatibility, also significantly reduce the damage risk of main test board caused by high-temperature welding;And, in PMIC chip iteration test, only replace power interface daughterboard can continue to use original main test board, that is, reduce the maintenance cost of PMIC chip, improve test efficiency.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor process equipment technology, and in particular to a test board and power supply test system. Background Technology

[0002] Display devices typically include a display panel and a timing controller; the display panel displays images, and the timing controller controls the overall operation of the display panel. Additionally, the display device may include a power management integrated circuit (PMIC) to supply power to the timing controller. Due to various reasons, defects or malfunctions may occur in the display device, and the causes of these defects and / or malfunctions may be recorded in the display device later when analyzing them.

[0003] Currently, when evaluating whether a new PMIC chip can meet the functions of the original PMIC chip, it is usually tested by directly soldering it onto the motherboard. However, this method requires repeated heating and disassembly with a hot air gun, which inevitably leads to complex soldering, labor-intensive testing, potential impact on the stability and consistency of testing, and the probability of damaging the chip's pads on the driver board with repeated soldering, resulting in the scrapping of the entire driver board. Furthermore, if the PMIC chip has defects, it may also damage the motherboard, further increasing testing costs. Utility Model Content

[0004] The purpose of this invention is to provide a test board and power supply test system to improve the convenience, safety and accuracy of PMIC chip testing.

[0005] To address the aforementioned technical problems, the first embodiment of this utility model provides a test board for performance testing of PMIC chips, comprising:

[0006] The main test board is used to carry the power interface sub-board and includes a first inter-board connector configured to be electrically connected to the power interface sub-board, and a load module configured to simulate the load of the actual driver board of the PMIC chip.

[0007] The power interface sub-board includes a second inter-board connector and is connected to the main test board in a pluggable manner with the first inter-board connector, and is configured to make an electrical connection with the PMIC chip under test.

[0008] Furthermore, one of the first inter-board connector and the second inter-board connector may be a pin header connector, and the other may be a female header connector.

[0009] Furthermore, the load module may include a cement resistor array.

[0010] Furthermore, the main test board may also include:

[0011] A voltage detection module is configured to sample the output voltage of the PMIC chip;

[0012] A microcontroller module, connected to the voltage detection module, is configured to read, judge, and process the output voltage of the voltage detection module in real time.

[0013] The communication module, connected to the microcontroller module, is configured to transmit the test results of the PMIC chip from the main test board to an external terminal device in real time for recording and test adjustment.

[0014] Furthermore, the voltage detection module may include an ADC chip, the ADC chip model may be AD7998, and the microcontroller module may include an STM32 microcontroller.

[0015] Furthermore, the main test board may also include:

[0016] An alarm module, connected to the microcontroller module and including a buzzer, is configured to send an alarm signal to the buzzer when the microcontroller module determines that the output voltage of the voltage detection module is in at least one of the abnormal conditions of overvoltage, undervoltage, or power failure.

[0017] Furthermore, the power interface sub-board may also include:

[0018] An electrostatic discharge (ESD) protection module is configured to provide ESD protection for the output voltage of the PMIC chip.

[0019] Furthermore, the microcontroller module may include multiple GPIO interfaces for configuring GPIO functions of each functional module.

[0020] Furthermore, the power interface sub-board may also include:

[0021] The voltage regulator module is configured to filter the input voltage transmitted from the main test board to the power interface sub-board before supplying power to the PMIC chip.

[0022] To address the aforementioned issues, the second embodiment of this utility model also provides a power supply testing system, which may specifically include the test board as described above, and a DC power supply that provides input voltage to the test board, wherein the operating voltage range of the DC power supply is 12V to 24V.

[0023] Compared with the prior art, the present invention has at least the following technical effects:

[0024] This invention provides a test board and power supply testing system. While maintaining the original motherboard power supply environment, the test board is divided into a main test board and a power interface daughter board. An inter-board connector is then installed on both the main test board and the power interface daughter board. The inter-board connectors allow for pluggable connection between the main test board and the inter-board connectors, which not only significantly improves the replaceability and compatibility of the test board but also significantly reduces the risk of damage to the main test board caused by high-temperature soldering. Furthermore, in PMIC chip iterative testing, only the power interface daughter board needs to be replaced to continue using the original main test board, thus reducing the maintenance cost of PMIC chips and improving testing efficiency.

[0025] Furthermore, the main test board of this invention is also equipped with a load module that simulates the load corresponding to the real environment in the application of PMIC chips, thereby enabling stable and accurate testing of the performance of PMIC chips under load, further improving testing efficiency and reducing the maintenance cost of PMIC chips. Attached Figure Description

[0026] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:

[0027] Figure 1 This is a schematic diagram of the structure of a test board for performance testing of PMIC chips provided in one embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram of the main test board provided in one embodiment of the present invention.

[0029] in, Figure 1 and Figure 2 The attached figures are labeled as follows:

[0030] 100-Main test board, 200-Power interface sub-board, 110-First board connector, 210-Second board connector, 120-Voltage detection module, 130-Micro control module, 140-Communication module, 150-Alarm module. Detailed Implementation

[0031] To make the technical solutions and advantages of the embodiments of this utility model clearer, the technical solutions of this utility model will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this utility model are shown in the accompanying drawings, it should be understood that this utility model can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this utility model and to fully convey the scope of this utility model to those skilled in the art.

[0032] The present invention will be described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and are only used to facilitate and clarify the illustration of the embodiments of the present invention. It is understood that the meanings of "on," "above," and "over" in the present invention should be interpreted in the broadest sense, such that "on" not only means "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer. In the embodiments of the present invention, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present invention can be arbitrarily combined without conflict.

[0033] Please refer to Figure 1 and Figure 2 ,in, Figure 1 The illustration shows a structural schematic diagram of a test board for performance testing of PMIC chips provided in one embodiment of this utility model; Figure 2 The illustration shows a schematic diagram of the main test board provided in one embodiment of this utility model.

[0034] like Figure 1 and Figure 2As shown, the test board in this embodiment of the present invention includes a main test board 100 and a power interface sub-board 200. The main test board 100 is mainly used to support the power interface sub-board 200, which is mainly used to connect the PMIC chip under test and to test the PMIC chip under test through multiple functional modules set in the main test board 100. In one embodiment, the main test board 100 may include a first inter-board connector 110 configured to be electrically connected to the power interface sub-board 200, and a load module (not shown), a voltage detection module 120, a microcontroller module 130, a communication module 140, and an alarm module 150 configured to simulate the load of the actual driver board of the PMIC chip. The power interface sub-board 200 specifically includes a second inter-board connector 210, which is pluggably connected to the main test board 100 through the first inter-board connector 110, and is configured to be electrically connected to the PMIC chip under test.

[0035] In one embodiment, the first inter-board connector 110 may be a pin header connector or a female header connector. The pin header connector includes multiple pin headers, each pin header corresponding to a test pin. The female header connector includes multiple female headers, each female header corresponding to a pin header, thereby realizing the electrical connection of different devices and / or modules. Similarly, each female header also corresponds to a test pin and is associated with a pin header. In this embodiment, the main test board 100 has at least two first inter-board connectors 110, one of which is a pin header connector and the other is a female header connector. The power interface sub-board 200 also has at least two second inter-board connectors 210, one of which is a pin header connector and the other is a female header connector. The female header connector on the main test board 100 is specifically electrically connected to the pin header connector on the power interface sub-board 200, and the pin header connector on the main test board 100 is specifically electrically connected to the female header connector on the power interface sub-board 200. The load module includes a cement resistor array, which includes multiple cement resistors with the same or different resistance values. The specific resistance values ​​of the cement resistors can be changed according to the actual situation, but are not limited thereto.

[0036] The voltage detection module 120 is configured to sample the output voltage of the PMIC chip. In one embodiment, the PMIC chip has multiple output voltages, such as VGH (higher positive voltage), VGL (lower negative voltage), AVDD, HVDD, VCOM, and DVDD, to power different devices. For example, the output voltage DVDD can power digital circuits such as CPU / GPU cores, FPGAs, and memory, while the output voltage AVDD can power analog circuits such as audio codecs, sensors, and analog-to-digital converters (ADCs). The output voltages VGH and VGL provide voltage to the gate driving circuit of the TFT-LCD / OLED display, but are not limited thereto. Specifically, the voltage detection module 120 includes an ADC chip, model AD7998, and the microcontroller module 130 includes an STM32 microcontroller. The microcontroller module 130, connected to the voltage detection module 120, is configured to perform real-time reading, voltage judgment, and logic processing of the output voltage of the voltage detection module 120. The microcontroller module 120 also includes multiple GPIO interfaces for configuring the GPIO functions of each functional module. The communication module 140, connected to the microcontroller module 130, is configured to transmit the test results of the PMIC chip from the main test board 100 to an external terminal device PC in real time for recording and test adjustment. The alarm module 150, connected to the microcontroller module 130 and including a buzzer, is configured to send an alarm signal to the buzzer when the microcontroller module 130 determines that the output voltage of the voltage detection module 120 is in at least one of the following abnormal conditions: overvoltage, undervoltage, or power failure.

[0037] The specific operation of the test board in this utility model is as follows: an external DC power supply, such as a regulated power supply module, inputs an input voltage VIN to the main test board 100, thereby powering the main test board 100 and enabling it to work normally. For example, the range of the input voltage VIN can be 12V to 24V, preferably 12V. Since the main test board 100 and the power interface sub-board 200 are connected together in a pluggable manner through the first inter-board connector 110 and the second inter-board connector 210 on the power interface sub-board 200, when the input voltage VIN is input to the main test board 100, the input voltage VIN is transmitted to the power interface sub-board 200 through the pin header and header header. 00; The power interface sub-board 200 receives the input voltage VIN and filters it through decoupling capacitors and inductors (or other filters) to obtain a stable voltage. This stable voltage is then output to the PMIC chip under test to power it. The PMIC chip then begins normal operation, outputting multiple output voltages and control signals, such as VGH, VGL, AVDD, HVDD, VCOM, DVDD output voltages, and several PWM square wave control signals. Subsequently, the pin headers of the power interface sub-board 200 transmit the output voltages and control signals back to the main test board 100. The main test board 100 receives each output voltage and then inputs it to the voltage detection module 120 through a resistor divider. The ADC chip (e.g., AD7998) in the voltage detection module 120 performs high-precision sampling of the output voltages from each PMIC chip, thus performing a test. The sampled results are then transmitted to the microcontroller module 130 (e.g., MCU), which then processes the parameters sampled by the ADC. The PMIC chip performs real-time reading, voltage judgment, and logic processing of the output voltage. If the microcontroller module 130 determines that a certain output voltage of the PMIC chip is abnormal, such as overvoltage, undervoltage, or power failure, it immediately triggers an LED or buzzer to issue a local alarm through the GPIO port. At the same time, the microcontroller module 130, for example, an MCU, uploads the sampled data and alarm information to an external terminal device PC through the communication module 140. Then, through the external terminal device PC, the test engineer can view the voltage curve, PWM waveform status, or export historical records on the host computer interface, thereby achieving accurate and efficient testing of the PMIC chip.

[0038] It should be noted that the methods, processes, and material descriptions involved in this utility model are all existing technologies used to explain the functionality of the structure or layout proposed in this embodiment.

[0039] In summary, this utility model provides a test board that, while maintaining the original motherboard power supply environment, divides the test board into a main test board and a power interface daughter board. An inter-board connector is then installed on both the main test board and the power interface daughter board, allowing for a pluggable connection between the main test board and the inter-board connector. This significantly improves the replaceability and compatibility of the test board and substantially reduces the risk of damage to the main test board caused by high-temperature soldering. Furthermore, in PMIC chip iterative testing, only the power interface daughter board needs to be replaced to continue using the original main test board, thus reducing PMIC chip maintenance costs and improving testing efficiency.

[0040] Furthermore, the main test board of this invention is also equipped with a load module that simulates the load corresponding to the real environment in the application of PMIC chips, thereby enabling stable and accurate testing of the performance of PMIC chips under load, further improving testing efficiency and reducing the maintenance cost of PMIC chips.

[0041] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the present invention without departing from the scope of the present invention, or equivalent embodiments can be modified based on the disclosed technical content. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

[0042] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various modules, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various modules, elements, and steps.

[0043] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a” and “an” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A test board for performance testing of PMIC chips, characterized in that, include: The main test board is used to carry the power interface sub-board and includes a first inter-board connector configured to be electrically connected to the power interface sub-board, and a load module configured to simulate the load of the actual driver board of the PMIC chip. The power interface sub-board includes a second inter-board connector and is connected to the main test board in a pluggable manner with the first inter-board connector, and is configured to make an electrical connection with the PMIC chip under test.

2. The test board as described in claim 1, characterized in that, One of the first board-to-board connector and the second board-to-board connector is a pin header connector, and the other is a female header connector.

3. The test board as described in claim 1, characterized in that, The load module includes a cement resistor array.

4. The test board as described in claim 1, characterized in that, The main test board also includes: A voltage detection module is configured to sample the output voltage of the PMIC chip; A microcontroller module, connected to the voltage detection module, is configured to read, judge, and process the output voltage of the voltage detection module in real time. The communication module, connected to the microcontroller module, is configured to transmit the test results of the PMIC chip from the main test board to an external terminal device in real time for recording and test adjustment.

5. The test board as described in claim 4, characterized in that, The voltage detection module includes an ADC chip, the model of which is AD7998, and the microcontroller module includes an STM32 microcontroller.

6. The test board as described in claim 4, characterized in that, The main test board also includes: An alarm module, connected to the microcontroller module and including a buzzer, is configured to send an alarm signal to the buzzer when the microcontroller module determines that the output voltage of the voltage detection module is in at least one of the abnormal conditions of overvoltage, undervoltage, or power failure.

7. The test board as described in claim 4, characterized in that, The power interface sub-board also includes: An electrostatic discharge (ESD) protection module is configured to provide ESD protection for the output voltage of the PMIC chip.

8. The test board as described in claim 4, characterized in that, The microcontroller module includes multiple GPIO interfaces for configuring the GPIO functions of each functional module.

9. The test board as described in claim 4, characterized in that, The power interface sub-board also includes: The voltage regulator module is configured to filter the input voltage transmitted from the main test board to the power interface sub-board before supplying power to the PMIC chip.

10. A power supply testing system, characterized in that, The test board includes any one of claims 1 to 9, and a DC power supply that provides an input voltage to the test board, wherein the operating voltage range of the DC power supply is 12V to 24V.

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