High-frequency electrotome negative plate impedance detection circuit

Abstract

The utility model discloses a high -frequency electrotome negative plate impedance detection circuit, including first drive chip, the input of first drive chip receives high -frequency electrotome signal generator's signal, and the original impedance detection signal is produced after the output through first resistance -capacity circuit, still include for the signal pretreatment of original impedance detection signal multichannel selector. The utility model prearranges multichannel selector U2 and is based on its build peripheral circuit and realizes impedance detection signal function, and through FPGA signal control selects and controls multichannel selector U2 internal circuit according to the current working mode, output power range and impedance range, selects the signal wave band of smaller interference and gathers, filters the signal wave band of bigger noise, avoids the interference noise transmission into the later stage calculation unit, leads to the problem of impedance detection inaccuracy. The utility model needs less peripheral circuit, reduces the difference caused by different devices.

Description

Technical Field

[0001] This utility model relates to the field of medical device technology, specifically to an impedance detection circuit for the negative electrode plate of a high-frequency electrosurgical unit. Background Technology

[0002] A high-frequency electrosurgical unit (HFEP) is an electrosurgical instrument that replaces a mechanical scalpel for tissue cutting. It typically includes a distally mounted end effector configured for bipolar or monopolar operation. During bipolar operation, current flows through the tissue via the working and return electrodes of the end effector. During monopolar operation, current flows through the tissue via the working electrode of the end effector and a separate return electrode positioned on the patient's body. The high-frequency, high-voltage current generated at the tip of the working electrode heats the tissue upon contact with the body, achieving tissue separation and coagulation, thereby achieving cutting and hemostasis. Due to its superior performance and ease of operation, the HFEP has become one of the essential pieces of equipment in the operating room.

[0003] Existing high-frequency electrosurgical control systems control energy output by detecting impedance signals, such as the high-frequency electrosurgical control method disclosed in Chinese Patent Publication No. CN114886552A. Since high-frequency electrosurgical devices target biological tissue, its impedance value changes under the influence of high-frequency current. If the impedance detection of the negative electrode is inaccurate, it can easily cause skin burns and serious medical accidents. This is because during surgery, patients are anesthetized and cannot perceive the heat and burns to their skin or internal tissues. If the contact status of the negative electrode is not detected in time, irreversible burns can occur within a very short period. Therefore, Chinese Patent Publications Nos. CN112666397A and CN107907744A disclose different impedance detection circuits or methods. Currently, the common method for detecting the impedance of the negative electrode is to sample the impedance detection signal in the high-frequency current loop using transformer coupling, and then transmit it to the impedance calculation module after signal processing (filtering). Generally, an FPGA (Field-Programmable Gate Array) device is used to calculate the impedance value.

[0004] However, the current domestic negative plate detection circuits suffer from problems such as a single detection method, insufficient detection accuracy, and poor detection flexibility. They cannot reflect the true state of contact impedance in a timely and accurate manner. In particular, they may transmit noisy impedance detection signals to subsequent calculation units, causing calculation deviations and posing a great safety hazard to the operation. Utility Model Content

[0005] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a high-frequency electrosurgical negative plate impedance detection circuit.

[0006] The objective of this utility model is achieved through the following technical solution: A high-frequency electrosurgical unit negative electrode plate impedance detection circuit includes a first driver chip. The input terminal of the first driver chip receives a signal from a high-frequency electrosurgical unit signal generator, and the output terminal generates a raw impedance detection signal after passing through a first RC circuit. It also includes a multiplexer for preprocessing the raw impedance detection signal. Pin 5 of the multiplexer is connected to the first RC circuit to receive the raw impedance detection signal; pin 1 receives a signal from an FPGA via a fifth resistor, thereby controlling the route selection within the multiplexer; pin 8 serves as a signal output terminal, connected to the inverting input terminal of a third operational amplifier via a fourth resistor to transmit the preprocessed impedance detection signal to the third operational amplifier. A first resistor and a second capacitor are connected in parallel between the inverting input terminal and the output terminal of the third operational amplifier. The first resistor adjusts the amplification factor and, together with the second capacitor, forms a low-pass filter and provides phase compensation.

[0007] Preferably, pin 16 of the multiplexer is grounded through a sixth resistor; pin 2 is connected to VCC_4 through an eighth resistor. This pin is the enable pin and is set to normally open.

[0008] Preferably, the first RC circuit consists of a capacitor and a resistor connected to the output terminal of the first driver chip.

[0009] Preferably, the non-inverting input terminal of the first driver chip is connected to VCC_1, and a third capacitor and a fourth capacitor connected in parallel serve as bypasses for filtering VCC_1.

[0010] Preferably, the first driver chip is the MC33152DR2G model from ON Semiconductor.

[0011] Preferably, the output terminal of the third operational amplifier is connected to the non-inverting input terminal of the fourth operational amplifier through the eleventh resistor and the twelfth resistor. The non-inverting input terminal of the fourth operational amplifier is grounded through the eleventh capacitor, and its inverting input terminal is shorted to the output terminal.

[0012] Preferably, the ninth capacitor is connected between the output of the fourth operational amplifier and the connection point of the eleventh and twelfth resistors.

[0013] Preferably, the output terminal of the fourth operational amplifier is connected to the inverting input terminal of the fifth operational amplifier through the tenth resistor, one end of the ninth resistor and the tenth capacitor are connected to the inverting input terminal of the fifth operational amplifier, and the other end is connected to the negative terminal of the diode; the non-inverting input terminal of the fifth operational amplifier is grounded.

[0014] Preferably, the output terminal of the fifth operational amplifier is connected to the non-inverting input terminal of the sixth operational amplifier through the diode, the thirteenth resistor, and the fourteenth resistor. The inverting input terminal of the sixth operational amplifier is grounded through the seventeenth resistor, and its output terminal is connected to the inverting input terminal through the sixteenth resistor.

[0015] Preferably, the output of the sixth operational amplifier is RC filtered by the fifteenth resistor and the thirteenth capacitor, and then output as an AD acquisition to convert the analog signal into a digital signal.

[0016] The main advantages of this invention are as follows: A pre-defined multiplexer U2 is used to build an external circuit based on it to achieve impedance detection signal functionality. Through FPGA signal control, the internal circuitry of the multiplexer U2 is selected and controlled according to the current operating mode, output power range, and impedance range. This selects signal bands with less interference for acquisition and filters out signal bands with higher noise levels, preventing interference noise from entering the subsequent calculation unit and causing inaccurate impedance detection. This invention requires fewer external circuits, reducing variability caused by different components. Attached Figure Description

[0017] The technical solution of this utility model will be further described below with reference to the accompanying drawings: Figure 1 : Schematic diagram of the detection circuit of this utility model. Detailed Implementation

[0018] The present invention will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments are not limited to the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the protection scope of the present invention.

[0019] like Figure 1 As shown, this utility model discloses an impedance detection circuit for the negative electrode plate of a high-frequency electrosurgical unit, including a first driver chip U1, which is an MC33152DR2G model from ON Semiconductor. Its input terminal receives a signal from a high-frequency electrosurgical unit signal generator, and its output terminal generates the original impedance detection signal after passing through a first RC circuit. The first RC circuit consists of a capacitor C6 and a resistor R7 connected to the output terminal of the first driver chip U1. The non-inverting input terminal of the first driver chip U1 is connected to VCC_1, and a third capacitor C3 and a fourth capacitor C4 connected in parallel serve as bypass filters for VCC_1.

[0020] In existing technologies, the generated raw impedance detection signal is directly transmitted to the subsequent calculation unit to calculate the impedance value of the negative plate. However, the feature of this invention is that an impedance detection signal preprocessing circuit is added. After filtering out the impedance detection signal with noise, the preprocessed impedance detection signal is then transmitted to the subsequent calculation unit. The specific structure is shown below.

[0021] The impedance detection signal preprocessing circuit includes a multiplexer U2 for preprocessing the original impedance detection signal. Pin 5 is connected to the first RC circuit to receive the original impedance detection signal; pin 1 receives signal control from the FPGA through resistor R5, thereby controlling the internal route selection of the multiplexer U2; pin 16 is also a pin controlling the internal selection of U2, and is normally grounded through resistor R6; pin 2 is connected to VCC_4 through resistor R8, and this pin is the enable pin, set to normally open. Pin 3 is connected to power supply VCC_3 to provide a negative operating voltage to the multiplexer U2, and is also grounded through capacitor C8 for bypass filtering. Pin 15 is directly grounded, serving as the chip's ground pin. Pin 14 is connected to power supply VCC_2 to provide a positive operating voltage to the multiplexer U2, and is also grounded through capacitor C1 for bypass filtering. Pin 4 is grounded, serving as one of the signal inputs for the multiplexer U2, used for chip multiplexing and selection.

[0022] In this embodiment, the voltage value of VCC1 is 9V, the voltage value of VCC2 is 12V, and the voltage value of VCC3 is -12V.

[0023] Pin 8 of the multiplexer U2 serves as the signal output terminal. It is connected to the inverting input terminal of the third operational amplifier U3 via the fourth resistor R4 to transmit the pre-processed impedance detection signal to the third operational amplifier U3. The first resistor R1 and the second capacitor C2 are connected in parallel between the inverting input terminal and the output terminal of the third operational amplifier U3. The first resistor R1 plays the role of adjusting the amplification factor and, together with the second capacitor C2, forms a low-pass filter and phase compensation.

[0024] The output of the third operational amplifier U3 is connected to the non-inverting input of the fourth operational amplifier U4 via the eleventh resistor R11 and the twelfth resistor R12. The non-inverting input of the fourth operational amplifier U4 is grounded via the eleventh capacitor C11, and its inverting input is shorted to the output. The ninth capacitor C9 is connected between the output of the fourth operational amplifier U4 and the connection point of the eleventh resistor R11 and the twelfth resistor R12, for loop compensation of the operational amplifier circuit. The fourth operational amplifier U4 and its peripheral circuitry function as a voltage follower, providing buffer isolation and improving the circuit's load-carrying capacity.

[0025] The output of the fourth operational amplifier U4 is connected to the inverting input of the fifth operational amplifier U5 via the tenth resistor R10. One end of the ninth resistor R9 and the tenth capacitor C10 are connected to the inverting input of the fifth operational amplifier U5, and the other end is connected to the cathode of the diode D1. The non-inverting input of the fifth operational amplifier U5 is grounded. The fifth operational amplifier U5 and its peripheral circuits flip the voltage value of the negative half-cycle to positive, facilitating subsequent sampling and identification.

[0026] The output of the fifth operational amplifier U5 is connected to the non-inverting input of the sixth operational amplifier U6 via diode D1, thirteenth resistor R13, and fourteenth resistor R14. The inverting input of the sixth operational amplifier U6 is grounded via seventeenth resistor R17, and its output is connected to the inverting input via sixteenth resistor R16. This section serves as a forward amplification circuit, scaling the signal to the voltage range required for subsequent AD acquisition, ensuring acquisition accuracy. The output of the sixth operational amplifier U6 is RC filtered via fifteenth resistor R15 and thirteenth capacitor C13 before being output as an AD converter, converting the analog signal into a digital signal.

[0027] The circuit design of this utility model uses fewer components, does not add any extra processing steps, and reduces the variability of components.

[0028] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0029] The detailed descriptions listed above are merely specific descriptions of feasible implementations of this utility model, and are not intended to limit the scope of protection of this utility model. All equivalent implementations or modifications made without departing from the spirit of this utility model should be included within the scope of protection of this utility model.

Claims

1. A high-frequency electrosurgical unit negative electrode plate impedance detection circuit, comprising a first driving chip (U1), wherein the input terminal of the first driving chip (U1) receives a signal from a high-frequency electrosurgical unit signal generator, and the output terminal generates an original impedance detection signal after passing through a first RC circuit; characterized in that: It also includes a multiplexer (U2) for preprocessing the original impedance detection signal, with its 5th pin connected to the first RC circuit to receive the original impedance detection signal; its 1st pin receives signal control from the FPGA through the fifth resistor (R5), thereby controlling the route selection inside the multiplexer (U2). Its 8th pin serves as the signal output terminal. It is connected to the inverting input terminal of the third operational amplifier (U3) through the fourth resistor (R4) to transmit the pre-processed impedance detection signal to the third operational amplifier (U3). The first resistor (R1) and the second capacitor (C2) are connected in parallel between the inverting input terminal and the output terminal of the third operational amplifier (U3). The first resistor (R1) plays the role of adjusting the amplification factor and, together with the second capacitor (C2), forms a low-pass filter and phase compensation.

2. The high-frequency electrosurgical negative plate impedance detection circuit according to claim 1, characterized in that: The 16th pin of the multiplexer (U2) is grounded through the sixth resistor (R6); the 2nd pin is connected to VCC_4 through the eighth resistor (R8). This pin is the enable pin and is set to normally open.

3. The high-frequency electrosurgical negative plate impedance detection circuit according to claim 1, characterized in that: The first RC circuit consists of a capacitor (C6) and a resistor (R7) connected to the output terminal of the first driver chip (U1).

4. The high-frequency electrosurgical unit negative electrode impedance detection circuit according to claim 1, characterized in that: The first driver chip (U1) has its non-inverting input terminal connected to VCC_1, and has a third capacitor (C3) and a fourth capacitor (C4) connected in parallel as a bypass to filter VCC_1.

5. The high-frequency electrosurgical negative plate impedance detection circuit according to claim 1, characterized in that: The first driver chip (U1) is the MC33152DR2G model from ON Semiconductor.

6. The high-frequency electrosurgical negative plate impedance detection circuit according to claim 1, characterized in that: The output of the third operational amplifier (U3) is connected to the non-inverting input of the fourth operational amplifier (U4) through the eleventh resistor (R11) and the twelfth resistor (R12). The non-inverting input of the fourth operational amplifier (U4) is grounded through the eleventh capacitor (C11), and its inverting input is shorted to the output.

7. The high-frequency electrosurgical negative plate impedance detection circuit according to claim 6, characterized in that: The ninth capacitor (C9) is connected between the output of the fourth operational amplifier (U4) and the connection point of the eleventh resistor (R11) and the twelfth resistor (R12).

8. The high-frequency electrosurgical negative plate impedance detection circuit according to claim 7, characterized in that: The output of the fourth operational amplifier (U4) is connected to the inverting input of the fifth operational amplifier (U5) through the tenth resistor (R10). One end of the ninth resistor (R9) and the tenth capacitor (C10) are connected to the inverting input of the fifth operational amplifier (U5), and the other end is connected to the negative terminal of the diode (D1). The non-inverting input of the fifth operational amplifier (U5) is grounded.

9. The high-frequency electrosurgical negative plate impedance detection circuit according to claim 8, characterized in that: The output terminal of the fifth operational amplifier (U5) is connected to the non-inverting input terminal of the sixth operational amplifier (U6) through the diode (D1), the thirteenth resistor (R13) and the fourteenth resistor (R14). The inverting input terminal of the sixth operational amplifier (U6) is grounded through the seventeenth resistor (R17), and its output terminal is connected to the inverting input terminal through the sixteenth resistor (R16).

10. The high-frequency electrosurgical negative plate impedance detection circuit according to claim 9, characterized in that: The output of the sixth operational amplifier (U6) is RC filtered by the fifteenth resistor (R15) and the thirteenth capacitor (C13) and then output as an AD acquisition to convert the analog signal into a digital signal.

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