Electrostatic discharge test circuit, system for chip, battery management system

Abstract

This application relates to chip testing technology and discloses a chip electrostatic discharge (ESD) test circuit, system, and battery management system. The test circuit includes: a battery configured to be connected to the positive and negative power terminals of the chip under test (DUT); a switch module with its control terminal connected to the control signal output terminal of the DUT; and a status indicator module configured to connect the battery and the switch module to form a loop. The switch module controls the circuit's on / off state based on the control signal from the DUT's control signal output terminal during ESD testing. The status indicator module indicates the operating state of the DUT, including normal operation and abnormal states entered by the DUT due to ESD testing. By monitoring the DUT's state during testing using the status indicator module, a more comprehensive evaluation of the DUT can be achieved.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to an electrostatic discharge testing circuit, system, and battery management system for a chip. Background Technology

[0002] Chips are increasingly used in modern electronic devices, ranging from consumer electronics to industrial control systems, covering almost all electronic fields. Electrostatic discharge (ESD) poses a significant threat during chip manufacturing, transportation, storage, and actual use, potentially leading to performance degradation or even complete destruction of the chip. Therefore, ESD testing has become an indispensable and critical step in the chip design and verification process.

[0003] However, existing testing methods cannot directly detect whether a chip is in a temporary shutdown state during ESD testing, making it difficult to comprehensively assess the chip's actual electrostatic discharge protection performance. Furthermore, the transient functional interruption caused by the shutdown state may lead to unforeseen consequences, further impacting the chip's reliability and safety. Utility Model Content

[0004] In view of this, embodiments of this application provide an electrostatic discharge test circuit, system, and battery management system for a chip, which can effectively solve the problem of difficulty in comprehensively evaluating the actual electrostatic discharge protection performance of the chip during ESD testing.

[0005] In a first aspect, embodiments of this application provide an electrostatic discharge test circuit for a chip, comprising: The battery is configured to be connected to the positive and negative power terminals of the chip under test; A switching module, wherein the control terminal of the switching module is configured to be connected to the control signal output terminal of the chip under test; A status indicator module is configured to connect the battery and the switch module to form a loop; The switching module is used to control the circuit to be turned on or off according to the control signal at the control signal output terminal of the chip under test during the electrostatic discharge test of the chip under test; The status indication module is used to indicate the working status of the chip under test, including normal operation status and abnormal status that the chip under test enters due to electrostatic discharge testing.

[0006] In some embodiments, the switching module includes a switching transistor, a first signal terminal of the switching transistor is connected to a second signal terminal of the status indication module, the second signal terminal of the switching transistor is connected to the negative terminal of the battery, and the control terminal of the switching transistor is connected to the control signal output terminal of the chip under test.

[0007] In some embodiments, the status indication module is configured to output a first indication signal when the circuit is in a conducting state, the first indication signal indicating that the working state of the chip under test is the normal operating state; and to output a second indication signal when the circuit is in a disconnected state, the second indication signal indicating that the working state of the chip under test is the abnormal state.

[0008] In some embodiments, the chip under test includes a battery management chip, and the control signal output terminal of the chip under test is the discharge control pin of the battery management chip.

[0009] In some embodiments, the switching module includes a discharge switch transistor, a first signal terminal of which is connected to a second signal terminal of the status indicator module, a second signal terminal of which is connected to the negative terminal of the battery, and a control terminal of which is connected to the discharge control pin of the battery management chip.

[0010] In some embodiments, the battery management chip further includes a voltage monitoring pin, which is connected to a connection node between the status indication module and the switch module.

[0011] In some embodiments, the status indication module includes: a light-emitting diode, the positive terminal of which is connected to the positive terminal of the battery, and the negative terminal of which is connected to the first signal terminal of the switching module.

[0012] Secondly, embodiments of this application provide an electrostatic discharge (ESD) testing system for a chip. The system includes: an electrostatic generation device and an ESD testing circuit for at least one chip as described in the first aspect above. The ESD testing circuit is used to connect to the chip under test, and the electrostatic generation device is used to provide an electrostatic signal to the chip under test.

[0013] Thirdly, embodiments of this application provide a battery management system, which includes a protection board. The protection board is provided with a battery management chip, a discharge switch, and a status indicator module. The positive and negative terminals of the power supply of the battery management chip are used to connect to the battery. The discharge control pin of the battery management chip is connected to the control terminal of the discharge switch transistor; The battery, the status indicator module, and the discharge switch are connected in series to form a loop, and the voltage monitoring pin of the battery management chip is connected to the connection node between the status indicator module and the discharge switch. The discharge switch is used to control the circuit to be turned on or off according to the control signal output terminal of the battery management chip during the electrostatic discharge test of the battery management chip. The status indication module is used to indicate the working status of the battery management chip, including normal operation and abnormal status that the battery management chip enters due to electrostatic discharge testing.

[0014] In some embodiments, the protection board is further provided with a charging switch transistor, and the charging control pin of the battery management chip is also connected to the control terminal of the charging switch transistor. The battery, the status indicator module, the charging switch transistor and the discharging switch transistor are connected in series to form the circuit. The voltage monitoring pin of the battery management chip is connected to the connection node between the status indication module and the charging switch.

[0015] The embodiments of this application have the following beneficial effects: The electrostatic discharge (ESD) test circuit for the chip in this application includes: a battery configured to be connected to the positive and negative power terminals of the chip under test (DUT); a switch module, the control terminal of which is configured to be connected to the control signal output terminal of the DUT; and a status indicator module configured to connect the battery and the switch module to form a loop. The switch module controls the circuit's on / off state according to the control signal from the control signal output terminal of the DUT during ESD testing. The status indicator module indicates the operating state of the DUT, including normal operation and abnormal states entered by the DUT due to ESD testing. This application utilizes the status indicator module to monitor the state of the DUT during ESD testing. The status indicator module provides corresponding indications based on the DUT's operating state. When the DUT is operating normally, the status indicator module indicates that the DUT is in normal operation; when the DUT malfunctions during testing, the status indicator module switches states, indicating that the DUT has entered an abnormal state due to ESD testing. This allows for a more comprehensive evaluation of the DUT, significantly improving chip reliability and safety. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This paper shows a first structural schematic diagram of the electrostatic discharge test circuit of the chip according to an embodiment of the present application; Figure 2 A circuit diagram of the electrostatic discharge test circuit of the chip according to an embodiment of this application is shown; Figure 3 A circuit diagram of the battery management system of the chip according to an embodiment of this application is shown.

[0018] Explanation of key component symbols: 11: Battery; 12: Switch module; 13: Status indicator module; 14: Chip under test. Detailed Implementation

[0019] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0020] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] In the following text, the terms "comprising," "having," and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more combinations thereof. Furthermore, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0022] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0023] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0024] Electrostatic discharge (ESD) testing of chips is a crucial step in ensuring that they can withstand electrostatic shocks in real-world environments without damage or malfunction. Static electricity can be generated by the human body, machinery, or other charged objects and conducted to electronic components through contact, potentially causing permanent damage to the chip's internal structure or temporary malfunction. An ESD generator can apply positive and negative electrostatic pulses to different pins of the chip, and the chip's condition can be used to determine whether it meets the ESD protection level, thereby improving chip reliability.

[0025] However, existing testing methods cannot directly detect whether a chip is in a temporary disconnected state during ESD testing, making it difficult to comprehensively assess the chip's actual electrostatic discharge protection performance and potentially affecting the chip's reliability and safety. This application provides an electrostatic discharge testing circuit, system, and battery management system for a chip. This application utilizes a status indication module to monitor the state of the chip under test during electrostatic discharge testing. The status indication module provides corresponding indications based on the chip's operating state. When the chip under test is normal, the status indication module indicates that the chip is in normal operating condition; when the chip under test malfunctions during testing, the status indication module switches states, indicating that the chip has entered an abnormal state due to electrostatic discharge testing. This allows for a more comprehensive evaluation of the chip under test, significantly improving its reliability and safety.

[0026] It is understood that the embodiments of this application do not specifically limit the model, function, and application scenario of the chip under test. The chip under test in the embodiments of this application can be any kind of chip. For example, the chip under test in this application can be a microcontroller chip; the chip under test in this application can also be a communication chip; the chip under test in this application can also be a power management chip; the chip under test in this application can also be a sensor chip for detecting various physical quantities such as temperature, humidity, and pressure; the chip under test in this application can also be a memory chip; the chip under test in this application can also be a display driver chip; the chip under test in this application can also be an audio processing chip, etc.

[0027] Understandably, electrostatic pulses can be applied to different pins of the chip depending on the actual application. Electrostatic pulses can be applied to all pins of the chip, or only to the positive and negative power supply pins. Different discharge methods can be selected according to the actual application; electrostatic pulses can be applied to the chip pins through air discharge or through contact discharge. This application does not limit the scope of the embodiments.

[0028] The electrostatic discharge test circuit for the chip under test will be described below with reference to some specific embodiments.

[0029] Exemplary, Figure 1 A first structural schematic diagram of an electrostatic discharge (ESD) test circuit for a chip according to an embodiment of this application is shown. Exemplarily, the ESD test circuit includes a battery 11, a switch module 12, and a status indicator module 13. The battery 11 is connected to the positive and negative power supply terminals of the chip under test (DUT) 14, and the control terminal of the switch module 12 is connected to the control signal output terminal of the DUT 14. The status indicator module 13 connects the battery 11 and the switch module 12 to form a closed-loop circuit.

[0030] Specifically, the positive terminal of battery 11 is connected to the positive power terminal of the chip under test 14, the negative terminal of battery 11 is connected to the negative power terminal of the chip under test 14, the positive terminal of battery 11 is also connected to the first signal terminal of status indicator module 13, the second signal terminal of status indicator module 13 is connected to the first signal terminal of switch module 12, the second signal terminal of switch module 12 is connected to the negative terminal of battery 11, and the control terminal of switch module 12 is connected to the control signal output terminal of chip under test 14.

[0031] It is understood that the embodiments of this application only show the modules required for electrostatic discharge testing of the chip under test 14 and the connection methods between the modules. In some scenarios, the connection can be made according to the typical application circuit of the chip under test 14. Optionally, in actual applications, the electrostatic discharge test circuit can be adjusted according to the actual application circuit of the chip under test 14 to avoid the electrostatic discharge results of the chip under test 14 being affected by different connection methods of the corresponding pins in the chip not conforming to the actual application scenario.

[0032] The status indication module 13 is used to indicate the operating status of the chip under test (DUT) 14. Specifically, the operating status includes a normal operating status and an abnormal status that the DUT 14 enters due to electrostatic discharge (ESD) testing. Exemplarily, the ESD test circuit of this embodiment is used to connect the DUT 14, and an ESD pulse is applied to the DUT 14 using an ESD generation device. If the DUT 14 is operating normally, the status indication module 13 indicates that the DUT 14 is in a normal operating status. If the status of the status indication module 13 switches, it indicates that the DUT 14 has entered an abnormal status and is temporarily shut down. By setting the status indication module 13, the response characteristics of the DUT 14 when subjected to ESD shock can be accurately evaluated, the anti-static performance of the DUT 14 can be comprehensively evaluated, and the reliability of the DUT 14 can be ensured. Furthermore, by directly observing the status switching, the reliability and accuracy of the test results are enhanced.

[0033] Understandably, the control logic of the chip under test 14 to the loop can be set according to the actual application. It can be set so that when the chip under test 14 is normal, the control loop is turned on and the first state of the status indicator module 13 is the normal operation state. When the chip under test 14 is abnormal, the control loop is turned off and the status indicator module 13 switches to the second state, which is the abnormal state. Alternatively, it can be set so that when the chip under test 14 is normal, the control loop is turned off and the second state of the status indicator module 13 is the normal operation state. When the chip under test 14 is abnormal, the control loop is turned on and the status indicator module 13 switches to the first state, which is the abnormal state.

[0034] The switch module 12 is used to control the conduction or disconnection of the circuit during the electrostatic discharge test (ESD) of the chip under test (DUT) 14, based on the control signal output terminal of the DUT 14. The control signal output terminal of the DUT 14 can be any output control pin of the DUT 14, and can be set according to the actual application. Understandably, the output of the output control pin should conform to the high and low level control of the switch module 12. If the DUT 14 is normal, the circuit is in a conducting state, and the output control pin should output the conduction signal of the switch module 12 when the DUT 14 is normal; if the DUT 14 is abnormal, it should output the disconnection signal of the switch module 12. By directly driving the switch module 12 through the output control pin of the DUT 14, and thus controlling the conduction or disconnection of the circuit of the status indication module 13, the working status of the DUT 14 during the ESD test can be reflected in real time and intuitively. This avoids the possible misjudgments that may occur with indirect detection methods, ensuring the reliability of the test results. Furthermore, status monitoring can be completed only through the chip's own pins, simplifying the design complexity of the test circuit and reducing hardware costs and system power consumption.

[0035] Furthermore, the switch module 12 can be configured to be turned on when a high-level signal is active and turned off when a low-level signal is active; alternatively, the switch module 12 can be configured to be turned off when a high-level signal is active and turned on when a low-level signal is active. If the switch module 12 is configured to be turned on when a high-level signal is active and turned off when a low-level signal is active, the output control pin should output a high-level signal when the chip under test 14 is functioning normally and a low-level signal when the chip under test 14 is malfunctioning.

[0036] Understandably, the switch module 12 can be configured as any type of switch element, such as a switching transistor. The chip under test (DUT) 14 controls the conduction or cutoff of the circuit by controlling the switching transistor to turn on or off. Specifically, when the DUT 14 outputs a conduction signal to the control terminal of the switching transistor, the switching transistor is turned on, and the circuit is turned on. When the DUT 14 outputs a cutoff signal to the control terminal of the switching transistor, the switching transistor is turned off, and the circuit is turned off.

[0037] The switch module 12 can also be configured as a relay, with the chip under test 14 controlling the conduction or cutoff of the control circuit by controlling the relay to turn on or off. Alternatively, the switch module 12 can be configured as an optocoupler, with the chip under test 14 controlling the conduction or cutoff of the control circuit by controlling the optocoupler to turn on or off. Furthermore, the switch module 12 can be composed of multiple switching elements, with the chip under test 14 controlling the conduction or cutoff of the control circuit by controlling the switching elements in the switch module 12 to turn on and off sequentially.

[0038] Exemplarily, the switching module 12 includes a switching transistor. The first signal terminal of the switching transistor is connected to the second signal terminal of the status indication module 13, the second signal terminal of the switching transistor is connected to the negative terminal of the battery 11, and the control terminal of the switching transistor is connected to the control signal output terminal of the chip under test 14. It is understood that the switching transistor can be a field-effect transistor, a MOSFET, a transistor, a thyristor, etc. By configuring the switching module 12 as a switching transistor, the switching transistor has a fast response capability. When the output control pin of the chip under test 14 sends a signal, the switching transistor can respond quickly, thereby accurately controlling the operating state of the circuit where the status indication module 13 is located. This ensures real-time monitoring of abnormal chip states and avoids data loss or misjudgment due to delays. Furthermore, the switching transistor has low power consumption characteristics in both the on and off states, which can significantly reduce the energy consumption of the entire test circuit.

[0039] Understandably, the status indicator module 13 can be set as an audio-visual indicator, a light indicator, or a sound indicator, etc. The light indicator can be implemented using a light-emitting diode, and the sound indicator can be implemented using a buzzer, etc.

[0040] Exemplarily, the status indication module 13 includes a light-emitting diode (LED), with its positive terminal connected to the positive terminal of the battery 11 and its negative terminal connected to the first signal terminal of the switch module 12. By configuring the status indication module 13 as an LED, the LED can visually reflect the operating status of the chip under test (DUT) 14 through changes in its on / off state. For example, when the switch module 12 is turned on, the LED lights up, indicating that the DUT 14 is in a normal operating state; when the switch module 12 is turned off, the LED turns off, indicating that the DUT 14 is in an abnormal state. This simple visual signal allows testers to quickly determine whether the chip is in a normal or abnormal state.

[0041] As an alternative solution, Figure 2 The diagram shows a schematic of an electrostatic discharge (ESD) test circuit. In this embodiment, a battery management chip U1 is used as the chip under test (DUT) 14, and the status indicator module 13 is a light-emitting diode (LED) D1. The two ends of the battery 11 are connected to the positive power terminal VDD and the negative power terminal VSS of the battery management chip U1, respectively. The control signal output terminals of the battery management chip U1 include a discharge control pin DO and a charging control pin, etc. Exemplarily, the control signal output terminal of the DUT 14 is the discharge control pin DO of the battery management chip U1. A discharge switch Q1 is used as a switch module 12. The first signal terminal of the discharge switch Q1 is connected to the second signal terminal of the status indicator module 13, the second signal terminal of the discharge switch Q1 is connected to the negative terminal of the battery 11, and the control terminal of the discharge switch Q1 is connected to the discharge control pin DO of the battery management chip U1.

[0042] When the chip under test 14 is the battery management chip U1, the discharge switch Q1 is used as the switch module 12, which can directly reflect the control performance of the battery management chip U1 in electrostatic discharge testing; it can also significantly simplify the design and implementation process of the test circuit, reduce hardware costs and development difficulty, and reduce the risk of interference or failure caused by the addition of components; at the same time, it makes the design of the test circuit more in line with the actual working scenario of the battery management chip U1, and enhances the reference value of the test results.

[0043] The pins of the battery management chip U1 can be connected appropriately according to the actual application of the chip to conform to its typical application circuit. For example, the battery management chip U1 also includes a voltage monitoring pin VM, which connects to the connection node between the status indicator module 13 and the switch module 12. By connecting the pins of the battery management chip U1 according to the typical application circuit, its operating environment in actual applications can be reproduced to the greatest extent possible, effectively avoiding misjudgments or abnormal behaviors caused by unreasonable circuit configurations. This ensures that the test results have higher reference value, thereby helping developers to more comprehensively evaluate chip performance. Furthermore, the battery management chip U1 can also be equipped with a current monitoring pin VINI, which monitors the current in the circuit by connecting to the circuit.

[0044] This application embodiment also provides a chip electrostatic discharge testing system. The electrostatic discharge testing system includes an electrostatic generation device and the electrostatic discharge testing circuit described above. The electrostatic discharge testing circuit is used to connect to the chip under test 14, and the electrostatic generation device is used to provide an electrostatic signal to the chip under test 14.

[0045] Understandably, the electrostatic discharge (ESD) generating device can be any type of device, such as an ESD simulator or generator, to produce electrostatic pulses that conform to specific standards. Alternatively, the ESD generating device can also be an ESD gun, etc.

[0046] Furthermore, the system also includes a photoelectric detection device used to detect the state of the photoelectric conversion module. Utilizing the photoelectric detection device to acquire changes in the state of the light-emitting diode improves testing efficiency and accuracy.

[0047] like Figure 3 As shown in the illustration, this application embodiment also provides a battery management system. The battery management system includes a protection board, on which a battery management chip U1, a discharge switch Q1, and a status indicator module 13 are disposed. The positive and negative terminals of the power supply of the battery management chip U1 are used to connect to the battery 11. The discharge control pin DO of the battery management chip U1 is connected to the control terminal of the discharge switch Q1. The battery 11, the status indicator module 13, and the discharge switch Q1 are connected in series to form a loop. The voltage monitoring pin VM of the battery management chip U1 is connected to the connection node between the status indicator module 13 and the discharge switch Q1. Further, a charging switch Q2 is also disposed on the protection board. The charging control pin CO of the battery management chip U1 is connected to the control terminal of the charging switch Q2. The battery 11, the status indicator module 13, the charging switch Q2, and the discharge switch Q1 are connected in series to form a loop. The voltage monitoring pin VM of the battery management chip U1 is connected to the connection node between the status indicator module 13 and the charging switch Q2.

[0048] Specifically, the battery management system operates as follows: When an external power source is connected and charging begins, the charging switch Q2 is turned on under the control of the battery management chip U1, allowing current to flow into the battery 11. When the load requires power, the discharging switch Q1 is turned on under the control of the battery management chip U1, enabling the battery 11 to supply power to the load. During charging or discharging, the battery management chip U1 monitors the voltage through the voltage monitoring pin VM. This embodiment adds a status indication module 13 to the battery management system. The status indication module 13 indicates the operating status of the battery management chip U1, including normal operation and abnormal states entered by the battery management chip U1 due to electrostatic discharge testing. In this embodiment, the discharging switch Q1 controls the conduction or disconnection of the circuit according to the control signal output of the battery management chip U1 during electrostatic discharge testing, thereby enabling a more comprehensive electrostatic discharge test of the battery management chip U1. Through the status indication module 13, the operating status of the battery management chip U1 during electrostatic discharge testing can be reflected in real time, providing a more comprehensive assessment of the reliability and stability of the battery management chip U1 in the electrostatic discharge environment. This also improves testing efficiency and reduces reliance on additional monitoring equipment.

[0049] Exemplarily, the status indication module 13 includes a light-emitting diode (LED) D1. The positive terminal of LED D1 is connected to the positive terminal of the battery 11, and the negative terminal of LED D1 is connected to the voltage monitoring pin VM of the battery management chip U1. Exemplarily, LED D1 being lit indicates that the battery management chip U1 is in normal operation; LED D1 being off indicates that the battery management chip U1 is in an abnormal state. By configuring the status indication module 13 with LED D1, the LED D1 can intuitively reflect the operating status of the chip under test 14 through changes in its lit or off state. The status indication module 13 presents test results in a simple and intuitive way, facilitating quick understanding by testers. It reduces the requirement for professional testing knowledge and is suitable for users with various technical levels.

[0050] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, in alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0051] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0052] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.

[0053] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. An electrostatic discharge test circuit for a chip, characterized in that, include: The battery is configured to be connected to the positive and negative power terminals of the chip under test; A switching module, wherein the control terminal of the switching module is configured to be connected to the control signal output terminal of the chip under test; A status indicator module is configured to connect the battery and the switch module to form a loop; The switching module is used to control the circuit to be turned on or off according to the control signal at the control signal output terminal of the chip under test during the electrostatic discharge test of the chip under test; The status indication module is used to indicate the working status of the chip under test, including normal operation status and abnormal status that the chip under test enters due to electrostatic discharge testing.

2. The electrostatic discharge test circuit of a chip according to claim 1, wherein, The switching module includes a switching transistor. The first signal terminal of the switching transistor is connected to the second signal terminal of the status indicator module. The second signal terminal of the switching transistor is connected to the negative terminal of the battery. The control terminal of the switching transistor is connected to the control signal output terminal of the chip under test.

3. The electrostatic discharge test circuit of a chip according to claim 1, wherein, The status indication module is used to output a first indication signal when the circuit is in the on state, the first indication signal being used to indicate that the working state of the chip under test is the normal operating state; and to output a second indication signal when the circuit is in the off state, the second indication signal being used to indicate that the working state of the chip under test is the abnormal state.

4. The electrostatic discharge test circuit of a chip according to claim 1, wherein, The chip under test includes a battery management chip, and the control signal output terminal of the chip under test is the discharge control pin of the battery management chip.

5. The electrostatic discharge test circuit of a chip according to claim 4, wherein, The switching module includes a discharge switch transistor. The first signal terminal of the discharge switch transistor is connected to the second signal terminal of the status indicator module. The second signal terminal of the discharge switch transistor is connected to the negative terminal of the battery. The control terminal of the discharge switch transistor is connected to the discharge control pin of the battery management chip.

6. The electrostatic discharge test circuit of a chip according to claim 4, wherein The battery management chip also includes a voltage monitoring pin, which is connected to the connection node between the status indication module and the switch module.

7. The electrostatic discharge test circuit of a chip according to claim 1, wherein The status indication module includes a light-emitting diode (LED), the positive terminal of which is connected to the positive terminal of the battery, and the negative terminal of which is connected to the first signal terminal of the switching module.

8. An electrostatic discharge test system for a chip, characterized by, The system includes: an electrostatic generation device and an electrostatic discharge test circuit for a chip as described in any one of claims 1-7, wherein the electrostatic discharge test circuit is used to connect to the chip under test, and the electrostatic generation device is used to provide an electrostatic signal to the chip under test.

9. A battery management system, characterized by, The battery management system includes: a protection board, on which a battery management chip, a discharge switch, and a status indicator module are provided; the positive and negative terminals of the power supply of the battery management chip are used to connect to the battery. The discharge control pin of the battery management chip is connected to the control terminal of the discharge switch transistor; The battery, the status indicator module, and the discharge switch are connected in series to form a loop, and the voltage monitoring pin of the battery management chip is connected to the connection node between the status indicator module and the discharge switch. The discharge switch is used to control the circuit to be turned on or off according to the control signal output terminal of the battery management chip during the electrostatic discharge test of the battery management chip. The status indication module is used to indicate the working status of the battery management chip, including normal operation and abnormal status of the battery management chip due to electrostatic discharge testing.

10. The battery management system according to claim 9, characterized in that, The protection board is also provided with a charging switch transistor, and the charging control pin of the battery management chip is also connected to the control terminal of the charging switch transistor. The battery, the status indicator module, the charging switch transistor and the discharge switch transistor are connected in series to form the circuit. The voltage monitoring pin of the battery management chip is connected to the connection node between the status indication module and the charging switch.

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