A circuit for detecting sticking of an inverter n-line relay

Abstract

The utility model discloses a kind of detection inverter N line relay sticking circuit, specific implementation scheme is: to be measured circuit, detection circuit, sampling circuit and for receiving the RLY signal of main control chip's relay drive circuit, the INV_N port of to be measured circuit is electrically connected with the Bus_M port of detection circuit, the RLY_GND port in the relay drive circuit is electrically connected with relay coil ground terminal in detection circuit, relay coil power supply end connects power supply, the sampling circuit is electrically connected with the to be measured circuit.The utility model changes the resistance of N to PE by controlling switch on-off to adjust the voltage value of inverter side N to PE, make A phase relay all attract, when N phase relay is not attracted, there is difference between grid side AN voltage and inverter side AN voltage, whether there is difference between grid A phase voltage and inverter side A phase voltage is judged to determine whether N phase relay appears sticking, solve the technical defects that traditional scheme cannot detect whether N phase relay sticks.

Description

Technical Field

[0001] This utility model relates to the field of circuit technology, and in particular to a circuit for detecting the sticking of the neutral (N) line relay of an inverter. Background Technology

[0002] A three-phase four-wire relay switch topology is as follows: Figure 1 As shown, it mainly consists of a first relay, a second relay, a third relay, a fourth relay, a fifth relay, a sixth relay, a seventh relay, and an eighth relay. Relays one, three, five, and seven are located on the grid side, while relays two, four, six, and eight are located on the inverter side. Its self-testing method is as follows: A trigger drive signal is given, causing relays one, two, three, and six to engage. At this time, phase A is fully conductive, while only a single relay in phases B and C is conductive. The voltages of phases AN, BN, and CN on the inverter side are then checked. If voltage is detected between AN and CN, it indicates that the relays in phase A are engaged normally. If voltage is detected between BN and CN, it indicates that the fourth relay is stuck. If voltage is detected between CN, it indicates that the fifth relay is stuck. A trigger drive signal is activated, causing the first, fourth, fifth, and sixth relays to engage. At this point, phase C is fully conducting, while only a single relay in phases A and B is conducting. The voltages of phases AN, BN, and CN on the inverter side are monitored. If voltage is detected between CN, it indicates that the phase C relay is engaged normally. If voltage is detected between BN, it indicates that the third relay is stuck. If voltage is detected between AN, it indicates that the second relay is stuck. A trigger drive signal is activated, causing the second, third, fourth, and fifth relays to engage. At this point, phase B is fully conducting, while only a single relay in phases A and C is conducting. The voltages of phases AN, BN, and CN on the inverter side are monitored. If voltage is detected between BN, it indicates that the phase B relay is engaged normally. If voltage is detected between AN, it indicates that the first relay is stuck. If voltage is detected between CN, it indicates that the sixth relay is stuck. Simultaneously, the drive signal is triggered, causing all six relays to engage. The voltage between AN, BN, and CN on the inverter side is detected and compared with the voltage on the grid side. If there is a significant difference, it indicates that the corresponding relay is damaged, and a relay self-test fault is reported in a timely manner.

[0003] Under normal operating conditions, since the N-phase potential on the inverter side and the N-phase potential on the grid side are basically the same, the above-mentioned relay self-test scheme cannot determine whether the two relays corresponding to the N line are stuck together in actual application. Utility Model Content

[0004] Based on this, in order to solve the problem that existing relay self-testing schemes cannot determine whether the two relays corresponding to the N line are stuck together in practical applications, this utility model provides a circuit for detecting the sticking of the N line relays of an inverter.

[0005] This utility model provides a circuit for detecting the sticking of the neutral (N) line relay in an inverter, comprising:

[0006] The circuit under test (DUT), the detection circuit, the sampling circuit, and the relay drive circuit for receiving the RLY signal from the main control chip are included. The INV_N port of the DUT is electrically connected to the Bus_M port of the detection circuit. The RLY_GND port of the relay drive circuit is electrically connected to the ground terminal of the relay coil in the detection circuit. The power supply terminal of the relay coil is connected to a power supply. The sampling circuit is electrically connected to the DUT.

[0007] The detection circuit includes a first resistor, a second resistor, a third resistor, a fifth relay, a first capacitor, and a second capacitor. The first capacitor and the second capacitor are connected in series. The end of the first capacitor away from the second capacitor is electrically connected to the Bus_P port. The end of the second capacitor away from the first capacitor is electrically connected to the Bus_N port. The Bus_M port is located at the connection end of the first capacitor and the second capacitor. The second resistor and the third resistor are connected in series and then in parallel with the first capacitor and the second capacitor. The first resistor and the fifth relay are connected in series and then in parallel with the third resistor.

[0008] The circuit under test includes a first relay, a second relay, a third relay, and a fourth relay. The first relay and the third relay are located on the grid side, the second relay and the fourth relay are located on the inverter side, the first relay and the second relay are connected in series between Grid_A and Inv_A, and the third relay and the fourth relay are connected in series between Grid_N and Inv_N.

[0009] The sampling circuit includes a first resistor string, a second resistor string, a fifteenth resistor, a sixteenth resistor, a fifth capacitor, and an operational amplifier. The first resistor string is connected to the inverting input terminal of the operational amplifier, the second resistor string is connected to the non-inverting input terminal of the operational amplifier, one end of the fifth capacitor is electrically connected to the inverting input terminal of the operational amplifier, and the other end of the fifth capacitor is electrically connected to the output terminal of the operational amplifier. The fifteenth resistor is connected in parallel with the fifth capacitor, and the output terminal of the operational amplifier is also electrically connected to the sixteenth resistor.

[0010] The sampling circuit also includes a fourth capacitor and a fourteenth resistor. The +1.5V voltage is electrically connected to the non-inverting input terminal of the operational amplifier through the fourteenth resistor, and the fourth capacitor is connected in parallel with the fourteenth resistor.

[0011] The positive power supply pin of the operational amplifier is connected to +12V, and the negative power supply pin of the operational amplifier is connected to -12V.

[0012] The sampling circuit includes a first sampling circuit and a second sampling circuit. The non-inverting input of the first sampling circuit is electrically connected to the Grid_A port of the circuit under test, and the inverting input of the first sampling circuit is electrically connected to the Grid_N port of the circuit under test. The non-inverting input of the second sampling circuit is electrically connected to the INV_A port of the circuit under test, and the inverting input of the second sampling circuit is electrically connected to the INV_N port of the circuit under test.

[0013] The relay driving circuit includes a fourth resistor, a fifth resistor, a third capacitor, and a MOSFET. The collector of the MOSFET is electrically connected to the RLY_GND port, and the emitter of the MOSFET is grounded. One end of the third capacitor is electrically connected to the base of the MOSFET, and the other end of the third capacitor is electrically connected to the emitter of the MOSFET. The fifth resistor is connected in parallel with the third capacitor, and the base of the MOSFET is also electrically connected to the RLY signal through the fourth resistor.

[0014] Beneficial effects: This utility model adjusts the voltage value from N to PE on the inverter side by changing the resistance from N to PE through the on / off switching of the switch, so that all A-phase relays are energized. When the N-phase relays are not energized, there is a difference between the AN voltage on the grid side and the AN voltage on the inverter side. By collecting the difference between the A-phase voltage on the grid and the A-phase voltage on the inverter side, it is determined whether the N-phase relays are stuck together, thus solving the technical defect of traditional solutions that cannot detect whether the N-phase relays are stuck together.

[0015] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0016] The accompanying drawings are provided for a better understanding of this solution and do not constitute a limitation on this utility model. Wherein:

[0017] Figure 1 It is based on the three-phase four-wire topology diagram provided by this utility model;

[0018] Figure 2 This is based on the relay drive circuit diagram provided by this utility model;

[0019] Figure 3 This is a topology diagram of the solution provided by this utility model;

[0020] Figure 4 The circuit diagram provided in this utility model is used;

[0021] Figure 5 It is based on the circuit diagram to be tested provided by this utility model;

[0022] Figure 6The detection circuit diagram provided by this utility model is as follows. Detailed Implementation

[0023] The following description, in conjunction with the accompanying drawings, illustrates exemplary embodiments of the present invention, including various details to aid understanding. These embodiments should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present invention. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0024] like Figure 3 As shown, this utility model provides a circuit for detecting the sticking of the N-line relay in an inverter, comprising:

[0025] The circuit under test (DUT), the detection circuit, the sampling circuit, and the relay drive circuit for receiving the RLY signal from the main control chip are included. The INV_N port of the DUT is electrically connected to the Bus_M port of the detection circuit. The RLY_GND port of the relay drive circuit is electrically connected to the ground terminal of the relay coil in the detection circuit. The power supply terminal of the relay coil is connected to a power supply. The sampling circuit is electrically connected to the DUT.

[0026] The RLY signal is connected to the GPIO port of the control chip.

[0027] The detection circuit diagram is as follows Figure 6 As shown, the circuit under test includes a first resistor R1, a second resistor R2, a third resistor R3, a fifth relay S1, a first capacitor Bus_C1, and a second capacitor Bus_C2. The first capacitor Bus_C1 and the second capacitor Bus_C2 are connected in series. The end of the first capacitor Bus_C1 away from the second capacitor Bus_C2 is electrically connected to the Bus_P port. The end of the second capacitor Bus_C2 away from the first capacitor Bus_C1 is electrically connected to the Bus_N port. The Bus_M port is located at the connection end of the first capacitor Bus_C1 and the second capacitor Bus_C2. The second resistor R2 and the third resistor R3 are connected in series and then in parallel with the first capacitor Bus_C1 and the second capacitor Bus_C2. The first resistor R1 and the fifth relay S1 are connected in series and then in parallel with the third resistor R3.

[0028] Where R2 = R3, Bus_P represents the positive terminal of the inverter bus, Bus_N represents the negative terminal of the inverter bus, and Bus_M represents the midpoint of the inverter bus.

[0029] The circuit under test, such as Figure 5As shown, the circuit under test includes a first relay, a second relay, a third relay, and a fourth relay. The first and third relays are located on the grid side, the second and fourth relays are located on the inverter side, the first and second relays are connected in series between Grid_A and Inv_A, and the third and fourth relays are connected in series between Grid_N and Inv_N.

[0030] Sampling circuit diagram as follows Figure 4 As shown, the sampling circuit includes a first resistor string, a second resistor string, a fifteenth resistor R15, a sixteenth resistor R16, a fifth capacitor, and an operational amplifier. The first resistor string is connected to the inverting input terminal of the operational amplifier, the second resistor string is connected to the non-inverting input terminal of the operational amplifier, one end of the fifth capacitor is electrically connected to the inverting input terminal of the operational amplifier, and the other end of the fifth capacitor is electrically connected to the output terminal of the operational amplifier. The fifteenth resistor R15 is connected in parallel with the fifth capacitor, and the output terminal of the operational amplifier is also electrically connected to the sixteenth resistor R16.

[0031] The sampling circuit also includes a fourth capacitor C4 and a fourteenth resistor R14. The +1.5V voltage is electrically connected to the non-inverting input terminal of the operational amplifier through the fourteenth resistor R14, and the fourth capacitor C4 is connected in parallel with the fourteenth resistor R14.

[0032] The positive power supply pin of the operational amplifier is connected to +12V, and the negative power supply pin of the operational amplifier is connected to -12V.

[0033] The sampling circuit includes a first sampling circuit and a second sampling circuit. The non-inverting input of the first sampling circuit is electrically connected to the Grid_A port of the circuit under test, and the inverting input of the first sampling circuit is electrically connected to the Grid_N port of the circuit under test. The non-inverting input of the second sampling circuit is electrically connected to the INV_A port of the circuit under test, and the inverting input of the second sampling circuit is electrically connected to the INV_N port of the circuit under test.

[0034] The relay drive circuit includes a fourth resistor R4, a fifth resistor R5, a third capacitor C3, and a MOSFET Q1. The collector of the MOSFET Q1 is electrically connected to the RLY_GND port, and the emitter of the MOSFET Q1 is grounded. One end of the third capacitor C3 is electrically connected to the base of the MOSFET Q1, and the other end of the third capacitor C3 is electrically connected to the emitter of the MOSFET Q1. The fifth resistor R5 is connected in parallel with the third capacitor C3. The base of the MOSFET Q1 is also electrically connected to the RLY signal through the fourth resistor R4.

[0035] Relay drive circuit such as Figure 2As shown, the first driving circuit drives the first and second relays, the second driving circuit drives the third relay, the third driving circuit drives the fourth relay, and the fourth driving circuit drives the fifth relay S1.

[0036] The detection principle is as follows:

[0037] When the inverter is in normal operation, in the circuit from Bus_P to Bus_M to Bus_N, Bus_M is the midpoint of the bus capacitor, so the voltage from Bus_M to Bus_N is... In the loop from Bus_P to PE to Bus_N, the voltage at point PE to Bus_N is... Therefore, the potential difference from PE to Bus_M is zero, and the potential difference from INV_N to PE is also zero. In industrial electrical systems, Grid_N has only a few ohms of resistance between itself and ground at the remote transformer, which can be considered negligible as a potential difference between Grid_N and PE. Therefore, when the N-line relay is open, the inverter-side N and the grid-side N have the same potential. This triggers the first drive circuit, energizing the first and second relays, connecting the A-phase inverter side and the grid side. The first sampling circuit detects the grid-side U... AN The second sampling circuit detects U on the inverter side. AN At this time, the sampling circuit detects the grid-side U AN Equal to the inverter-side U detected by the second sampling circuit AN The fourth drive circuit is triggered, energizing the fifth relay S1. At this time, the resistance between Bus_N and PE is R1 and R3 in parallel, and the voltage between Bus_M and Bus_N remains unchanged. The voltage from PE to N is equal to At this time, the potential difference between Bus_M and PE The second drive circuit is triggered, causing the third relay to engage and detecting the U-side grid. AN and inverter side U AN If the first sampling circuit detects the grid-side U AN The inverter-side U is greater than that detected by the second sampling circuit. AN The fourth relay is not stuck, releasing the second drive circuit, triggering the third drive circuit, causing the fourth relay to engage, and detecting the U on the grid side. AN and inverter side U AN If the first sampling circuit detects the grid-side U AN The inverter-side U is greater than that detected by the second sampling circuit. AN The third relay is not stuck, and vice versa.

[0038] This invention adjusts the voltage value from N to PE on the inverter side by controlling the on / off state of the relays to change the resistance from N to PE, so that all A-phase relays are engaged. When the N-phase relays are not engaged, there is a difference between the AN voltage on the grid side and the AN voltage on the inverter side. By collecting data on whether there is a difference between the A-phase voltage on the grid side and the A-phase voltage on the inverter side, it is determined whether the N-phase relays are stuck together, thus solving the technical defect of traditional solutions that cannot detect whether the N-phase relays are stuck together.

[0039] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any changes or substitutions within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the protection scope of the claims.

Claims

1. A circuit for detecting sticking of the neutral (N) line relay in an inverter, characterized in that, include: The circuit under test (DUT), the detection circuit, the sampling circuit, and the relay drive circuit for receiving the RLY signal from the main control chip are included. The INV_N port of the DUT is electrically connected to the Bus_M port of the detection circuit. The RLY_GND port of the relay drive circuit is electrically connected to the ground terminal of the relay coil in the detection circuit. The power supply terminal of the relay coil is connected to a power supply. The sampling circuit is electrically connected to the DUT.

2. The circuit for detecting the sticking of the inverter's neutral (N) line relay according to claim 1, characterized in that: The detection circuit includes a first resistor, a second resistor, a third resistor, a fifth relay, a first capacitor, and a second capacitor. The first capacitor and the second capacitor are connected in series. The end of the first capacitor away from the second capacitor is electrically connected to the Bus_P port. The end of the second capacitor away from the first capacitor is electrically connected to the Bus_N port. The Bus_M port is located at the connection end of the first capacitor and the second capacitor. The second resistor and the third resistor are connected in series and then in parallel with the first capacitor and the second capacitor. The first resistor and the fifth relay are connected in series and then in parallel with the third resistor.

3. The circuit for detecting the sticking of the inverter's neutral (N) line relay according to claim 2, characterized in that: The circuit under test includes a first relay, a second relay, a third relay, and a fourth relay. The first relay and the third relay are located on the grid side, the second relay and the fourth relay are located on the inverter side, the first relay and the second relay are connected in series between Grid_A and Inv_A, and the third relay and the fourth relay are connected in series between Grid_N and Inv_N.

4. The circuit for detecting the sticking of the inverter's neutral (N) line relay according to claim 3, characterized in that: The sampling circuit includes a first resistor string, a second resistor string, a fifteenth resistor, a sixteenth resistor, a fifth capacitor, and an operational amplifier. The first resistor string is connected to the inverting input terminal of the operational amplifier, the second resistor string is connected to the non-inverting input terminal of the operational amplifier, one end of the fifth capacitor is electrically connected to the inverting input terminal of the operational amplifier, and the other end of the fifth capacitor is electrically connected to the output terminal of the operational amplifier. The fifteenth resistor is connected in parallel with the fifth capacitor, and the output terminal of the operational amplifier is also electrically connected to the sixteenth resistor.

5. The circuit for detecting the sticking of the inverter's neutral (N) line relay according to claim 4, characterized in that: The sampling circuit also includes a fourth capacitor and a fourteenth resistor. The +1.5V voltage is electrically connected to the non-inverting input terminal of the operational amplifier through the fourteenth resistor, and the fourth capacitor is connected in parallel with the fourteenth resistor.

6. The circuit for detecting the sticking of the inverter's neutral (N) line relay according to claim 5, characterized in that: The positive power supply pin of the operational amplifier is connected to +12V, and the negative power supply pin of the operational amplifier is connected to -12V.

7. The circuit for detecting the sticking of the inverter's neutral (N) line relay according to claim 6, characterized in that: The sampling circuit includes a first sampling circuit and a second sampling circuit. The non-inverting input of the first sampling circuit is electrically connected to the Grid_A port of the circuit under test, and the inverting input of the first sampling circuit is electrically connected to the Grid_N port of the circuit under test. The non-inverting input of the second sampling circuit is electrically connected to the INV_A port of the circuit under test, and the inverting input of the second sampling circuit is electrically connected to the INV_N port of the circuit under test.

8. A circuit for detecting the sticking of the inverter's neutral (N) line relay according to claim 1 or 7, characterized in that: The relay driving circuit includes a fourth resistor, a fifth resistor, a third capacitor, and a MOSFET. The collector of the MOSFET is electrically connected to the RLY_GND port, and the emitter of the MOSFET is grounded. One end of the third capacitor is electrically connected to the base of the MOSFET, and the other end of the third capacitor is electrically connected to the emitter of the MOSFET. The fifth resistor is connected in parallel with the third capacitor, and the base of the MOSFET is also electrically connected to the RLY signal through the fourth resistor.

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