Silicon photonic package structure

Abstract

Some embodiments of the present application provide a silicon photonics packaging structure, comprising: a circuit layer, a bridge structure being disposed in the circuit layer; a first chip and a second chip being disposed on the circuit layer; an optical transceiver being disposed on the first chip and the second chip and transmitting light through the bridge structure; and an electrical transceiver being disposed on the first chip and the second chip and transmitting electricity through the bridge structure, wherein the bridge structure comprises a plurality of stacked graphene layers. The present application utilizes the characteristics of the graphene layers, which simultaneously have light transmittance, good electrical conductivity and heat dissipation capacity, to simultaneously serve as an optical / electrical channel, thereby replacing the original bridge structure with separated optical / electrical channels, and reducing stress and packaging thickness.

Description

Technical Field

[0001] The embodiments of this application relate to the semiconductor field, and more specifically, to silicon photonic packaging structures. Background Technology

[0002] Currently, the bridging structure of FOCoS (fan-out substrate on-board packaging) has separate optical / electrical transmission paths and uses different materials, resulting in higher overall costs. Furthermore, due to the different channel materials, mismatched CTE (coefficient of thermal expansion) or uneven thermal stress distribution can easily lead to splitting or delamination problems.

[0003] Specifically, see Figure 1 In electronic products, such as the FOCoS10 with bridge wiring 17 used to integrate multiple silicon photonic chips, the current solution is to use different optical channels and circuits separately. For example... Figure 1 As shown, in FOCoS10, multiple dielectric layers 15 and 16 are formed on substrate 14, and multiple chips 11 and 12 are integrated thereon. Optical transceiver devices 11A and 12A of chip 11 transmit light between each other through waveguides 13 in dielectric layer 15. Figure 1 The diagram illustrates the optical transmission path L, and chips 11 and 12 transmit electrical signals via their respective bump structures 11B and 12B, metal lines and vias 16V in dielectric layer 16, and bridge wiring 17. It is evident that in FOCoS10, the optical transmission path L and the electrical transmission path are separated and made of different materials, resulting in higher manufacturing costs. Furthermore, the FOCoS10 package structure is large and complex, making it prone to warping / cracking / delamination / deformation problems around bridge wiring 17 during heating or under load stress due to different channel materials, CTE mismatch, or uneven thermal stress distribution.

[0004] In summary, in FOCoS10, these problems, including warpage (W), cracking (C), delamination (D) and / or deformation, are caused by material CTE mismatch and thermal storage between the internal electrical and optical channels using metals (e.g., copper) and non-metals (e.g., organic materials). Therefore, it is necessary to address the corresponding material CTE mismatch. Utility Model Content

[0005] This application utilizes graphene to solve the above problems. Specifically, it utilizes the properties of graphene, which simultaneously possess light transmittance, good conductivity, and heat dissipation capabilities, to simultaneously serve as an optical / electrical channel, thereby replacing the original bridging structure that separates the optical / electrical channels, and simultaneously reducing stress and packaging thickness.

[0006] Some embodiments of this application provide a silicon photonic packaging structure, including: a circuit layer having a bridging structure therein; a first chip and a second chip disposed on the circuit layer; an optical transceiver disposed on the first chip and the second chip, and transmitting light through the bridging structure; and an electrical transceiver disposed on the first chip and the second chip, and transmitting electrical signals through the bridging structure, wherein the bridging structure includes a plurality of stacked graphene layers.

[0007] In some embodiments, the optical transceiver includes a transmitter and a receiver.

[0008] In some embodiments, the bridging structure further includes a metal layer for supporting the plurality of graphene layers.

[0009] In some embodiments, the electrical transceiver is electrically connected to the metal layer.

[0010] In some embodiments, the optical transceiver is directly connected to the graphene layer.

[0011] In some embodiments, the silicon photonic packaging structure further includes a packaging layer for packaging the first chip and the second chip.

[0012] In some embodiments, the portion of the encapsulation layer located between the first chip and the second chip has a surface recessed toward the graphene layer.

[0013] In some embodiments, a seed layer is disposed between the encapsulation layer and the graphene layer.

[0014] In some embodiments, the seed layer covers a portion of the graphene layer.

[0015] In some embodiments, the silicon photonic packaging structure further includes a solder resist layer disposed on the seed layer and the circuit layer.

[0016] In some embodiments, the encapsulation layer is a non-transparent, highly reflective material, wherein the encapsulation layer is in direct contact with the graphene layer.

[0017] In some embodiments, the silicon photonic packaging structure further includes: a potting layer disposed above the graphene layer and sealing the gap between the first chip and the second chip, wherein the potting layer has a surface protruding away from the graphene layer.

[0018] In some embodiments, the encapsulation layer completely encapsulates the first chip and the second chip, wherein the top surface of the encapsulation layer is higher than the top surfaces of the first chip and the second chip, and the sidewalls of the encapsulation layer extend beyond the lateral extent of the first chip and the second chip.

[0019] In some embodiments, the sidewalls of the encapsulation layer are aligned with the sidewalls of the circuit layer.

[0020] In some embodiments, the sidewalls of the encapsulation layer are recessed from the sidewalls of the circuit layer.

[0021] In some embodiments, the bridging structure has a tapered shape in the direction from the first chip and the second chip toward the circuit layer, and the metal layer has a U-shaped structure.

[0022] Other embodiments of this application provide a silicon photonic packaging structure, including: a bridging structure; a first chip and a second chip disposed above the bridging structure; an optical transceiver disposed on the first chip and the second chip and directly connected to the bridging structure; and an electrical transceiver disposed on the first chip and the second chip and electrically connected to the bridging structure, wherein the bridging structure includes a plurality of stacked graphene layers, and the optical transceiver and the electrical transceiver respectively transmit light and electricity through the bridging structure.

[0023] In some embodiments, the optical transceiver includes a transmitter and a receiver.

[0024] In some embodiments, the bridging structure further includes a metal layer for carrying the plurality of graphene layers, wherein the bridging structure has a tapered shape in the direction from the first chip and the second chip toward the circuit layer, and the metal layer has a U-shaped structure.

[0025] This application utilizes multiple graphene layers to form graphene bridging lines that simultaneously serve as photoelectric channels, thereby replacing the photoelectric channels formed using different materials in the prior art. This can reduce splitting or delamination caused by material CTE mismatch in silicon photonic packaging structures, while also reducing the packaging thickness of silicon photonic packaging structures. Attached Figure Description

[0026] The various aspects of this utility model can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0027] Figure 1 The packaging structure in the prior art is shown.

[0028] Figures 2 to 11 A silicon photonic packaging structure according to some embodiments of this application is shown.

[0029] Figures 12 to 40 as well as Figure 41A and Figure 41B The process for forming a silicon photonic packaging structure according to some embodiments of this application is illustrated. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art are within the scope of protection of this application. In addition, when using terms such as "approximately," "about," "substantial," or "basically" to describe numerical values ​​or numerical ranges, unless otherwise stated, the term is intended to cover values ​​within ±10% of the described value. For example, the term "about 5nm" covers a size range from 4.5nm to 5.5nm.

[0031] This application uses circuits made of the same material with good electrical and optical properties, such as graphene (lowest resistivity = 0.5 x 10⁻⁶). -6 Ω·cm⁻¹.0x10 -6 With a high transmittance of ≥98% in visible light (Ω·cm), the material's CTE mismatch can be resolved. Furthermore, the redistributed graphene exhibits a high thermal conductivity of 3000 W / m·K–5300 W / m·K, providing enhanced heat dissipation efficiency for the entire packaging structure. Further, for FOCOS applications, using multiple graphene layers as graphene bridging provides excellent optoelectronic interconnect performance and higher efficiency; these graphene layers possess excellent electrical properties (minimum resistivity <0.5 x 10⁻⁶). -6 The graphene layer exhibits excellent light transmittance (≥98%) and high light transmittance (≥98% in visible light). This optoelectronic design facilitates reducing the thickness of the multilayer redistributed structure containing the graphene layer, thereby meeting the requirements for miniaturization and lower cost solutions. Therefore, this application utilizes graphene to address the aforementioned problems. Specifically, it leverages graphene's simultaneous light transmittance, good conductivity, and heat dissipation capabilities to simultaneously function as an optical / electrical channel, replacing the original separate bridging structure and simultaneously reducing stress and encapsulation thickness.

[0032] See Figure 2Some embodiments of the silicon photonics packaging structure 100 of this application include: a circuit layer 107, in which a bridging structure 103 is disposed, as shown in the dashed box; a first chip 101 and a second chip 102 disposed on the circuit layer 107; an optical transceiver 104 disposed on the first chip 101 and the second chip 102, and transmitting optical signals through the bridging structure 103; and an electrical transceiver 105 disposed on the first chip 101 and the second chip 102, and transmitting electrical signals through the bridging structure 103. Figure 3 It shows Figure 2 An enlarged view of region B of the silicon photonics packaging structure 100 shown, and as... Figure 2 and Figure 3 As shown, the bridging structure 103 includes a plurality of stacked graphene layers 103s. In some embodiments, the optical transceiver 104 includes a transmitter and a receiver; that is, one of the optical transceivers 104 disposed on the first chip 101 and the second chip 101 is a transmitter, and the other is a receiver, which can be determined according to the actual situation. In some embodiments, the bridging structure 103 further includes a metal layer 103M for supporting the plurality of graphene layers 103s. Further, the electrical transceiver 105 is electrically connected to the metal layer 103M, and the optical transceiver 104 is directly connected to the graphene layers 103s. In the direction D from the first chip 101 and the second chip 102 toward the line layer 107, the bridging structure 103 has a tapered shape, and the metal layer 103M has a U-shaped structure. Multiple graphene layers 103s (graphene bridging lines) supported by the metal layer 103M can form a U-shaped structure from two undulating reflective layers (graphene layers 103s). This U-shaped structure provides three functions: first, optical signal transmission can proceed from the transmitter in the optical transceiver 104 through the space of the graphene layers 103s after the first reflection; second, the receiver in the optical transceiver 104 can obtain the signal from the second reflection, such as... Figure 3 The optical transmission path P in the diagram is shown. Furthermore, the graphene layer 103s is an excellent circuit material that can be used for higher-speed electronic signal transmission, and... Figure 3 The electrical transmission path L' of the electrical transceiver 105 is shown in the figure. It can be seen that in this application, an inclined cross-section is formed at the edges of the multiple graphene layers 103s (graphene bridging lines), (e.g., through drilling), providing excellent horizontal circuitry for higher-speed signal transmission between two chips (e.g., the first chip 101 and the second chip 102), and the highest thermal conductivity of the multilayer graphene material (i.e., the multiple graphene layers 102s) is as high as 5300 W / m·K, which is beneficial for improving the heat dissipation efficiency of the entire silicon photonic packaging structure 100.

[0033] from Figure 2 and Figure 3As can be further seen, the bridging structure 103 also includes a seed layer 103A disposed on the graphene layer 103s and a seed layer 103B disposed between the graphene layer 103s and the metal layer 103M. In some embodiments, the seed layer 103A is a bridging seed layer, the seed layer 103B is a reflective seed layer, and the metal layer 103M is a reflective layer. In embodiments with the seed layer 103A, the seed layer 103A has a reflective function. Figure 3 As shown, the seed layer 103A covers a portion of the graphene layer 103s, and the seed layer 103A is not provided at the position directly below the optical transceiver 104 to facilitate optical transmission between the optical transceiver 104 and the graphene layer 103s.

[0034] Furthermore, from Figure 2 and Figure 3 As can be seen, the silicon photonics packaging structure 100 further includes a packaging layer 106, which encapsulates the first chip 101 and the second chip 102, and further encapsulates the optical transceiver 104 and the electrical transceiver 105. In some embodiments, the portion of the packaging layer 106 located between the first chip 101 and the second chip 102 has a surface 106t recessed toward the graphene layer 103s. In some embodiments, the packaging layer 106 may be a molding compound, an underfill, etc. In this embodiment, the packaging layer 106 encapsulates a portion of the first chip 101 and the second chip 102, and the sidewalls 106s of the packaging layer 106 extend beyond the lateral range of the first chip 101 and the second chip 102. Furthermore, the silicon photonics packaging structure 100 also includes an external connector 111 disposed on the side of the circuit layer 107 opposite to the first chip 101 and the second chip 102; in some embodiments, the external connector 111 may be a solder bump.

[0035] from Figure 2 and Figure 3 As can be seen, the seed layer 103A is disposed between the encapsulation layer 106 and the graphene layer 103s. Further, the circuit layer 107 in the silicon photonics encapsulation structure 100 includes corresponding dielectric layers 107A-107C, metal lines and vias 107M embedded in the dielectric layers, and a pad 107P located on top of the dielectric layer 107A. For example... Figure 2As shown, the first chip 101 is connected to the pad 107P of the circuit layer 107 via pads 101P and corresponding microbumps 108, and the second chip 102 is connected to the pad 107P of the circuit layer 107 via pads 102P and corresponding microbumps 109. Further, the transceiver 105 of the first chip 101 can be composed of pads 101P and corresponding microbumps 108, and the transceiver 105 of the second chip 102 can be composed of pads 102P and corresponding microbumps 109. In some embodiments, pads 101P and 102P are chip pads, and microbumps 108 and 109 can be internal connectors and can be made of solder. In this embodiment, the seed layer 103B serves as the solder mask layer for the microbumps 108 and 109.

[0036] In the aforementioned silicon photonics packaging structure 100, the non-metallic materials of the packaging layer 106 and the dielectric layers 107A-107C in the circuit layer 107 can optionally be PI (polyimide), epoxy resin, ABF (Ajinomoto reinforced film), PP (polypropylene) or / and acrylic resin. In some embodiments, organic photosensitive and / or non-photosensitive liquids and / or dry film materials can also be used. The graphene material of the graphene layer 103s is an anisotropic material that conducts electricity in the lateral direction H. In some embodiments, the pads 101P and 102P, the seed layers 103A and 103B, the metal layer 103M, and the metal lines and vias 107M can be selected from any suitable metal material. In some embodiments, the same or different metal materials such as copper, gold, silver, aluminum, palladium, platinum, and nickel alloys can be used. In some embodiments, the microbumps 108 and 109 and the external connectors 111 can be made of deformable materials, such as solder, ACF (anisotropic conductive film), ACP (anisotropic conductive paste), etc. In some embodiments, each of the pads 101P and 102P, the seed layers 103A and 103B, and the metal line and via 107M may include a corresponding seed layer and a corresponding metal layer formed on the seed layer, which may be selected according to the actual situation.

[0037] Next, refer to Figure 4 To describe the dimensions of the various components in the silicon photonics packaging structure 100, it should be noted that... Figure 4 Only some component designations are shown. For details, see [link to documentation]. Figure 4The thickness (GBT) of multiple graphene layers 103s (graphene bridging lines) is in the range of 0.5 μm to several μm, and the thickness of the seed layer 103A is in the range of 0.1 μm to 0.5 μm. The length (GBL) of the multiple graphene layers 103s is in the range of 10μm-300μm, the thickness (DT) of the dielectric layer 107A is in the range of 1μm-5μm, the gap (GBCD) between the second chip 102 and / or the first chip 101 and the surface of the dielectric layer 107A is in the range of 10μm-30μm, the distance (DBB) between the electrical transceivers 105 is in the range of 30μm-500μm, the distance (DBD) between the optical transceivers 104 is in the range of 20μm-250μm, the spacing (SBC) between the first chip 101 and the second chip 102 is in the range of 10μm-200μm, and the spacing between the corresponding optical transceivers 104 and electrical transceivers 105 of the first chip 101 or the second chip 102 is in the range of 5μm-30μm. In some embodiments, the dimensions (or diameters) of the microbumps 108 and 109 in the lateral direction H are in the range of 5 μm to 20 μm, the dimensions (or diameters) of the external connector 111 in the lateral direction H are in the range of 50 μm to 100 μm, and the edge angle (θ) of the graphene layer 103s is in the range of 5° to 85°.

[0038] Next, see Figure 5 , Figure 5 This illustrates a silicon photonics package structure 100' in which an external connector 111 is connected to a substrate 112 (or motherboard). Figure 4 As can be seen, the external connector 111 can be connected to the pad 112P on the substrate 112 (or motherboard) and is encapsulated by another encapsulation layer 110. In some embodiments, the other encapsulation layer 110 may be the same as or different from the encapsulation layer 106. In one embodiment, the substrate 112 can be any suitable substrate, such as a printed circuit board.

[0039] See Figure 6 , Figure 6 A silicon photonics packaging structure 200 according to some embodiments of this application is shown, which is related to... Figure 2 The silicon photonics packaging structure shown is similar to 100, except that... Figure 6 In the silicon photonics packaging structure 200 shown, a solder resist layer 112 is provided on the seed layer 103A and the circuit layer 107. This solder resist layer 112 is an organic layer. Therefore, in the silicon photonics packaging structure 200, an organic layer such as the solder resist layer 112 is used as the solder resist layer for the microbumps 109, instead of using... Figure 2The seed layer 103B in the silicon photonics packaging structure 100 shown is used as a solder resist layer. In some embodiments, the solder resist layer 112 can be any suitable organic layer, such as organic materials like PI, PP, etc.

[0040] See Figure 7 , Figure 7 A silicon photonics packaging structure 300 according to some embodiments of this application is shown, which is related to... Figure 2 The silicon photonics encapsulation structure 100 shown is similar, except that the encapsulation layer 106 is made of a non-transparent, highly reflective material. In this embodiment, a seed layer 103A may not be formed in region F on the upper surface of the graphene layer 103s. In some embodiments, region F is filled by the encapsulation layer 106, and the encapsulation layer 106 is in direct contact with the graphene layer 103s. As described above, in embodiments with a seed layer 103A, the seed layer 103A has a reflective function, while... Figure 7 In the silicon photonics encapsulation structure 300 shown, the non-transparent, highly reflective material has a reflective function.

[0041] See Figure 8 , Figure 8 A silicon photonics packaging structure 400 according to some embodiments of this application is shown, which is related to the silicon photonics packaging structure 300. Figure 2 The silicon photonics packaging structure shown is similar to 100, except that... Figure 8 The silicon photonics packaging structure 400 shown further includes: a potting layer 113 disposed above the graphene layer 103s and sealing the gap between the first chip 101 and the second chip 102. The potting layer 113 has a surface 113s protruding away from the graphene layer 103s. The potting layer 113, or the encapsulation layer 106 in the above embodiments, can be used to protect the graphene layer 103s. The method of protecting the graphene layer 103s includes using an underfill encapsulation layer 106 and / or a potted potting layer 113 followed by an underfill encapsulation layer 106. Furthermore, Figure 8 The external connector 111 in the silicon photonics packaging structure 400 shown is further connected to the substrate 112.

[0042] See Figures 9 to 11 , Figures 9 to 11 Silicon photonic packaging structures 500-700 according to some embodiments of this application are shown, which are related to... Figure 2 The silicon photonics packaging structure shown is similar to 100, except that... Figure 9 In the silicon photonics packaging structure 500, a capillary bottom fill (CUF) packaging layer 106 can be used to form Figure 9The silicon photonics packaging structure 500 shown, and the capillary bottom fill (CUF) packaging layer 106 can also be as follows: Figure 2 The structure shown. Figures 10 to 11 In the silicon photonic packaging structures 600 and 700 shown, the encapsulation layer 106 completely encapsulates the first chip 101 and the second chip 102 through partial molding or full molding (MUF). In this embodiment, the top surface (surface 106t) of the encapsulation layer 106 is higher than the top surfaces of the first chip 101 and the second chip 102, and the sidewalls 106s of the encapsulation layer 106 extend beyond the lateral extent of the first chip 101 and the second chip 102. Figure 10 In the silicon photonics packaging structure 600 shown, the sidewall 106s of the packaging layer 106 is aligned with the sidewall 107s of the circuit layer 107. Figure 11 In the silicon photonics packaging structure 700 shown, the sidewall 106s of the packaging layer 106 is recessed from the sidewall 107s of the circuit layer 107. It can be seen that in... Figure 9 The silicon photonics package structure 500 shown can be protected using a capillary bottom-filled encapsulation layer 106, while... Figure 10 and Figure 11 In the silicon photonics packaging structures 600 and 700 shown, a partially molded or fully molded (MUF) packaging layer 106 can be used to protect the corresponding silicon photonics packaging structures 500 and 600. Furthermore, Figure 10 and Figure 11 The external connector 111 in the silicon photonics packaging structures 600 and 700 shown is further connected to the substrate 112.

[0043] Return to reference Figures 2 to 3 Other embodiments of this application provide a silicon photonics packaging structure 100, including: a bridging structure 103; a first chip 101 and a second chip 102 disposed above the bridging structure 103; an optical transceiver 104 disposed on the first chip 101 and the second chip 102 and directly connected to the bridging structure 103; and an electrical transceiver 105 disposed on the first chip 101 and the second chip 102 and electrically connected to the bridging structure 103. The bridging structure 103 includes a plurality of stacked graphene layers 103s, and the optical transceiver 104 and the electrical transceiver 105 respectively transmit light and electricity through the bridging structure 103. In some embodiments, the optical transceiver 104 includes a transmitter and a receiver. In some embodiments, the bridging structure 103 further includes a metal layer 103M for carrying a plurality of graphene layers 103s, and wherein the bridging structure 103 has a tapered shape in the direction D from the first chip 101 and the second chip 102 toward the line layer 107, and the metal layer 103M has a U-shaped structure, and the stacked plurality of graphene layers 103s carried by the metal layer 103M also have a U-shaped structure.

[0044] In summary, this application utilizes the properties of graphene, which simultaneously possesses light transmittance, good conductivity, and heat dissipation capabilities, to form a bridging structure 103 that can be used as both an optical and electrical channel. This replaces the original bridging structure that separates the optical and electrical channels, thereby reducing the stress and packaging thickness of the silicon photonics packaging structure 100-700 and minimizing the problems of splitting or delamination.

[0045] The following will refer to Figures 12 to 40 Let me introduce Figure 5 The silicon photonics packaging structure 100' shown is illustrated.

[0046] See Figure 12 A carrier 1001 is provided on which a seed layer 103A' is formed (manufactured). In some embodiments, the carrier 1001 can be any suitable carrier, such as a glass carrier, a silicon carrier, etc., and the seed layer 103A' can be a copper seed layer. See also Figure 13 Multiple graphene layers 103s were deposited using a deposition process such as PVD (physical vapor deposition) P1 to achieve the target thickness. See [link to documentation]. Figure 14 Multiple graphene layers 103s are patterned using a laser drilling process P2 to fabricate graphene layers 103s for use in graphene bridging. For example... Figure 14 As shown, the multiple graphene layers 103s used as graphene bridging wires have inclined sidewalls.

[0047] Next, see Figures 15 to 16 The portion of the seed layer 103A' not covered by the graphene layer 103s is removed using an etching process P3, such as oxygen plasma etching, thereby forming... Figure 16 The structure shown. (As illustrated) Figure 16 As shown, multiple graphene layers 103s were formed for graphene bridging.

[0048] See Figure 17 For example, a PVD deposition process can be used to deposit a seed layer 103B on the graphene layer 103 and the carrier 1001, such as using copper to form the seed layer 103B. See then... Figures 18 to 19 The photoresist 1002 is formed using a lamination process, and then exposed and developed using a photolithography process (P4) to form a structure as shown. Figure 19 The photoresist opening shown is 1002O. (As shown...) Figure 19 As shown, a metal such as copper is deposited in the photoresist opening 1002O to form a metal layer 103M'.

[0049] See afterward. Figure 20The photoresist 1002 is removed, and the metal layer 103M' is patterned, thereby forming the metal layer 103M and the pad 107P. See also Figure 21 A dielectric layer 107A is formed on the metal layer 103M and the pads 107P using a coating process such as P5, or by using PI to form the dielectric layer 107A. Then, a photolithography process is used to expose and develop the dielectric layer 107A using P5, thereby forming openings that expose the pads 107P, such as... Figure 22 As shown. See further details. Figure 22 A seed layer 107Ms is formed on the dielectric layer 107A and in the openings of the exposed pads 107P of the dielectric layer 107A, such as by a PVD process.

[0050] See Figure 23 Photoresist 1003 is formed on dielectric layer 107A and seed layer 107Ms by a process such as lamination. The photoresist 1003 is then exposed and developed by a photolithography process, thereby forming P6 within the photoresist 1003. Figure 24 The opening shown is 1003O. (As shown in the image) Figure 24 As shown, a metal layer of 107 μm, such as copper, is plated in the opening 1003O, such as by a plating process including chemical plating or electroplating. See then... Figure 25 The photoresist layer 1003 is removed, and the portion of the seed layer 107Ms not covered by the metal layer 107Mm is removed, thereby forming metal lines and vias 107M. Then, the process is repeated. Figure 21 To the diagram Figure 25 The process shown allows for the formation of a dielectric layer 107B on the dielectric layer 107A, in which metal wires and vias 107M are embedded, as shown. Figure 26 As shown.

[0051] See afterward. Figure 27 A dielectric layer 107C is formed on a dielectric layer 107B using a process such as lamination, and then the dielectric layer 107C is exposed and developed using a photolithography process P7, thereby forming openings in the dielectric layer 107C to expose metal lines and vias 107M, such as... Figure 28 As shown. See also Figure 28 A seed layer 107Ms is formed on the dielectric layer 107C and in the corresponding openings, such as through a PVD process. See also Figure 29 For example, photoresist 1004 is formed on the seed layer 107Ms through a lamination process, and the photoresist 1004 is exposed and developed P8 to form a structure such as... Figure 30 The opening shown is 1004O. (As shown...) Figure 30 As shown, the opening 1004O may or may not expose the metal wire and the through-hole 107M. Further, as... Figure 30 As shown, a 107 μm metal layer is plated in the opening 1004O, using a metal such as copper. Then, as... Figure 31 As shown, a solder layer 111' is plated on the metal layer 107Mm in the opening 1004O. See then... Figure 32 The portion of the photoresist 1004 and the seed layer 107Ms not covered by the metal layer 107Mm is removed, thereby forming a metal line or via 107M in the dielectric layer 107C. Then, the solder layer 111' is reflowed using a heating process P9 to form the desired bump shape, thereby forming the external connector 111.

[0052] See Figure 33 ,Will Figure 32 The resulting structure is flipped and attached to a substrate 112 on which pads 112P are formed, that is, the external connectors 111 on the fan-out redistribution structure (FORDL) circuit layer 107 are bonded to the substrate 112. Figure 33 As shown, pad 112P is encapsulated by another packaging layer 110. See also Figure 34 After the external connector 111 is attached to the substrate 112, the resulting structure is flipped over, and the carrier 1001 is removed by a carrier removal process such as a peeling process.

[0053] Next, see Figure 35 The photoresist 1005 is formed through processes such as lamination, and then exposed and developed (P10) the photoresist 1005 using photolithography. Afterwards, as... Figure 36 As shown, a portion of the photoresist 1005 is removed using the commonly used etching process P11, thereby forming an opening 1005O to expose the pad 107P. See [link to relevant documentation]. Figure 37 Remove the photoresist 1005 to expose the pads 107P for attaching the microbumps.

[0054] See Figure 38 The first chip 101 is bonded by bonding the microbumps 108 of the first chip 101 to the pads 107P. For example... Figure 38 As shown, the surface of the first chip 101 has pads 101P, microbumps 108 are formed on the pads 101P, and an optical transceiver 104 is further disposed on the first chip 101. The pads 101P and corresponding microbumps 108 adjacent to the optical transceiver 104 form an electrical transceiver 105. Figure 38 As shown, the optical transceiver 104 is aligned with the opening of the seed layer 103A so that the optical transceiver 104 can be directly connected to the graphene layer 103s.

[0055] See Figure 39 ,and Figure 38 The process shown is similar, involving bonding the second chip 102 to the pad 107P via microbumps 109. (As shown) Figure 39As shown, the surface of the second chip 102 has pads 102P formed thereon, microbumps 109 are formed on the pads 102P, and an optical transceiver 104 is further disposed on the second chip 102, and the pads 102P and the corresponding microbumps 109 adjacent to the optical transceiver 104 form an electrical transceiver 105. Figure 39 As shown, the optical transceiver 104 is aligned with the opening of the seed layer 103A so that the optical transceiver 104 can be directly connected to the graphene layer 103s.

[0056] Finally, see Figure 40 An underfill material is formed around the first chip 101 and the second chip 102 and between the first chip 101 and the second chip 102 and the circuit layer 107 by means of a capillary underfill process (CUF) or other suitable underfill process, thereby forming an encapsulation layer 106 that encapsulates the first chip 101 and the second chip 102, thereby forming Figure 5 The silicon photonics packaging structure 100' shown is illustrated.

[0057] Figure 41A and Figure 41B Various shapes of the carrier, such as carrier 1001, are shown. Figure 41A and Figure 41B As shown, the carrier 1001 can use different types of carriers, such as those using... Figure 41A The shown square-shaped carrier or use Figure 41B The carrier is circular in shape as shown.

[0058] In the above-described fabrication process, firstly, a carrier 1001 with graphene bridging (WL (wafer-level) or PNL (panel-level)), a metal pattern (metal layer 103M), and reflective seed layers 103A and 103B (e.g., using Ti, Ni, and / or Cu) are prepared. The graphene layer 103s used for the graphene bridging is fabricated by PVD and laser drilling processes. Further, reflective layers using seed layers 103A and 103B are placed above and below the graphene bridging. These seed layers 103A and 103B form the same channel for both light and circuitry, thereby avoiding the splitting or delamination problems of the silicon photonics package structure 100'. Furthermore, in this application, photolithography and deposition processes are used to fabricate the metal layer 103M and the seed layers 103A and 103B.

[0059] Next, a multilayer redistribution structure circuit layer 107 is manufactured from the surface of the metal pattern of the carrier 1001 and the metal layer 103M, etc. Bumps are then manufactured on the surface of the multilayer redistribution structure of the circuit layer 107 using photolithography and plating processes for use with external connectors 111, etc.

[0060] Finally, after bumps such as external connector 111 are bonded to the substrate 112, the carrier is removed from the circuit layer 107. Next, a first chip 101 and a second chip 102, having microbumps 108 and 109 on their surfaces respectively, and optical transceivers 104 such as transmitters and receivers, are bonded to pads 107P, which are exposed (formed) by etching a portion of the seed layer 103A on the plane after the carrier 1001 has been removed. After a bottom package is formed to form a package layer 106 by filling the gaps between the first chip 101 and the second chip 102 and between the first chip 101 and the second chip 102 and the dielectric layer 107A with an underfill material, a silicon photonic package structure 100' is formed.

[0061] In the above-described forming process, in addition to the methods described above, different manufacturing methods such as PVD, electroplating, electroless plating, printing, and metal potting can also be used to form pads 101P and 192P, circuit layer 107, seed layers 103A and 103B, external connector 111, and graphene layer 103s.

[0062] This application utilizes multiple graphene layers 103s to form graphene bridging lines that simultaneously serve as photoelectric channels, thereby replacing the photoelectric channels formed using different materials in the prior art. This can reduce the splitting or delamination caused by material CTE mismatch in the silicon photonic packaging structure 100-700, while also reducing the packaging thickness of the silicon photonic packaging structure 100-700.

[0063] The features of several embodiments have been summarized above to enable those skilled in the art to better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present invention.

Claims

1. A silicon photonics packaging structure, comprising: A circuit layer, wherein a bridging structure is provided in the circuit layer; The first chip and the second chip are disposed on the circuit layer; An optical transceiver is disposed on the first chip and the second chip, and performs optical transmission through the bridging structure; as well as An electrical transceiver is disposed on the first chip and the second chip, and performs electrical transmission through the bridge structure. The bridging structure comprises multiple stacked graphene layers.

2. The silicon photonic packaging structure according to claim 1, wherein, The optical transceiver includes a transmitter and a receiver, wherein the optical transceiver is directly connected to the graphene layer.

3. The silicon photonic package structure of claim 1, wherein, The bridging structure also includes: A metal layer is used to support the plurality of graphene layers. The electrical transceiver is electrically connected to the metal layer.

4. The silicon photonic packaging structure according to claim 1 further includes: The encapsulation layer encapsulates the first chip and the second chip. The portion of the encapsulation layer located between the first chip and the second chip has a surface recessed toward the graphene layer.

5. The silicon photonics package structure of claim 4, wherein, A seed layer is disposed between the encapsulation layer and the graphene layer.

6. The silicon photonic packaging structure according to claim 5, wherein, The seed layer covers a portion of the graphene layer.

7. The silicon photonic packaging structure according to claim 5 further comprises: A solder resist layer is disposed on the seed layer and the circuit layer.

8. The silicon photonics package structure of claim 4, wherein, The encapsulation layer is made of a non-transparent, highly reflective material. The encapsulation layer is in direct contact with the graphene layer.

9. A silicon photonics packaging structure, comprising: Bridging structure; The first chip and the second chip are disposed above the bridging structure; An optical transceiver is mounted on the first chip and the second chip, and is directly connected to the bridging structure; as well as An electrical transceiver is disposed on the first chip and the second chip, and is electrically connected to the bridge structure. The bridging structure comprises multiple stacked graphene layers, and the optical transceiver and the electrical transceiver respectively transmit optical and electrical signals through the bridging structure.

10. The silicon photonics package structure of claim 9, wherein, The optical transceiver includes a transmitter and a receiver. The bridging structure further includes: A metal layer is provided for supporting the plurality of graphene layers, wherein the bridging structure has a tapered shape in the direction from the first chip and the second chip toward the circuit layer, and the metal layer has a U-shaped structure.

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