A high-precision touchpad circuit based on a multi-channel MCU

Abstract

The application relates to a high-precision touchpad circuit based on a multi-channel MCU, which comprises a main control processing module, an external storage module and a touch electrode array module, wherein the main control processing module is connected with row electrodes of the touch electrode array module through a row driving port and connected with column electrodes of the touch electrode array module through an induction port; the external storage module is connected with the main control processing module and used for storing firmware and touch parameters. The high-precision touchpad circuit architecture provided by the application stores the firmware and the touch parameters in the external storage module from the main control processing module, independently configures and reuses the storage resources under the condition that the connection relationship between the row driving and the column induction is not changed, so that the overall cost is reduced and the flexibility of parameter updating and mass production calibration is improved.

Description

Technical Field

[0001] This application relates to the field of touch control, and in particular to a high-precision touchpad circuit based on a multi-channel MCU. Background Technology

[0002] High-precision touchpad circuits using multi-channel MCUs are widely used in laptops, home appliance HMIs, and industrial control terminals. These circuits typically employ a row-column matrix touch electrode structure. The main controller performs timing scans of the row electrodes and highly sensitive acquisition and calculation of capacitance changes in the column electrodes to achieve high-resolution, low-noise, and strong anti-interference touch recognition. As touchpad size increases, the number of channels rises, and algorithm complexity increases, the firmware size and the quantity and accuracy requirements of calibration / compensation touch parameters also increase, thus placing higher demands on storage resources and system maintainability.

[0003] Existing solutions mostly use a single-chip multi-channel MCU as the core, connecting row / column electrodes via its row drive port and sensing port respectively. Firmware and touch parameters are usually stored in the MCU's built-in non-volatile memory, or in tightly coupled configurations of storage resources on the same control board. This type of solution performs signal sampling, filtering, compensation, threshold determination, and gesture recognition within the MCU, and, in conjunction with production calibration, writes parameters for different models into on-chip memory to achieve productization of general-purpose hardware with differentiated parameters.

[0004] However, with the accelerated iteration of channel counts and algorithms, on-chip storage capacity, bandwidth, and erase / write lifespan have gradually become bottlenecks. To meet the storage requirements of firmware and a large number of touch parameters, it is often necessary to choose higher-specification, multi-channel MCUs with larger on-chip storage, leading to increased bill of materials (BOM) costs. The strong coupling of parameters and firmware within the MCU complicates parameter management and back-end calibration processes for different models / batches, requiring a complete firmware upgrade for version switching, increasing maintenance costs and risks. At the same time, fixed on-chip resources make it difficult to flexibly expand or reduce according to product lines, resulting in uneconomical inventory and configuration. To address these issues, a high-precision touchpad circuit architecture is needed that moves the storage module out of the main control processing module and uses external storage to carry firmware and touch parameters. While maintaining the row drive / column sensing connection relationship, this architecture enables independent configuration and reuse of storage resources, thereby reducing overall costs and improving the flexibility of parameter updates and mass production calibration. Utility Model Content

[0005] In view of this, it is necessary to provide a high-precision touchpad circuit based on a multi-channel MCU with the storage module moved externally, in order to solve the above problems.

[0006] Embodiments of this application provide a high-precision touchpad circuit based on a multi-channel MCU, including a main control processing module, an external storage module, and a touch electrode array module, wherein: the main control processing module is connected to the row electrodes of the touch electrode array module through its row driving port and to the column electrodes of the touch electrode array module through its sensing port; the external storage module is connected to the main control processing module and is used to store firmware and touch parameters.

[0007] In at least one embodiment of this application, the main control processing module uses a touch processor PCT1035QN, and the connection relationship between its pins and peripheral components is as follows: the DRV1 to DRV23 pins of the PCT1035QN are respectively connected to the row electrodes of the touch electrode array module via series current-limiting resistors; the SEN1 to SEN13 pins of the PCT1035QN are respectively connected to the column electrodes of the touch electrode array module via series current-limiting resistors; the SPI_CS pin of the PCT1035QN is connected to the CS terminal of the external storage module, the SPI_CLK pin is connected to the CLK terminal of the external storage module, the SPI_MOSI pin is connected to the DI terminal of the external storage module, and the SPI_MISO pin is connected to the DO terminal of the external storage module; the I... The PCT1035QN's I²C_SCL pin is connected to the SCL terminal of the connector and then to VCC via a pull-up resistor. The PCT1035QN's I²C_SDA pin is connected to the SDA terminal of the connector and then to VCC via a pull-up resistor, used for HID-I²C communication with the host computer. The PCT1035QN's INT pin is connected to the INT terminal of the connector and then to VCC via a pull-up resistor, used for outputting a touch / data ready interrupt. The PCT1035QN's EN pin is connected to the EN terminal of the connector and then to VCC via a pull-up resistor, used for power-on and sleep control. The PCT1035QN's VIN pin is connected to VCC and then to signal ground via a decoupling capacitor; the VDD pin is connected to VCC and then to signal ground via a decoupling capacitor; and the GND pin is connected to signal ground.

[0008] In at least one embodiment of this application, the external storage module uses a ZB25WD40C, and the connection relationship between its pins and peripheral components is as follows: the CS pin of the ZB25WD40C is connected to the SPI_CS pin of the main control processing module; the SCLK pin is connected to the SPI_CLK pin of the main control processing module; the SI pin is connected to the SPI_MOSI pin of the main control processing module; the SO pin is connected to the SPI_MISO pin of the main control processing module; the VCC pin is connected to the VCC power network and connected to signal ground with a parallel filter capacitor; the VSS pin is connected to signal ground; the WP pin is connected to VCC through a pull-up resistor; and the HOLD pin is connected to VCC through a pull-up resistor.

[0009] In at least one embodiment of this application, the touch electrode array module includes: a 13×23 capacitive sensing matrix; wherein each row electrode is connected to the DRV1 to DRV23 pins of the PCT1035QN through a current-limiting resistor, and each column electrode is connected to the SEN1 to SEN13 pins of the PCT1035QN through a current-limiting resistor; the resistance value of the current-limiting resistor is in the range of 100Ω to 1kΩ.

[0010] In at least one embodiment of this application, a configuration circuit module is further included, the configuration circuit module comprising: a configuration resistor network connected between the GPIO1 to GPIO4 pins of the PCT1035QN and the VCC / signal ground; the resistance value combination of the configuration resistor network is used to set the address and operating mode of the device.

[0011] In at least one embodiment of this application, a communication interface module is further included, comprising: an I²C communication interface, consisting of the I²C_SCL signal line and the I²C_SDA signal line of the PCT1035QN and connected to VCC via a pull-up resistor; an SPI communication interface, consisting of the SPI_CLK, SPI_MOSI, SPI_MISO, and SPI_CS signal lines of the PCT1035QN; an interrupt output interface, consisting of the INT signal line of the PCT1035QN and connected to VCC via a pull-up resistor; and an enable control interface, consisting of the EN signal line of the PCT1035QN and connected to VCC via a pull-up resistor.

[0012] In at least one embodiment of this application, a switch and jumper configuration module is further included, wherein: one end of the first switch S1 is connected to the reset / BOOT configuration pin of the main control processing module and the other end is connected to signal ground; one end of the second switch S2 is connected to the K1 function input pin of the main control processing module and the other end is connected to signal ground; jumpers JR1, JB1, and JC1 respectively connect the configuration pin of the main control processing module to VCC or to signal ground, for address / function selection and production test mode switching.

[0013] In at least one embodiment of this application, a test module is further included, the test module including test points T1 to T7, wherein: test point T1 is connected to the EN signal of the PCT1035QN; test point T2 is connected to the INT signal of the PCT1035QN; test point T3 is connected to the I²C_SDA signal of the PCT1035QN; test point T4 is connected to the I²C_SCL signal of the PCT1035QN; test point T5 is connected to the VCC power network; test point T6 is connected to the K1 signal of the PCT1035QN; and test point T7 is connected to GND.

[0014] In at least one embodiment of this application, a reset circuit module is further included, the reset circuit module comprising: a reset chip, the output of which is connected to the RST pin of the PCT1035QN; a manual reset button, one end of which is connected to the trigger terminal of the reset chip and the other end of which is connected to signal ground; and a power-on reset circuit, which is composed of a resistor-capacitor network and connected between VCC and the trigger terminal of the reset chip.

[0015] In at least one embodiment of this application, a status indication module is further included, the status indication module including: an LED indicator, the anode of which is connected to VCC through a current-limiting resistor and the cathode of which is connected to the GPIO pin of the PCT1035QN; the GPIO pin is configured in open-drain output mode to drive the LED indicator to indicate the working status.

[0016] The aforementioned high-precision touchpad circuit architecture, in which the storage module is moved out of the main control processing module and the firmware and touch parameters are carried by external storage, achieves independent configuration and reuse of storage resources while maintaining the row drive / column sensing connection relationship. This reduces the overall cost and improves the flexibility of parameter updates and mass production calibration. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a block diagram of the module structure of the high-precision touchpad circuit according to one embodiment of this application; Figure 2 This is a wiring diagram of the touch processor PCT1035QN for the high-precision touchpad circuit described in one embodiment of this application; Figure 3 This is a wiring diagram of the ZB25WD40C chip, the external storage module of the high-precision touchpad circuit described in one embodiment of this application. Figure 4 This is a wiring diagram of the jumper configuration module of the high-precision touchpad circuit according to one embodiment of this application; Figure 5 This is a wiring diagram of the test module described in one embodiment of this application; Figure 6 This is a wiring diagram of the touch electrode array module of the high-precision touchpad circuit according to one embodiment of this application.

[0019] Reference numerals: 100, Touchpad circuit; 10, Main control processing module; 20, External storage module; 30, Touch electrode array module; 40, Configuration circuit module; 50, Communication interface module; 60, Switch and jumper configuration module; 70, Test module; 80, Reset circuit module; 90, Status indicator module; U1, PCT1035QN; U2, ZB25WD40C; S1, First switch; S2, Second switch. Detailed Implementation

[0020] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0022] The embodiments of this application provide a high-precision touch panel circuit 100 based on a multi-channel MCU, including a main control processing module 10, an external storage module, and a touch electrode array module 30, wherein: the main control processing module 10 is connected to the row electrodes of the touch electrode array module 30 through its row driving port and to the column electrodes of the touch electrode array module 30 through its sensing port; the external storage module is connected to the main control processing module 10 and is used to store firmware and touch parameters.

[0023] The aforementioned high-precision touchpad circuit 100 architecture, in which the storage module is moved out of the main control processing module 10 and the firmware and touch parameters are carried by external storage, achieves independent configuration and reuse of storage resources while maintaining the row drive / column sensing connection relationship. This reduces the overall cost and improves the flexibility of parameter updates and mass production calibration.

[0024] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0025] Please refer to Figure 1 - Figure 6 One embodiment of this application provides a high-precision touch panel circuit 100 based on a multi-channel MCU, including a main control processing module 10, an external storage module, and a touch electrode array module 30, wherein: the main control processing module 10 is connected to the row electrodes of the touch electrode array module 30 through its row driving port and to the column electrodes of the touch electrode array module 30 through its sensing port; the external storage module is connected to the main control processing module 10 and is used to store firmware and touch parameters.

[0026] Specifically, in this embodiment, it should be noted that the high-precision touchpad circuit 100 consists of a main control processing module 10, an external storage module, and a touch electrode array module 30. The main control processing module 10 integrates multi-channel row driving and multi-channel sensing sampling resources. Its row driving port applies excitation signals to the row electrodes of the touch electrode array module 30 row by row, and its sensing port samples the capacitance changes of the column electrodes of the array in parallel or time-division. The external storage module is electrically connected to the main control processing module 10 and is used to store the firmware image required for the main control to start and run, as well as the set of parameters related to touch recognition.

[0027] Furthermore, after power-on, the main controller first performs integrity and version verification on the external storage, loads firmware and parameters into the running space as needed, and initializes the row drive waveform, sampling timing, channel mapping and filtering strategy accordingly. Then, it constructs a frame of two-dimensional capacitance change graph according to the scanning sequence of "row drive - column sampling", completes peak extraction, centroid calculation and multi-point tracking through built-in calculation, and finally reports the touch coordinates and events to the host system.

[0028] Furthermore, to ensure signal quality, this embodiment employs timing gating at the row end to isolate crosstalk from non-selective rows at the column end, and uses a differential method of reference sampling – effective sampling at the column end to suppress common-mode noise. To ensure data consistency, the main controller performs gradual tracking of the baseline and uses a short-time filtering window for rapid disturbances to balance response speed and stability. Parameters in external storage can be divided into different configuration areas according to the device model. The main controller selects and loads the corresponding parameter set based on the device identifier, achieving adaptation of the same hardware platform to different sizes, electrode densities, and covering materials. The above structure and connection relationships are limited to the components of this embodiment and do not introduce other functional modules.

[0029] In one specific embodiment, the main control processing module 10 uses a touch processor PCT1035QN chip (hereinafter referred to as U1), and the connection relationship between its pins and peripheral components is as follows: the DRV1 to DRV23 pins of U1 are respectively connected to the row electrodes of the touch electrode array module 30 through series current-limiting resistors; the SEN1 to SEN13 pins of U1 are respectively connected to the column electrodes of the touch electrode array module 30 through series current-limiting resistors; the SPI_CS pin of U1 is connected to the CS terminal of the external storage module, the SPI_CLK pin is connected to the CLK terminal of the external storage module, the SPI_MOSI pin is connected to the DI terminal of the external storage module, and the SPI_MISO pin is connected to the DO terminal of the external storage module; the U1's The I²C_SCL pin is connected to the SCL terminal of the connector and then to VCC via a pull-up resistor. The I²C_SDA pin of U1 is connected to the SDA terminal of the connector and then to VCC via a pull-up resistor, used for HID-I²C communication with the host computer. The INT pin of U1 is connected to the INT terminal of the connector and then to VCC via a pull-up resistor, used for outputting a touch / data ready interrupt. The EN pin of U1 is connected to the EN terminal of the connector and then to VCC via a pull-up resistor, used for power-on and sleep control. The VIN pin of U1 is connected to VCC and then to signal ground via a decoupling capacitor. The VDD pin is connected to VCC and then to signal ground via a decoupling capacitor. The GND pin is connected to signal ground.

[0030] Specifically, in this embodiment, it should be noted that the main control processing module 10 uses a touch processor U1 chip, and its connection relationship with external circuits and touch electrode array is as follows, thereby completing row and column scanning, signal acquisition, and external communication. In this embodiment, the DRV1 to DRV23 row drive pins of U1 are connected to the 23 row electrodes of the touch electrode array via series current-limiting resistors; the SEN1 to SEN13 sensing pins are connected to the 13 column electrodes of the array via series current-limiting resistors. The row-end current-limiting resistors are used to limit the driving transient current, reduce row-to-row coupling and surges, and the column-end current-limiting resistors are used to protect the front-end sampling / shaping network of the sensing port and form damping with wiring parasites, thereby improving the high-frequency noise suppression effect.

[0031] Furthermore, external storage is connected to the main controller via the SPI bus: SPI_CS→CS, SPI_CLK→CLK, SPI_MOSI→DI, SPI_MISO→DO, used to store boot firmware fragments, calibration and compensation parameters, model configuration tables, etc. After the main controller powers on, it accesses the external storage using the on-chip boot code to perform version and checksum checks, and loads the runtime image and parameter set as needed. The external system interface uses HID-I²C: I²C_SCL is pulled up to VCC and then connected to the SCL terminal of the external connector; I²C_SDA is similarly connected to the SDA terminal of the connector. This I²C channel remains pulled up high when idle. When the main controller detects new touch data, it generates a "data ready / state change" interrupt through the INT pin (pulled up to VCC), prompting the host computer to read the coordinates and events according to the HID-I²C protocol.

[0032] Furthermore, in this embodiment, the power and control pins are configured as follows: the EN pin is connected to the EN terminal of the connector and pulled up to VCC for power-on enable and sleep / wake-up control; VIN and VDD are respectively connected to VCC and each is connected in parallel with a decoupling capacitor to signal ground to provide a near-end power loop and suppress power ripple and ground bounce during driving and sampling transients; GND is uniformly connected to signal ground and serves as the reference plane for row / column return paths.

[0033] Furthermore, the operating sequence is as follows: the main controller sets the row excitation amplitude, frequency, and phase according to the parameters loaded from external storage, and selects and drives each row sequentially in the order of DRV1→DRV23; the column terminals SEN1~SEN13 sample the changes in coupling capacitance within the selection window, and generate a row intensity vector through on-chip front-end and digital filtering; after cyclic scanning to form a complete frame matrix diagram, peak positioning and centroid calculation are performed, and finally the data frame is output through HID-I²C, with INT high / low indicating the read clock cycle. To ensure interface robustness and ESD reliability, both I²C and INT lines are pulled up and combined with near-end decoupling of wiring and ground reference plane continuity design; the SPI line pairs are wired with equal length / equal impedance to reduce reflections and crosstalk caused by clock edges. The above connections and processes are strictly limited to the device and pin relationships of this embodiment and do not introduce other undescribed functional modules.

[0034] In one specific embodiment, the external storage module uses a ZB25WD40C chip (hereinafter referred to as U2), and the connection relationship between its pins and peripheral components is as follows: the CS pin of U2 is connected to the SPI_CS pin of the main control processing module 10; the SCLK pin is connected to the SPI_CLK pin of the main control processing module 10; the SI (IO0) pin is connected to the SPI_MOSI pin of the main control processing module 10; the SO (IO1) pin is connected to the SPI_MISO pin of the main control processing module 10; the VCC pin is connected to the VCC power network and connected to the signal ground in parallel with a filter capacitor; the VSS pin is connected to the signal ground; the WP pin is connected to VCC through a pull-up resistor; and the HOLD pin is connected to VCC through a pull-up resistor.

[0035] Specifically, in this embodiment, it should be noted that the external storage module uses a ZB25WD40C serial Flash chip. Its connection relationship with the main control processing module 10 and the power / ground / control pins is as follows, and the storage and access of firmware and touch parameters are completed accordingly. The CS pin of U2 is connected to the SPI_CS pin of the main control for chip select control; the SCLK pin is connected to the SPI_CLK pin of the main control to provide a serial clock; the SI (IO0) pin is connected to the SPI_MOSI pin of the main control for data input from the main control to the memory; and the SO (IO1) pin is connected to the SPI_MISO pin of the main control for data output from the memory to the main control.

[0036] Furthermore, in this embodiment, regarding power supply and reference ground, the VCC pin of U2 is connected to the board-level VCC power network, and a filter / decoupling capacitor is placed in parallel between this pin and the signal ground (VSS / GND) to suppress ripple and ground bounce caused by transient power currents from the master controller's SPI access; the VSS pin is directly connected to the signal ground to provide a stable reference plane. Regarding write protection and bus hold control, the WP pin is connected to VCC via a pull-up resistor, keeping the chip in a default non-write-protected state and preventing it from being floating; the HOLD pin is also connected to VCC via a pull-up resistor, preventing the device from entering the bus hold state by default, ensuring that SPI transmission is not unexpectedly interrupted during normal operation.

[0037] Furthermore, the aforementioned connection ensures that this embodiment can complete the reading and updating of firmware images and touch parameter tables using the standard SPI (single I / O input, single I / O output) operating mode, without the need for additional mode selection or pin multiplexing. After the system powers on, the main controller starts with the minimum boot code, establishes an SPI session with U2 via CS / SCLK / MOSI / MISO, first reads the device ID and status register to confirm the device's online and write-protected status, and then sequentially reads the firmware image and parameter area; when parameter / firmware updates are required, the main controller executes the write enable—page programming—busy detection—verification process, and sets / clears write-protected bits as needed to prevent unintended rewriting.

[0038] Furthermore, to ensure signal integrity, this embodiment uses equal-length and adjacent-to-ground routing for the clock and data lines, and optimizes the edge speed by terminating the CS line near the main control side with pull-up and termination. The power supply decoupling capacitor is placed near the VCC pin to shorten the high-frequency loop. Both WP and HOLD use fixed pull-up resistors to avoid false triggering caused by external interference. The above connections, power-on timing, and access procedures are limited to the device and pin relationships of this embodiment and do not introduce other functional modules outside of this embodiment.

[0039] In one specific embodiment, the touch electrode array module 30 includes a 13×23 capacitive sensing matrix; wherein each row electrode is connected to the DRV1 to DRV23 pins of U1 through a current-limiting resistor, and each column electrode is connected to the SEN1 to SEN13 pins of U1 through a current-limiting resistor; the resistance value of the current-limiting resistor is in the range of 100Ω to 1kΩ.

[0040] Specifically, in this embodiment, it should be noted that the touch electrode array module 30 adopts a 13×23 capacitive sensing matrix structure, wherein 23 row electrodes are connected to the DRV1~DRV23 row drive pins of the touch processor U1 through series current-limiting resistors; and 13 column electrodes are connected to the SEN1~SEN13 sensing pins of U1 through series current-limiting resistors. The resistance value range of the above-mentioned row / column side series resistors is limited to 100Ω~1kΩ. In physical implementation, the row electrodes are arranged horizontally to match the row-by-row gating timing of the main controller, and the column electrodes are arranged vertically to match the parallel / time-division sampling rhythm of the main controller; at the intersection of the row and column electrodes, a variable capacitor unit is formed with the surrounding air through a covering medium (such as a glass / plastic cover plate and its adhesive layer), and the proximity of a finger / stylus will cause an increase in the coupling capacitance of the intersection unit.

[0041] Furthermore, to ensure signal integrity and robustness, the current-limiting resistor connected in series at the row end in this embodiment not only limits the transient current and overshoot generated by the main control drive edge, but also forms a damping network with the traces and electrode parasitic capacitance to reduce high-frequency crosstalk and reflection between rows and between rows and columns; the current-limiting resistor connected in series at the column end plays the role of first-order input protection and bandwidth shaping for the sensing port, which can suppress the impact energy of ESD / EMI shocks on the front-end sampling network, and together with the main control internal sampling and holding capacitor / front-end input capacitor, set a suitable anti-aliasing characteristic.

[0042] Furthermore, regarding resistor selection: when R≈100Ω, the driving edge is faster and the frame rate potential is higher, making it suitable for models with low on-board noise and short wiring; when R is between 200 and 560Ω, a balance is achieved between response speed and noise suppression, making it suitable for most medium-sized touchpads; when R is close to 1kΩ, input protection and high-frequency noise suppression capabilities are stronger, making it more suitable for long traces or strong interference scenarios, but external memory parameters (driving amplitude, sampling window, integration time) are needed to compensate for the possible signal amplitude and phase delay.

[0043] Furthermore, to reduce parasitics and crosstalk, this embodiment preferably features: row / column traces of equal width and spacing, rounded critical corners, continuous reference ground with guard rings at the boundaries, and current-limiting resistors placed close to the main controller or near the array terminals to reduce exposed trace length. The above-mentioned electrode matrix size and current-limiting resistor range settings are limited to this embodiment and do not introduce other size or resistance value variations.

[0044] In one specific embodiment, a configuration circuit module 40 is also included. The configuration circuit module 40 includes a configuration resistor network connected between the GPIO1 to GPIO4 pins of U1 and VCC or signal ground. The combination of resistance values ​​of the configuration resistor network is used to set the address and operating mode of the device.

[0045] Specifically, in this embodiment, it should be noted that the configuration circuit module 40 is used to provide power-on identification of the device address and operating mode for the touch processor U1 through a combination of hardware resistors without modifying the firmware. Specifically, a configuration resistor network is arranged between the four general-purpose pins GPIO1 to GPIO4 of U1 and VCC / signal ground (GND). Each GPIO pin is pulled up to VCC or pulled down to GND through one or a set of resistors with selected values ​​to form a stable logic level. To avoid floating and level jitter, the resistor values ​​are preferably in the range of 10kΩ to 100kΩ (typically 47kΩ), and combined with the small capacitance between the pin and ground (naturally formed by the traces and chip input capacitance) to form a small RC circuit, suppressing power-on transients.

[0046] Furthermore, during the power-on process, U1 internally disables its built-in pull-up / pull-down switches. After a delay of several milliseconds, it samples GPIO1 to GPIO4 once or multiple times and takes multiple values, mapping the four-bit logic to binary code: for example, GPIO1 is the least significant bit and GPIO4 is the most significant bit, thus providing 16 combinations. Some of these combinations are used for HID-I²C slave address selection (such as the encoding mapping of the 0x24 to 0x2B range), while the remaining combinations are used for operating mode settings (such as "low-power scan / standard scan / high sensitivity / production test" etc.).

[0047] Furthermore, to ensure sufficient level margin, the network does not employ a voltage divider intermediate level structure, but instead uses a single-ended classification method with explicit pull-up or pull-down. Resistors are placed close to U1, with short traces and continuous ground references to avoid misinterpretations caused by external noise coupling. The production line can configure addresses and modes for different models by changing the resistor placement positions or mounting orientation. For rapid switching during production testing, alternative positions (such as R_PU and R_PD mutual exclusion bits) can be reserved on the PCB, allowing the logic orientation to be determined by process technology. The above connections and procedures are limited to the resistor network relationship between the four GPIO channels and VCC / GND in this embodiment, and do not introduce switches, jumpers, or other active devices.

[0048] In one specific embodiment, a communication interface module 50 is further included. The communication interface module 50 includes: an I²C communication interface, which is composed of the I²C_SCL signal line and the I²C_SDA signal line of U1 and connected to VCC through a pull-up resistor; an SPI communication interface, which is composed of the SPI_CLK, SPI_MOSI, SPI_MISO and SPI_CS signal lines of U1; an interrupt output interface, which is composed of the INT signal line of U1 and connected to VCC through a pull-up resistor; and an enable control interface, which is composed of the EN signal line of U1 and connected to VCC through a pull-up resistor.

[0049] Specifically, in this embodiment, it should be noted that the communication interface module 50 consists of four types of interfaces, each responsible for communication with the host computer, peripheral data path, event indication, and power / power consumption management functions. Firstly, the I²C communication interface consists of two signal lines, I²C_SCL and I²C_SDA, of U1. Both are connected to VCC via pull-up resistors, used for master-slave data interaction with the host computer according to a predetermined protocol (such as HID-I²C). At the physical level, the open-drain / open-collector design, combined with pull-up resistors, enables wired-AND arbitration of the bus, ensuring reliability when multiple devices share the bus.

[0050] Furthermore, the SPI communication interface consists of four lines: SPI_CLK, SPI_MOSI, SPI_MISO, and SPI_CS, providing a full-duplex, clock-synchronized data link. In the system of this embodiment, this link is used for high-speed data read and write between the main controller and external devices (such as sequential / random access to firmware images and touch parameters), ensuring that necessary data exchange is completed within the scanning interval.

[0051] Furthermore, the interrupt output interface consists of an INT signal line connected to VCC via a pull-up resistor. When the main controller detects a touch event, a data frame ready, or a state change, it actively pulls the line low / high to notify the host computer of the event. The host computer then triggers the reading process, avoiding polling. Fourth, the enable control interface consists of an EN signal line connected to VCC via a pull-up resistor, used for power-on authorization and sleep / wake-up control. Under the default pull-up condition, the system can remain enabled, or it can be pulled low by the host computer or power management device to enter a low-power state.

[0052] Furthermore, to ensure signal integrity, in this embodiment, each pull-up resistor is placed close to the main control pin, the I²C lines are kept of equal length and continuous with the ground reference plane, the SPI lines prioritize clock return path and chip select timing margins, and the INT / EN lines reserve necessary decoupling and protection pads, thereby maintaining stable communication and control under electromagnetic interference and thermal drift conditions. The structure, connection, and application of the above interface are limited to this embodiment and do not introduce other interface forms outside of this embodiment.

[0053] In one specific embodiment, a switch and jumper configuration module 60 is also included, wherein: one end of the first switch S1 is connected to the reset / BOOT configuration pin of the main control processing module 10, and the other end is connected to signal ground; one end of the second switch S2 is connected to the K1 function input pin of the main control processing module 10, and the other end is connected to signal ground; jumpers JR1, JB1, and JC1 respectively connect the configuration pin of the main control processing module 10 to VCC or to signal ground, for address / function selection and production test mode switching.

[0054] Specifically, in this embodiment, it should be noted that the switch and jumper configuration module 60 is used to complete the selection of startup mode, temporary function triggering, address / function bit hardware classification, and mass production test mode switching without changing the connection relationship between the main controller and the electrode matrix. Specifically, it includes: a first switch S1, a second switch S2, and jumpers JR1, JB1, and JC1. One end of the first switch S1 is connected to the reset / BOOT configuration pin of the main controller processing module 10, and the other end is connected to signal ground (GND); one end of the second switch S2 is connected to the K1 function input pin of the main controller, and the other end is also connected to GND. All buttons are instantaneous self-reset structures, defaulting to an open state. Combined with internal or external pull-up (pull-down) mechanisms of the main controller, the target pin maintains a stable logic level when not pressed; when pressed, the target pin is reliably pulled to GND.

[0055] Furthermore, jumpers JR1, JB1, and JC1 are connected to several configuration pins of the main controller, with their pads forming optional shorting points with VCC / GND. Installing shorting blocks or bridging the pads with solder can hardware pull up the corresponding configuration pin to VCC or hardware pull down to GND, allowing the main controller to sample a specific binary combination during power-up. This combination is used for device address / function bit selection and entering and exiting production test modes (such as mass production self-test, noise floor measurement, short open circuit detection, coordinate consistency calibration process triggering, etc.).

[0056] Furthermore, during the power-on process, the main controller first reads the level of the configuration pins where JR1 / JB1 / JC1 are located and latches it as an address / function / test mode flag. If the test mode flag is detected to be valid, the firmware enters the production line-specific process, opens the I²C / SPI test instruction set, and enables more detailed diagnostic reporting. In the running state, S1 is used to trigger a reset or BOOT entry: for example, pressing and holding S1 during power-on forces entry into BOOT loading mode, and releasing it restores normal startup; during operation, a short press of S1 can perform a controlled reset. S2 serves as a temporary function key / diagnostic trigger key, such as initiating self-calibration, performing a one-time threshold re-evaluation, or switching preset sensitivity levels; its trigger edge is debouncing by the firmware and a timestamp is recorded to distinguish the different functions of short press / long press. All the above structures and processes are limited to the connection relationship between S1, S2, JR1, JB1, JC1 and the main controller target pins, VCC / GND in this embodiment, without introducing other switching devices or logic circuits.

[0057] In one specific embodiment, a test module 70 is also included. The test module 70 includes test points T1 to T7, wherein: test point T1 is connected to the EN signal of U1; test point T2 is connected to the INT signal of U1; test point T3 is connected to the I²C_SDA signal of U1; test point T4 is connected to the I²C_SCL signal of U1; test point T5 is connected to the VCC power network; test point T6 is connected to the K1 signal of U1; and test point T7 is connected to GND.

[0058] Specifically, in this embodiment, it should be noted that the test module 70 is used for production line ICT / ATE, functional debugging, and after-sales field diagnosis, and extracts the reachability of key control / communication / power reference signals of the main control processor U1. Specifically, it includes test points T1 to T7, with the following connection relationships: T1 → EN (U1 enable control signal), used for external injection and level observation of power-on permission / sleep wake-up; T2 → INT (data ready / touch event interrupt), used to monitor the main control interrupt timing and duty cycle, and can also verify the upper computer interrupt link by applying a controlled level through a tooling. Furthermore, T3→I²C_SDA and T4→I²C_SCL serve as data / clock observation and injection nodes for the external I²C bus, facilitating logic analysis, waveform integrity assessment, and protocol consistency testing; T5→VCC provides an onboard operating power supply test / injection point for measuring ripple, transients, and voltage drop, and can also supply power to the entire board offline; T6→K1 (main control function input pin) is used to trigger maintenance / self-test commands (such as rapid baseline reconstruction, mass production self-test entry) or verify firmware's debouncing and event parsing of external function pins; T7→GND serves as a universal ground reference and probe return point, ensuring loop closure and reference consistency for high-speed / low-noise measurements.

[0059] Furthermore, to reduce load disturbances to normal operation, the test points in this embodiment use small pads or gold finger contacts, are arranged close to the corresponding signal source, and the shortest return path is reserved; the test pads for high-sensitivity signals such as I²C and INT / EN are connected in series with small-value protective resistors or have series connection positions to limit current and suppress reflection during test injection; for the T5 power supply test point, a measurement ground pad (with T7 sharing a ground reference) is placed near the end to form a short-loop measurement pair, improving the accuracy of ripple / transient readings.

[0060] Furthermore, the production line ATE fixture can complete power-on sequence control, communication link scanning, firmware write verification, and noise and interrupt timing verification processes by making one-time contact with T1 to T7 using spring-loaded clamps. During field maintenance, portable logic analyzers / oscilloscopes can also quickly locate problems through these test points. The number, naming, and connection relationships of the above test points are strictly limited to this embodiment, without introducing additional probe interfaces or debugging connectors.

[0061] In one specific embodiment, it should be noted that the reset circuit module 80 is used to provide a definite, clean and timing-controlled reset signal to the touch processor U1 in the case of power-on, abnormal fluctuations and manual intervention. The module includes three parts.

[0062] Specifically, the reset chip (power monitoring / watchdog integrated or pure power monitoring type) has its output connected to the RST pin of U1. When the power supply voltage is detected to be lower than the threshold, the reset hold timer has not expired, or the external trigger is valid, the output maintains a valid reset level (low / high depending on the device polarity) until the release condition is met and then releases according to the internal timer delay, ensuring that the main controller starts under stable voltage and clock conditions.

[0063] Furthermore, the manual reset button has one end connected to the trigger terminal of the reset chip (such as the MR / RESET_IN pin), and the other end connected to signal ground GND. When pressed, the trigger terminal is forcibly pulled to an active level, and the reset chip outputs a controlled reset pulse. After release, it is restored by an internal / external pull-up. This path avoids user button bounce directly affecting the main control RST; all debouncing and pulse width shaping are performed by the reset chip.

[0064] Furthermore, the power-on reset circuit consists of a resistor-capacitor (RC) network connected between VCC and the trigger terminal of the reset chip. Upon power-on, the capacitor charges from 0V, and the trigger terminal maintains a valid level within the RC time constant, forming a power-on delay reset. This covers the time required for the power regulator startup transition, peripheral power-on initialization, and crystal / clock locking. The RC network value follows the principle that "the time for the RC charging curve to reach the release threshold > the slowest power / clock stabilization time of the system," and ensures that there will be no misjudgment during rapid power-down and repeated power-on cycles (the residual RC voltage achieves rapid reset through a parallel discharge path or internal chip discharge).

[0065] Furthermore, to suppress interference, a small capacitor is connected in parallel near the trigger terminal to filter out spikes. Simultaneously, the traces are routed close to the ground reference plane and away from high dv / dt regions (such as horizontal drive and SPI clock lines) to ensure that the trigger threshold is not crossed by crosstalk. The above connections and timing logic are limited to the specific relationship of the reset chip—U1—RC network—manual button in this embodiment, without introducing other control paths.

[0066] In one specific embodiment, a status indication module 90 is also included. The status indication module 90 includes an LED indicator, whose anode is connected to VCC through a current-limiting resistor and whose cathode is connected to the GPIO pin of U1. The GPIO pin is configured as an open-drain output mode to drive the LED indicator to indicate the working status.

[0067] Specifically, in this embodiment, it should be noted that the status indication module 90 is used to provide visual prompts for key states of the touchpad with minimal hardware overhead. Its specific structure is an LED indicator, whose anode is connected to the VCC power network via a current-limiting resistor; its cathode is directly connected to a GPIO pin of the touch processor U1. This GPIO is configured in open-drain output mode.

[0068] Furthermore, when the GPIO outputs a low level, it is equivalent to pulling the LED cathode to GND, and the LED anode is powered by VCC and the current-limiting resistor to conduct and emit light; when the GPIO outputs a high-impedance state (release), there is almost no voltage difference across the LED and it goes out.

[0069] To ensure a balance between brightness and power consumption, the current-limiting resistor (denoted as R_LED) in this embodiment is preferably selected from 1kΩ to 10kΩ (for example, under a 3.3V power supply, R_LED=2.2kΩ to 3.9kΩ can obtain an indication current of about 0.8 to 1.5mA, which satisfies the balance between indoor visibility and low power consumption).

[0070] Furthermore, the LEDs and resistors are placed close to the VCC bus point and corresponding GPIO pins, ensuring a short return path and continuous ground reference to reduce coupling impact on sensitive analog front-ends. The firmware employs a duty cycle-adjustable PWM drive strategy (maintaining open-drain configuration, with on / off control by timer ticks) to achieve multiple brightness levels under varying ambient brightness and power consumption targets. To improve noise immunity and ESD reliability, LED traces are routed away from high-speed SPI / I²C clocks, and small RC damping bits are reserved near the GPIO pins where necessary to slow edge speed and reduce radiation.

[0071] Furthermore, regarding the semantic indications, this embodiment stipulates that: constant light indicates successful system power-on and normal scanning operation; slow flashing (approximately 1Hz) indicates standby / low power maintenance; fast flashing (approximately 4Hz) indicates firmware upgrade / parameter writing in progress; and intermittent double flashing indicates an abnormal state (such as self-test failure). The above structure, resistance range, pin relationships, and semantic indications are all limited to this embodiment, without introducing additional multi-color LEDs, lamp driver ICs, or other display components.

[0072] The embodiments described above are merely illustrative of several implementations of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of protection of this application. Therefore, the scope of protection of this patent application should be determined by the appended claims.

Claims

1. A high-precision touchpad circuit based on a multi-channel MCU, characterized in that, It includes a main control processing module, an external storage module, and a touch electrode array module, wherein: the main control processing module is connected to the row electrodes of the touch electrode array module through its row driving port and to the column electrodes of the touch electrode array module through its sensing port; the external storage module is connected to the main control processing module and is used to store firmware and touch parameters.

2. The high-precision touchpad circuit based on a multi-channel MCU according to claim 1, characterized in that, The main control processing module uses a touch processor PCT1035QN, and its pin connections to peripheral components are as follows: The DRV1 to DRV23 pins of the PCT1035QN are connected to the row electrodes of the touch electrode array module via series current-limiting resistors; the SEN1 to SEN13 pins of the PCT1035QN are connected to the column electrodes of the touch electrode array module via series current-limiting resistors; the SPI_CS pin of the PCT1035QN is connected to the CS terminal of the external storage module, the SPI_CLK pin is connected to the CLK terminal of the external storage module, the SPI_MOSI pin is connected to the DI terminal of the external storage module, and the SPI_MISO pin is connected to the DO terminal of the external storage module; the I²C_SCL pin of the PCT1035QN... The PCT1035QN's I²C_SDA pin is connected to the connector's SCL terminal and then to VCC via a pull-up resistor, for HID-I²C communication with the host computer. The PCT1035QN's INT pin is connected to the connector's INT terminal and then to VCC via a pull-up resistor, for outputting a touch / data ready interrupt. The PCT1035QN's EN pin is connected to the connector's EN terminal and then to VCC via a pull-up resistor, for power-on and sleep control. The PCT1035QN's VIN pin is connected to VCC and then to signal ground via a decoupling capacitor; the VDD pin is connected to VCC and then to signal ground via a decoupling capacitor; and the GND pin is connected to signal ground.

3. The high-precision touchpad circuit based on a multi-channel MCU according to claim 2, characterized in that, The external storage module uses a ZB25WD40C, and its pin connections to peripheral components are as follows: the CS pin of the ZB25WD40C is connected to the SPI_CS pin of the main control processing module; the SCLK pin is connected to the SPI_CLK pin of the main control processing module; the SI pin is connected to the SPI_MOSI pin of the main control processing module; the SO pin is connected to the SPI_MISO pin of the main control processing module; the VCC pin is connected to the VCC power network and connected to signal ground via a parallel filter capacitor; the VSS pin is connected to signal ground; the WP pin is connected to VCC via a pull-up resistor; and the HOLD pin is connected to VCC via a pull-up resistor.

4. The high-precision touchpad circuit based on a multi-channel MCU according to claim 3, characterized in that, The touch electrode array module includes a 13×23 capacitive sensing matrix; each row electrode is connected to the DRV1~DRV23 pins of the PCT1035QN through a current-limiting resistor, and each column electrode is connected to the SEN1~SEN13 pins of the PCT1035QN through a current-limiting resistor; the resistance value of the current-limiting resistor is in the range of 100Ω~1kΩ.

5. The high-precision touchpad circuit based on a multi-channel MCU according to claim 4, characterized in that, It also includes a configuration circuit module, which includes a configuration resistor network connected between the GPIO1 to GPIO4 pins of the PCT1035QN and the VCC / signal ground; the combination of resistance values ​​of the configuration resistor network is used to set the device address and operating mode.

6. The high-precision touchpad circuit based on a multi-channel MCU according to claim 4, characterized in that, It also includes a communication interface module, which comprises: an I²C communication interface, consisting of the I²C_SCL and I²C_SDA signal lines of the PCT1035QN and connected to VCC via pull-up resistors; an SPI communication interface, consisting of the SPI_CLK, SPI_MOSI, SPI_MISO, and SPI_CS signal lines of the PCT1035QN; an interrupt output interface, consisting of the INT signal line of the PCT1035QN and connected to VCC via pull-up resistors; and an enable control interface, consisting of the EN signal line of the PCT1035QN and connected to VCC via pull-up resistors.

7. The high-precision touchpad circuit based on a multi-channel MCU according to claim 4, characterized in that, It also includes a switch and jumper configuration module, wherein: one end of the first switch S1 is connected to the reset / BOOT configuration pin of the main control processing module and the other end is connected to signal ground; one end of the second switch S2 is connected to the K1 function input pin of the main control processing module and the other end is connected to signal ground; jumpers JR1, JB1, and JC1 respectively connect the configuration pin of the main control processing module to VCC or to signal ground, for address / function selection and production test mode switching.

8. The high-precision touchpad circuit based on a multi-channel MCU according to claim 4, characterized in that, It also includes a test module, which includes test points T1 to T7, wherein: test point T1 is connected to the EN signal of the PCT1035QN; test point T2 is connected to the INT signal of the PCT1035QN; test point T3 is connected to the I²C_SDA signal of the PCT1035QN; test point T4 is connected to the I²C_SCL signal of the PCT1035QN; test point T5 is connected to the VCC power network; test point T6 is connected to the K1 signal of the PCT1035QN; and test point T7 is connected to GND.

9. The high-precision touchpad circuit based on a multi-channel MCU according to claim 4, characterized in that, It also includes a reset circuit module, which includes: a reset chip, the output of which is connected to the RST pin of the PCT1035QN; a manual reset button, one end of which is connected to the trigger terminal of the reset chip and the other end is connected to signal ground; and a power-on reset circuit, which consists of a resistor-capacitor network and is connected between VCC and the trigger terminal of the reset chip.

10. The high-precision touchpad circuit based on a multi-channel MCU according to claim 4, characterized in that, It also includes a status indicator module, which includes an LED indicator whose anode is connected to VCC through a current-limiting resistor and whose cathode is connected to the GPIO pin of the PCT1035QN; the GPIO pin is configured as an open-drain output mode to drive the LED indicator to indicate the working status.

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