A device for upgrading firmware of a serial port servo FPGA

Abstract

The utility model relates to servo FPGA firmware technical field, and disclose a kind of media and device of serial port upgrade servo FPGA firmware, including host computer PC, the output of host computer PC is connected with control panel FPGA by Mini USB port, and control panel FPGA is connected with FLASH memory chip by SPI interface.This media and device of serial port upgrade servo FPGA firmware, by utilizing the existing debugging port of servo driver, the rapid programming of FPGA firmware is realized, without disassembling shell or disassembling screw, make full use of servo driver internal preset debugging port as transmission medium, simplify the process of firmware upgrade, reduce the operation difficulty and maintenance cost, and the scheme has good expansibility, can adapt to future servo driver hardware upgrade and firmware version iteration, ensure the long-term compatibility and upgrade convenience of equipment, mean field engineer can upgrade firmware, program update anytime, anywhere, to improve the performance and function of servo driver, and will not be subject to physical access restrictions.

Description

Technical Field

[0001] This utility model relates to the field of servo FPGA firmware technology, specifically a device for serial port upgrading of servo FPGA firmware. Background Technology

[0002] Servo drives are an important component of modern industrial automation. Their performance largely depends on the control algorithms inside the drive, and FPGA chips are key to implementing these algorithms. Currently, servo drive designs generally adopt a dual-chip architecture of MCU + FPGA. The MCU is responsible for system control, while the FPGA undertakes tasks with extremely high real-time requirements, such as current loop calculation, PWM signal generation, and communication with the servo motor encoder.

[0003] Traditional servo drives require the servo FPGA chip to be programmed after the casing is removed. When there are many drives that need to be upgraded, the repeated disassembly operations will waste a lot of time, which will seriously affect the efficiency of debugging and maintenance. In addition, the disassembly process may damage the internal components of the drive, increasing maintenance costs and potentially affecting the normal operation of the drive. Utility Model Content

[0004] (a) Technical problems to be solved To address the shortcomings of existing technologies, this invention provides a device for upgrading servo FPGA firmware via serial port, thereby resolving the problems mentioned in the background section.

[0005] (II) Technical Solution To achieve the above objectives, this utility model provides the following technical solution: a device for upgrading servo FPGA firmware via serial port, comprising a host computer PC, wherein the output terminal of the host computer PC is connected to a control board FPGA via a Mini USB port, and the control board FPGA is connected to a FLASH storage chip via an SPI interface.

[0006] Preferably, the MX25L1636E chip is the peripheral FLASH memory chip of the FPGA, the CFG_SPICS signal is the chip select signal for SPI communication, the CFG_SPIMISO signal is the transmit signal for the FPGA master controller to send data to the FLASH chip, the CFG_SPICLK signal is the signal for the FLASH chip to return data to the FPGA master controller, and the CFG_SPICLK is the SPI clock signal.

[0007] Preferably, the ADM202EARNZ chip is an RS232 communication chip, the RS232-RXD signal is data sent from the PC host computer to the FPGA, and the RS232-TXD signal is signal data returned from the FPGA to the host computer.

[0008] Preferably, the FPGA chip is the LFE5U-25F chip from Lattice. The TDO_FPGA, TCK_FPGA, TDI_FPGA, and TMS_FPGA signals are the FPGA's JTAG download port. The CFG_SPIMOSI, CFG_SPIMISO, IO2, and IO3 are SPI communication signals. The CFG_0, CFG_1, and CFG_2 are configuration download modes.

[0009] Compared with the prior art, this utility model provides a device for serial port upgrade of servo FPGA firmware, which has the following advantages: This device for serial port upgrade of servo FPGA firmware realizes rapid burning of FPGA firmware by utilizing the existing debugging port of the servo driver, without disassembling the casing or removing screws. It makes full use of the pre-set debugging port inside the servo driver as a transmission medium, which simplifies the firmware upgrade process, reduces the difficulty of operation and maintenance costs, and the solution has good scalability, which can be adapted to future hardware upgrades and firmware version iterations of the servo driver, ensuring the long-term compatibility and upgrade convenience of the device. This means that field engineers can perform firmware upgrades and program updates anytime and anywhere to improve the performance and function of the servo driver without being restricted by physical access. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the principle structure of this utility model; Figure 2 This is a schematic diagram of the circuit structure of the MX25L1636E chip in this utility model; Figure 3 This is a schematic diagram of the circuit structure of the ADM202EARNZ chip in this utility model; Figure 4 This is a schematic diagram of the circuit structure of the LFE5U-25F chip in this utility model; Figure 5 This is a timing diagram of the RX receiving data of this utility model; Figure 6 This is a timing diagram of the TX data receiving of this utility model. Detailed Implementation

[0011] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0012] like Figure 1-6 As shown, this utility model provides a technical solution: a device for upgrading servo FPGA firmware via serial port, including a host computer PC, the output end of the host computer PC is connected to a control board FPGA via a Mini USB port, and the control board FPGA is connected to a FLASH storage chip via an SPI interface.

[0013] Furthermore, the MX25L1636E chip is the peripheral FLASH memory chip of the FPGA. The CFG_SPICS signal is the chip select signal for SPI communication, the CFG_SPIMISO signal is the transmit signal for the FPGA master controller to send data to the FLASH chip, the CFG_SPICLK signal is the signal for the FLASH chip to return data to the FPGA master controller, and the CFG_SPICLK is the SPI clock signal.

[0014] Specifically, when the FPGA needs to communicate with the FLASH chip, it pulls the signal low, and when the communication is over, it pulls it high. By controlling the CFG_SPICS signal, it ensures that only the target device responds when multiple devices share the SPI bus. The CFG_SPIMISO signal can transmit data when reading the stored content from the chip. In each clock cycle, it controls the sampling and transmission direction of the data to ensure that the data is transmitted in the correct timing. The CFG_SPICLK signal can control the sampling and transmission direction of the data in each clock cycle to ensure that the data is transmitted in the correct timing.

[0015] Furthermore, the ADM202EARNZ chip is an RS232 communication chip. The RS232-RXD signal is the data sent from the PC host computer to the FPGA, and the RS232-TXD signal is the signal data returned by the FPGA to the host computer.

[0016] Specifically, the ADM202EARNZ chip and RS232-RXD / TXD signals together enable RS232 serial communication between the FPGA and the PC host computer, providing the FPGA with a convenient interface with external devices. This eliminates the need to disassemble the servo housing and remove screws, greatly facilitating FPGA firmware upgrades for on-site debugging personnel.

[0017] Furthermore, the FPGA chip used is the Lattice LFE5U-25F chip. The TDO_FPGA, TCK_FPGA, TDI_FPGA, and TMS_FPGA signals are the FPGA's JTAG download port, CFG_SPIMOSI, CFG_SPIMISO, IO2, and IO3 are SPI communication signals, and CFG_0, CFG_1, and CFG_2 are configuration download modes.

[0018] Specifically, the TDO_FPGA, TCK_FPGA, TDI_FPGA, and TMS_FPGA signals are used for secure debugging, configuration loading, and boundary scanning of the FPGA, supporting rapid programming and testing. SPI communication is used for high-speed configuration loading or application storage data, ensuring rapid deployment and data access. The configuration download mode is controlled by multi-path configuration, allowing selection of different configuration sources or startup modes in different scenarios.

[0019] Working principle: First, when the system starts up, the FPGA initializes and configures itself via JTAG, storing the configuration information in internal registers or SRAM. Then, it enters normal operation, reading control signals from the host computer or FLASH, and writing or reading data via the SPI interface. Initially, the RX receives data in the "IDLE" state. When a falling edge appears on the data line, it jumps to the "START" state. The duration of the "START" state is 1 second as specified in the protocol. The duration of the data bit is determined by the counter. When the counter reaches one cycle, it jumps to the "RX_DATA" state, where the data is eight bits. After eight counting cycles, it jumps to the "STOP" state, indicating that one byte of data has been received. Finally, during the TX reception process, the FPGA starts data reception by monitoring the falling edge of the data line, entering the "START" state. It then parses the 8-bit data and the stop bit according to the preset counter cycle, completing the reception of one byte of data. The transmission process begins at the falling edge of the "START" state. In the "TX_DATA" state, the counter periodically outputs 8 bits of data until the "STOP" state, indicating that one byte of data has been sent. Through this timing control, the FPGA can accurately exchange and process data with the Flash memory chip and the host computer, thereby completing the functions of the entire system.

[0020] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A device for upgrading servo FPGA firmware via serial port, comprising a host computer (PC), characterized in that: The output of the host PC is connected to the control board FPGA via a Mini USB port, and the control board FPGA is connected to a FLASH storage chip via an SPI interface. The MX25L1636E chip is the peripheral FLASH memory chip of the FPGA. The CFG_SPICS signal is the chip select signal for SPI communication, the CFG_SPIMISO signal is the transmit signal for the FPGA master controller to send data to the FLASH chip, the CFG_SPICLK signal is the signal for the FLASH chip to return data to the FPGA master controller, and the CFG_SPICLK is the SPI clock signal. The ADM202EARNZ chip is an RS232 communication chip. The RS232-RXD signal is the data sent from the PC host computer to the FPGA, and the RS232-TXD signal is the signal data returned by the FPGA to the host computer. The FPGA chip used is the LFE5U-25F chip. The TDO_FPGA, TCK_FPGA, TDI_FPGA, and TMS_FPGA signals are the FPGA's JTAG download ports. CFG_SPIMOSI, CFG_SPIMISO, IO2, and IO3 are SPI communication signals. CFG_0, CFG_1, and CFG_2 are the configuration download modes.

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