Array substrate, display panel and display device

Abstract

The present disclosure relates to the technical field of display, and particularly relates to an array substrate, a display panel and a display device. The array substrate comprises a driving substrate, a first connector and a second connector, the first connector and the second connector are arranged at opposite ends of the driving substrate along a first direction and are electrically connected through a connection trace on the driving substrate. When two adjacent array substrates are spliced along the first direction, the first connector of one array substrate and the second connector of the other array substrate are connected in series. The present disclosure solves the problem of series connection difficulty between array substrates from the source by arranging the first connector and the second connector at opposite ends of the array substrate along the first direction. The present disclosure improves the problem of complicated connection trace and high cost of connection trace when each array substrate needs to be separately externally connected to the power supply, and also shortens the distance between two adjacent connectors on two adjacent array substrates, thereby further shortening the connection trace of the two array substrates connected in series to reduce the series connection cost.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to an array substrate, a display panel, and a display device. Background Technology

[0002] In current technologies for connecting multiple display panels, a common approach is to install a connection interface on the main control chip of each display panel and then connect these interfaces to adjacent display panels via traces. However, because the main control chip is relatively small on the display panel, longer traces are required to connect adjacent display panels, resulting in higher costs. Utility Model Content

[0003] The purpose of this application is to provide an array substrate, a display panel, and a display device that can solve the problem of difficult interconnection between array substrates from the source, shorten the traces connecting two array substrates, and reduce interconnection costs.

[0004] This disclosure provides an array substrate, including: Drive substrate; A first connector and a second connector are disposed at opposite ends of the drive substrate along a first direction, and the first connector and the second connector are electrically connected through connection traces on the drive substrate. When two adjacent array substrates are spliced ​​along the first direction, the first connector of one array substrate is connected in series with the second connector of the other array substrate.

[0005] In one exemplary embodiment of this disclosure, the driving substrate has a trace surface and a back surface disposed opposite to each other in its thickness direction, the connecting trace is disposed on the trace surface, and at least one of the first connector and the second connector is disposed on the back surface and electrically connected to the connecting trace through a through hole penetrating the driving substrate.

[0006] In one exemplary embodiment of this disclosure, the first connector is disposed in the first bonding area of ​​the wiring surface; The second connector is located on the back side of the drive substrate and is electrically connected to the connection trace through the first through hole in the drive substrate.

[0007] In an exemplary embodiment of this disclosure, both the first connector and the second connector are disposed on the back side of the driving substrate. The second connector is electrically connected to the connection trace through a first through hole in the driving substrate, and the first connector is electrically connected to the connection trace through a second through hole in the driving substrate.

[0008] In an exemplary embodiment of this disclosure, one side of the driving substrate in the thickness direction is a wiring surface, the wiring surface includes a pixel circuit area, a first bonding area and a second bonding area, the first bonding area and the second bonding area are located at opposite ends of the pixel circuit area in the first direction, the first connector is disposed on the first bonding area and the second connector is disposed on the second bonding area.

[0009] In one exemplary embodiment of this disclosure, at least one of the first connector and the second connector is embedded in the drive substrate.

[0010] This disclosure provides a display panel, including: Opposite substrate; An array substrate is disposed opposite to the opposing substrate along the thickness direction of the display panel. The array substrate includes a driving substrate, a first connector, and a second connector. The first connector and the second connector are disposed at opposite ends of the driving substrate along a first direction. The first connector and the second connector are electrically connected through connection traces on the driving substrate. When two adjacent array substrates are spliced ​​along the first direction, the first connector of one array substrate is connected in series with the second connector of the other array substrate.

[0011] In an exemplary embodiment of this disclosure, the driving substrate has a trace surface and a back surface disposed opposite to each other in the thickness direction of the display panel, and the opposing substrate is located on the side of the trace surface away from the back surface. At least one of the first connector and the second connector is disposed on the wiring surface, and its surface facing away from the driving substrate is not higher than the surface of the opposing substrate facing away from the driving substrate.

[0012] In an exemplary embodiment of this disclosure, the driving substrate has a trace surface and a back surface disposed opposite to each other in the thickness direction of the display panel, and a first bonding area is provided at one end of the trace surface, and the first connector is disposed in the first bonding area; The display panel also includes a main circuit board, which is disposed on the back side of the driving substrate and electrically connected to the first connector through a third through hole penetrating the driving substrate.

[0013] This disclosure provides a display device including a plurality of display panels as described above, the plurality of display panels being arranged along a first direction, and a first connector of one display panel being connected in series with a second connector of another adjacent display panel.

[0014] The technical solutions provided in this disclosure have at least the following advantages: This embodiment of the present disclosure provides a first connector and a second connector at opposite ends along a first direction on a driving substrate. When multiple array substrates are arranged along the first direction, the first connector on one array substrate is adjacent to the second connector on another array substrate. By connecting the first connector on one array substrate to the adjacent second connector on another array substrate in series, the problem of difficult series connection between array substrates can be solved from the source. This not only improves the problem of cumbersome wiring and high wiring cost when each array substrate needs to be connected to an external power supply, but also shortens the distance between two adjacent connectors on two adjacent array substrates, thereby further shortening the wiring of the two array substrates in series and reducing the series connection cost.

[0015] Furthermore, the array substrate in this embodiment can also be electrically connected to other items besides the array substrate via the first connector and the second connector to provide power to other items, thereby increasing the functionality of the array substrate and enhancing its added value.

[0016] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0019] Figure 1 A schematic diagram illustrating the interconnection of multiple electronic price tags in related technologies is shown.

[0020] Figure 2 A top view of a first embodiment of the array substrate is shown.

[0021] Figure 3 It shows Figure 2 A schematic diagram of a cross-sectional structure of a medium array substrate.

[0022] Figure 4 A second top view of the array substrate in an embodiment of this disclosure is shown.

[0023] Figure 5 A third top view of the array substrate in an embodiment of this disclosure is shown.

[0024] Figure 6 A fourth top view of the array substrate in an embodiment of this disclosure is shown.

[0025] Figure 7 A fifth top view of the array substrate in an embodiment of this disclosure is shown.

[0026] Figure 8 It shows Figure 7 A schematic diagram of a cross-sectional structure of a medium array substrate.

[0027] Figure 9 It shows Figure 7 Another cross-sectional view of the array substrate.

[0028] Figure 10 It shows Figure 2 Another cross-sectional view of the array substrate.

[0029] Figure 11 A top view of a first embodiment of the display panel is shown.

[0030] Figure 12 It shows Figure 11 A cross-sectional view of the central display panel.

[0031] Figure 13 A second top view of the display panel in an embodiment of this disclosure is shown.

[0032] Figure 14 It shows Figure 13 A cross-sectional view of the central display panel.

[0033] Figure 15 A third top view of the display panel in an embodiment of this disclosure is shown.

[0034] Figure 16 It shows Figure 15 A cross-sectional view of the central display panel.

[0035] Figure 17 This illustration shows a first cross-sectional view of the main circuit board and the main circuit board located on the back side of the driving substrate in an embodiment of this disclosure.

[0036] Figure 18 This illustration shows a second cross-sectional view of the main circuit board and the main circuit board located on the back side of the driving substrate in an embodiment of this disclosure.

[0037] Figure 19 A third cross-sectional view of the main circuit board and the main circuit board located on the back side of the driving substrate is shown in an embodiment of this disclosure.

[0038] Explanation of reference numerals in the attached figures: 100, Array substrate; 200, Opposing substrate; 300, Display panel; 1, Driving substrate; 11, First bonding area; 12, Second bonding area; 13, First connecting hole; 14, Third connecting hole; 15, Pixel circuit area; 2, First connector; 3, Second connector; 4, Chip-on film; 5, Main circuit board; X, First direction; Y, Second direction; Z, Vertical direction. Detailed Implementation

[0039] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0040] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0041] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0042] Currently, electronic shelf labels are electronic display devices with information transmission and reception functions. They are usually placed on shelves and combined with wireless communication modules (such as Bluetooth, WiFi, etc.) and low-power chips to realize data interaction with the back-end management system. They are used to display product prices, promotional information, pictures, QR codes, and other content in real time, which can reduce the workload of manually changing shelf labels and reduce operating costs.

[0043] There are two types of electronic shelf labels: e-ink screens and LCD screens. LCD screen electronic shelf labels support full-color display, can display high-definition videos, animations and pictures, with bright colors, high contrast and high refresh rate, which can quickly update the displayed content and is suitable for dynamic information display. However, LCD screens consume more power and require continuous power to maintain the display.

[0044] In related technologies, electronic shelf labels are displayed individually on the shelf, and each electronic shelf label needs to be equipped with an output power supply to light up. This not only leads to increased costs for pre-planning the wiring during the decoration, but also makes it easy for the wiring between the various electronic shelf labels and the output power supply to become tangled, increasing the difficulty of maintenance, and also affecting the aesthetics of the shelf location.

[0045] In addition, such as Figure 1 As shown, some current serialization technologies involve setting up a connection interface on the main control chip (SOC) in the electronic shelf label's core board, and then achieving serialization through the connection interface. However, for long, narrow electronic shelf labels (such as...),... Figure 1 (Electronic price tags extending in the first direction X). When multiple electronic price tags are arranged in series in the first direction X, the distance between adjacent connection interfaces on the main control chips of two adjacent electronic price tags is very large. Therefore, a longer trace is required to connect the two electronic price tags in series.

[0046] To address the aforementioned technical problems, this disclosure provides an array substrate 100, which may include: a driving substrate 1, a first connector 2, and a second connector 3. For example... Figure 2 and Figure 3 As shown, the first connector 2 and the second connector 3 can be disposed at opposite ends of the driving substrate 1 along the first direction X, and the first connector 2 and the second connector 3 are electrically connected through the connection traces on the driving substrate 1.

[0047] Specifically, when preparing the array substrate 100, the design of the connection traces connecting the first connector 2 and the second connector 3 can be completed on the driving substrate 1 first. Then, the first connector 2 and the second connector 3 can be set at opposite ends of the driving substrate 1 in the first direction X, and the first connector 2 and the second connector 3 can be connected to the connection traces on the driving substrate 1. The connection between the first connector 2, the second connector 3 and the connection traces can be used to realize the electrical conduction between the array substrate 100 and the corresponding main control chip.

[0048] In this embodiment of the present disclosure, when two adjacent array substrates 100 are spliced ​​along the first direction X, the first connector 2 of one array substrate 100 is connected in series with the second connector 3 of the other array substrate 100. The first connector 2 and the second connector 3 connected in series are adjacent to each other in the two adjacent array substrates 100.

[0049] In some embodiments, the driving substrate 1 has a thickness direction (i.e., Figure 3 The vertical (Z) side and the back side are arranged opposite each other. Multiple traces can be arranged on the trace surface of the driving substrate 1 to realize electrical conduction between the driving substrate 1 and other structures through the traces.

[0050] For example, the traces on the trace surface may include connection traces that are electrically connected to the first connector 2 and the second connector 3. By setting the connection traces, the first connector 2 and the second connector 3 can be connected to the main control chip that provides the required voltage to the array substrate 100.

[0051] Furthermore, the connection traces on the driver substrate 1 can also be connected to the main circuit board (PCB) 5. The first connector 2 and the second connector 3 can be connected to the main circuit board 5 via the connection traces and supply power to the power management unit (PMU) on the main circuit board 5. The power management unit can distribute power to the entire device, for example, to the logic board (T-ConBoard) of the display module or the display control circuit on the main circuit board 5. However, this disclosure is not limited to this; other traces besides the connection traces can be provided on the driver substrate 1 according to the actual situation.

[0052] It should be noted that, in the embodiments of this disclosure, the connection between the first connector 2 and the second connector 3 in two adjacent array substrates 100 can be achieved through wiring.

[0053] For example, the first connector 2 and the second connector 3 can be configured as a structure similar to a Type-C interface, with traces connecting to adjacent first connectors 2 and second connectors 3 on two adjacent array substrates 100 to achieve series connection of adjacent array substrates 100. Simultaneously, the array substrate 100 can also obtain external voltage through traces connected to the first connector 2 and the second connector 3 to power the corresponding main control chip. Then, the main control chip outputs voltage to power the array substrate 100, thus achieving electrical conduction between the series-connected array substrates 100. Of course, the first connector 2 and the second connector 3 can also be configured with structures other than Type-C interfaces, depending on the actual situation. The voltage output by the main control chip can be 12V, but is not limited to this; the voltage output by the main control chip can also be other values ​​besides 12V, depending on the actual situation.

[0054] In addition to connecting the first connector 2 and the second connector 3 in two adjacent array substrates 100 via wiring, this embodiment of the present disclosure can also configure one of the first connector 2 and the second connector 3 on the array substrate 100 as a male connector and the other as a female connector. When two adjacent array substrates 100 are arranged along the first direction X, the first connector 2 on one array substrate 100 can be directly inserted into the second connector 3 on the other array substrate 100. This not only achieves the series connection between two adjacent array substrates 100, but also reduces the cost of wiring in the array substrates 100. Furthermore, in this embodiment of the present disclosure, the direct connection between two adjacent array substrates 100 via adjacent first connector 2 and second connector 3 can enhance the stability of the connection between the two adjacent array substrates 100 and improve the problem of bending, deformation, or even damage that can easily occur when connecting the first connector 2 and the second connector 3 via wiring, as the wiring is relatively flexible. This can further reduce the maintenance cost when multiple array substrates 100 are connected in series.

[0055] That is, in this embodiment of the present disclosure, by providing a first connector 2 and a second connector 3 at opposite ends of the driving substrate 1 along the first direction X, when multiple array substrates 100 are arranged along the first direction X, the first connector 2 on one array substrate 100 is adjacent to the second connector 3 on another array substrate 100. By connecting the first connector 2 on one array substrate 100 to the adjacent second connector 3 on another array substrate 100 in series, the problem of difficult series connection between array substrates 100 can be solved from the source. While improving the problem of cumbersome wiring and high wiring cost when each array substrate 100 needs to be connected to an external power supply, the distance between two adjacent connectors on two adjacent array substrates 100 can also be shortened, thereby further shortening the wiring of connecting two array substrates 100 in series and reducing the series connection cost.

[0056] Furthermore, the array substrate 100 in this embodiment can also be electrically connected to other items besides the array substrate 100 through the first connector 2 and the second connector 3 to provide power to other items, thereby increasing the functionality of the array substrate 100 and enhancing its added value.

[0057] In some embodiments, at least one of the first connector 2 and the second connector 3 may be disposed on the back side and electrically connected to the connection trace through the through hole of the drive substrate 1.

[0058] For example, such as Figures 4 to 5 As shown, the routing surface may include a first bonding area 11, a first connector 2 may be disposed in the first bonding area 11 of the routing surface, and a second connector 3 may be disposed on the back side of the driving substrate 1. The second connector 3 is electrically connected to the connecting routing through a first through hole 13 penetrating the driving substrate 1.

[0059] It should be noted that the connection traces on the driving substrate 1 are usually set on the trace surface of the driving substrate 1. When the second connector 3 is set on the back side of the driving substrate 1, the connection traces on the trace surface of the driving substrate 1 need to be pulled to the back side of the driving substrate 1 to connect with the second connector 3 located on the back side of the driving substrate 1.

[0060] Specifically, the drive substrate 1 can be grouted to form a first connecting hole 13. The wiring is pulled to the back side of the drive substrate 1 through the first connecting hole 13. The second connector 3 is connected to the connecting wiring in the first connecting hole 13 to achieve electrical connection with the drive substrate 1.

[0061] In this embodiment of the disclosure, by placing the first connector 2 on the wiring surface of the driving substrate 1, it is convenient to directly connect the first connector 2 to the wiring surface of the driving substrate 1. This eliminates the cumbersome process of drilling holes on the back side of the driving substrate 1 when the first connector 2 is placed on the back side of the driving substrate 1 to achieve the connection between the first connector 2 and the wiring surface of the driving substrate 1. This can improve the fabrication efficiency of the array substrate 100 and reduce the fabrication cost.

[0062] However, this is not the only limitation. In some embodiments, when the second connector 3 is disposed on the routing surface of the driving substrate 1, the first connector 2 can also be disposed on the back side of the driving substrate 1. That is, both the first connector 2 and the second connector 3 can be disposed on the back side of the driving substrate 1. In this case, the second connector 3 can be electrically connected to the connecting trace through the first through hole 13 penetrating the driving substrate 1, and the first connector 2 can be electrically connected to the connecting trace through the second through hole penetrating the driving substrate 1.

[0063] The fabrication process of the second connecting hole can be the same as that of the first connecting hole 13, but it is not limited to this. The second connecting hole and the first connecting hole 13 can also adopt different fabrication processes, depending on the actual situation.

[0064] This embodiment of the present disclosure provides a second connecting hole on the driving substrate 1, so that the connection traces on the routing surface of the driving substrate 1 can be pulled to the back side of the driving substrate 1 through the second connecting hole, thereby enabling the first connector 2 to achieve electrical connection with the driving substrate 1 through the connection traces in the second connecting hole. Furthermore, by providing both the first connector 2 and the second connector 3 on the back side of the driving substrate 1, this embodiment of the present disclosure facilitates the series connection between multiple array substrates 100 arranged along the first direction X.

[0065] Specifically, when multiple array substrates 100 are placed on the same plane and arranged along the first direction X, by setting both the first connector 2 and the second connector 3 on the back side of the driving substrate 1, the first connector 2 in one array substrate 100 can be directly plugged into the second connector 3 of another array substrate 100 to achieve serial connection. Alternatively, the first connector 2 in one array substrate 100 can be connected to the second connector 3 of another array substrate 100 through wiring to achieve serial connection of two adjacent array substrates 100. In this case, the wiring is located on the back side of the array substrate 100, which can reduce the length of the wiring, reduce wiring costs, and improve the aesthetics of serial connection of multiple array substrates 100. At the same time, it can also improve the problem of wiring damage caused by bending the wiring to connect two adjacent array substrates 100 when the first connector 2 and the second connector 3 are located on the wiring surface and back side of the driving substrate 1, respectively.

[0066] It should be noted that in this embodiment of the present disclosure, the first connector 2 is located on the first bonding area 11 of the wiring surface, meaning that the first connector 2 overlaps with the first bonding area 11 when viewed from above the array substrate 100.

[0067] Specifically, from a top view of the array substrate 100, the first connector 2 can be partially placed on the first bonding area 11, and the other part can extend outward in a direction away from the center of the driving substrate 1 to protrude from the first bonding area 11. See reference [for more details]. Figure 4 As shown. But not limited to this, such as Figure 5 As shown, from a top view of the array substrate 100, the first connector 2 can also be completely placed within the first bonding area 11 to reduce the risk of the first connector 2 colliding with the external structure.

[0068] like Figures 6 to 9 As shown, in some embodiments, the routing surface of the driving substrate 1 may include a pixel circuit area 15, a first bonding area 11 and a second bonding area 12. The first bonding area 11 and the second bonding area 12 may be located at opposite ends of the pixel circuit area 15 in the first direction X. The first connector 2 may be disposed on the first bonding area 11 and the second connector 3 may be disposed on the second bonding area 12.

[0069] It should be noted that the second connector 3 being located on the second bonding area 12 means that, from the top view of the array substrate 100, the second connector 3 and the second bonding area 12 overlap.

[0070] For example, such as Figure 6 As shown, from a top view of the array substrate 100, the second connector 3 can be partially placed on the second bonding area 12, and another part can extend outward in a direction away from the center of the driving substrate 1 to protrude from the second bonding area 12. However, it is not limited to this; for example... Figure 7As shown, from a top view of the array substrate 100, the second connector 3 can also be completely placed within the second bonding area 12 to reduce the risk of the second connector 3 colliding with the external structure.

[0071] In this embodiment, by placing both the first connector 2 and the second connector 3 on the wiring surface of the driving substrate 1, it is convenient for the first connector 2 and the second connector 3 to be directly connected to the wiring surface of the driving substrate 1. This eliminates the cumbersome process of drilling holes on the back side of the driving substrate 1 to connect the first connector 2 and the second connector 3 to the wiring surface of the driving substrate 1 when the first connector 2 and the second connector 3 are placed on the back side of the driving substrate 1. This can improve the fabrication efficiency of the array substrate 100 and reduce the fabrication cost.

[0072] Furthermore, by placing both the first connector 2 and the second connector 3 on the trace surface of the driving substrate 1, it is also convenient to connect multiple array substrates 100 arranged along the first direction X, thereby reducing the length of the connecting traces, lowering the trace cost, and improving the aesthetics of connecting multiple array substrates 100 in series. At the same time, it can also improve the problem that when the first connector 2 and the second connector 3 are located on the trace surface and the back side of the driving substrate 1, respectively, the connection traces of the adjacent array substrates 100 need to be bent, which exacerbates the damage to the connection traces.

[0073] However, this is not the only option. In some embodiments, when the routing surface of the driving substrate 1 includes the pixel circuit area 15, the first bonding area 11, and the second bonding area 12, at least one of the first connector and the second connector can be disposed on the back side of the driving substrate. The specific arrangement can be determined according to the actual situation.

[0074] like Figure 3 and Figure 8 As shown, in some embodiments, surface mount technology (SMT) can be used to attach the first connector 2 to the surface of the driving substrate 1 (the surface here refers to the routing surface or back side of the driving substrate 1).

[0075] Similarly, in the embodiments disclosed herein, surface mount technology (SMT) and other techniques can be used to attach the second connector 3 to the surface of the driving substrate 1 (the surface here also refers to the routing surface or back side of the driving substrate 1).

[0076] But not limited to this, such as Figure 9 and Figure 10 As shown, in some embodiments, at least one of the first connector 2 and the second connector 3 can be embedded on the driving substrate 1 to reduce the overall thickness of the array substrate 100 and achieve a thinner and lighter array substrate 100.

[0077] For example, a first receiving groove may be provided on the driving substrate 1, and the first connector 2 may be at least partially embedded in the first receiving groove.

[0078] Furthermore, the orthographic projection of the first receiving groove onto the trace surface of the driving substrate 1 can be located within the first bonding area 11.

[0079] It should be noted that when the first connector 2 is disposed on the trace surface of the driving substrate 1, the first receiving groove can be disposed through the trace surface. When the first connector 2 is disposed on the back side surface of the driving substrate 1, the first receiving groove can be disposed through the back side surface of the driving substrate 1.

[0080] In this embodiment of the disclosure, the first receiving groove may be designed by making a cut in the driving substrate 1. After the first connector 2 is embedded in the first receiving groove, the first connector 2 can be bound to the connection wiring in the first receiving groove.

[0081] In addition, a second receiving groove may be provided on the driving substrate, and the second connector 3 may be at least partially embedded in the second receiving groove.

[0082] Furthermore, when the routing surface of the driving substrate 1 includes the first bonding area 11 but does not include the second bonding area 12, the orthographic projection of the second receiving groove on the routing surface of the driving substrate 1 does not coincide with the first bonding area 11. When the routing surface of the driving substrate 1 includes the first bonding area 11 and the second bonding area 12, the orthographic projection of the first receiving groove on the routing surface of the driving substrate 1 can be located in the first bonding area 11, and the orthographic projection of the second receiving groove on the routing surface of the driving substrate 1 can be located in the second bonding area 12.

[0083] It should be noted that when the second connector 3 is disposed on the trace surface of the drive substrate 1, the second receiving groove can be disposed through the trace surface. When the second connector 3 is disposed on the back side surface of the drive substrate 1, the second receiving groove can be disposed through the back side surface of the drive substrate 1.

[0084] In this embodiment, the second receiving groove can also be designed by making a cut in the driving substrate 1. After the second connector 3 is embedded in the second receiving groove, the second connector 3 can be bound to the connection wiring in the second receiving groove.

[0085] like Figures 11 to 12 As shown, this disclosure provides a display panel 300, which may include an opposing substrate 200 and an array substrate 100. The array substrate 100 and the opposing substrate 200 are disposed opposite to each other along the thickness direction of the display panel 300. The array substrate 100 may include a driving substrate 1, a first connector 2 and a second connector 3. The first connector 2 and the second connector 3 are disposed at opposite ends of the driving substrate 1 along a first direction X. The first connector 2 and the second connector 3 are electrically connected through connection traces on the driving substrate 1.

[0086] When two adjacent array substrates 100 are spliced ​​along the first direction X, the first connector 2 of one array substrate 100 is connected in series with the second connector 3 of the other array substrate 100, so that electrical conduction can be achieved between adjacent array substrates 100.

[0087] It should be noted that the thickness direction of the display panel 300 is the same as the thickness direction of the driving substrate 1.

[0088] The display panel 300 in this embodiment may be an electronic price tag, but is not limited thereto. The display panel 300 in this embodiment may also be any other panel with display function besides an electronic price tag.

[0089] In some embodiments, the opposing substrate 200 may be located on the side of the driving substrate 1 where the trace surface faces away from the back side.

[0090] like Figure 11 and Figure 12 As shown, when the trace surface of the driving substrate 1 includes the first bonding area 11 but does not include the second bonding area 12, the orthographic projection of the opposing substrate 200 on the driving substrate 1 can cover the areas other than the first bonding area 11.

[0091] like Figure 13 and Figure 14 As shown, when the trace surface of the driving substrate 1 includes the pixel circuit area 15, the first bonding area 11 and the second bonding area 12, the orthogonal projection of the opposing substrate 200 on the driving substrate 1 can cover the pixel circuit area 15.

[0092] In some embodiments, when at least one of the first connector 2 and the second connector 3 is located on the wiring surface, its surface away from the driving substrate 1 may not be higher than the surface of the opposing substrate 200 away from the driving substrate 1, thereby improving the problem of the overall film thickness of the display panel 300 being additionally increased due to the first connector 2 and / or the second connector 3.

[0093] In some embodiments, the length of the first binding area 11 along the first direction X can be equal to the length of the second binding area 12 along the first direction X, so as to improve the overall aesthetics of the display panel 300.

[0094] In some embodiments, the first connector 2 may be disposed in the middle of the first bonding area 11 to improve the connection stability between the first connector 2 and the driving substrate 1.

[0095] For example, the first connector 2 may be located at the middle of the drive substrate 1 along the second direction Y, which intersects with the first direction X.

[0096] Furthermore, such as Figure 11 As shown, the second direction Y can be perpendicular to the first direction X.

[0097] like Figure 13 and Figure 14 As shown, in this embodiment of the present disclosure, the first connector 2 and the second connector 3 can both be disposed in the middle of the driving substrate 1 along the second direction Y. When multiple array substrates 100 are connected in series through adjacent first connectors 2 and second connectors 3, the array substrates 100 are all connected to the middle of adjacent array substrates 100, thereby improving the stability of the connection between multiple array substrates 100.

[0098] However, this is not the only option. In this embodiment, the first connector 2 and the second connector 3 may also be located at positions other than the middle of the drive substrate 1 in the second direction Y. The specific location may vary depending on the actual situation.

[0099] In some embodiments, the display panel may include a main circuit board 5.

[0100] For example, such as Figure 15 and Figure 16 As shown, the main circuit board 5 can be disposed on the side of the first bonding area 11 away from the center of the drive substrate 1, and is electrically connected to the first connector 2.

[0101] Specifically, the display panel may also include a chip flip film (COF) 4, which may be partially placed on the first bonding area 11 and electrically connected to the driving substrate 1. The main circuit board 5 may be disposed on the side of the chip flip film 4 away from the array substrate 100 and electrically connected to the first connector 2 through the chip flip film 4.

[0102] In this embodiment, the molding process of the display panel 300 can be as follows: First, the circuit design is completed on the driving substrate 1, and the conductive design lines for the first connector 2 and the second connector 3 are reserved on the driving substrate 1. The conductive lines of the array substrate 100 and the conductive lines of the flip-chip film 4 are set in other positions. After completing the cell assembly process of the array substrate 100 and the opposing substrate 200, and completing the setting and bonding process of the polarizer, the first connector 2 and the second connector 3 are then electrically connected to the driving substrate 1.

[0103] It should be noted that when the first connector 2 is located in the middle of the driving substrate 1, the first connector 2 may occupy the setting area of ​​the flip-chip film 4 and the conductive lines.

[0104] To solve the above technical problems, such as Figures 17 to 19 As shown, in this embodiment of the present disclosure, the main circuit board 5 can be disposed on the back side of the driving substrate 1, and the main circuit board 5 can be electrically connected to the first connector 2 through the third through hole 14 penetrating the driving substrate 1.

[0105] Meanwhile, the flip-chip film 4 can also be disposed on the back side of the driving substrate 1. One end of the flip-chip film 4 is connected to the main circuit board 5, and the other end is connected to the connection trace in the third connecting hole 14.

[0106] That is, by placing the flip-chip film 4 and the main circuit board 5 on the back side of the driving substrate 1, the interference problem between the conductive lines of the first connector 2 and the conductive lines of the flip-chip film 4 can be improved in this embodiment. By providing the third connecting hole 14, the connection traces on the wiring surface of the driving substrate 1 can be pulled to the back side of the driving substrate 1, so that the main circuit board 5 can achieve electrical connection with the driving substrate 1 through the connection traces in the third connecting hole 14.

[0107] The preparation process of the third connecting hole 14 can be the same as that of the first connecting hole 13, but it is not limited to this. The third connecting hole 14 and the first connecting hole 13 can also adopt different preparation processes, depending on the actual situation.

[0108] This disclosure also provides a display device, which may include a plurality of display panels 300 as described above, the plurality of display panels 300 may be arranged along a first direction X, and a first connector 2 of one display panel 300 may be connected in series with a second connector 3 of another adjacent display panel 300.

[0109] It should be noted that in two adjacent display panels 300, the first connector 2 on one display panel 300 and the second connector 3 on the other display panel 300 are arranged adjacent to each other.

[0110] In the description of this specification, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0111] Furthermore, it should be noted that terms such as "upper," "lower," "left," and "right" are used only for distinction and convenience of description, and do not impose any positional limitations on the embodiments of the present invention. For example, "upper" in practice can refer to "lower," "left," or "right." In this disclosure, unless otherwise explicitly specified and limited, terms such as "assembly" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in this disclosure can be understood according to the specific circumstances.

[0112] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0113] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. An array substrate, characterized by, include: Drive substrate; A first connector and a second connector are disposed at opposite ends of the drive substrate along a first direction, and the first connector and the second connector are electrically connected through connection traces on the drive substrate. When two adjacent array substrates are spliced ​​along the first direction, the first connector of one array substrate is connected in series with the second connector of the other array substrate.

2. The array substrate of claim 1, wherein, The driving substrate has a trace surface and a back surface disposed opposite to each other in its thickness direction. The connection trace is disposed on the trace surface, and at least one of the first connector and the second connector is disposed on the back surface and is electrically connected to the connection trace through a through hole penetrating the driving substrate.

3. The array substrate of claim 2, wherein, The first connector is located in the first bonding area of ​​the wiring surface; The second connector is located on the back side of the drive substrate and is electrically connected to the connection trace through the first through hole in the drive substrate.

4. The array substrate of claim 2, wherein, Both the first connector and the second connector are disposed on the back side of the driving substrate. The second connector passes through the first through hole of the driving substrate and is electrically connected to the connection trace. The first connector is electrically connected to the connection trace through the second through hole of the driving substrate.

5. The array substrate of claim 1, wherein, The driving substrate has a routing surface on one side in the thickness direction. The routing surface includes a pixel circuit area, a first bonding area, and a second bonding area. The first bonding area and the second bonding area are located at opposite ends of the pixel circuit area in the first direction. The first connector is disposed on the first bonding area, and the second connector is disposed on the second bonding area.

6. The array substrate of claim 1, wherein, At least one of the first connector and the second connector is embedded in the drive substrate.

7. A display panel, characterized by include: Opposite substrate; An array substrate is disposed opposite to the opposing substrate along the thickness direction of the display panel. The array substrate includes a driving substrate, a first connector, and a second connector. The first connector and the second connector are disposed at opposite ends of the driving substrate along a first direction. The first connector and the second connector are electrically connected through connection traces on the driving substrate. When two adjacent array substrates are spliced ​​along the first direction, the first connector of one array substrate is connected in series with the second connector of the other array substrate.

8. The display panel of claim 7, wherein, The driving substrate has a trace surface and a back surface disposed opposite to each other in the thickness direction of the display panel, and the opposing substrate is located on the side of the trace surface away from the back surface. At least one of the first connector and the second connector is disposed on the wiring surface, and its surface facing away from the driving substrate is not higher than the surface of the opposing substrate facing away from the driving substrate.

9. The display panel of claim 7, wherein, The driving substrate has a trace surface and a back surface disposed opposite to each other in the thickness direction of the display panel. A first bonding area is provided at one end of the trace surface, and the first connector is disposed in the first bonding area. The display panel also includes a main circuit board, which is disposed on the back side of the driving substrate and electrically connected to the first connector through a third through hole in the driving substrate.

10. A display device, characterized by comprising: It includes a plurality of display panels as described in any one of claims 7 to 9, the plurality of display panels being arranged along the first direction, and the first connector of one display panel being connected in series with the second connector of another adjacent display panel.

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