A display board with optimized driver chip and wiring

Abstract

This invention provides a driver chip and a display board with optimized wiring, which can reduce the number of jumpers and traces on a single-layer or fewer-layer display board, and optimize the wiring space structure. The driver chip internally includes at least one set of signal transmission pipe components; these components receive one signal input to the driver chip, split the signal into at least two signals, and output them to the driver chip from at least two directions, providing signals to multiple cascaded driver chip groups connected to the driver chip in the at least two directions; wherein the at least two directions include a first routing direction and a second routing direction that are perpendicular to each other. This invention optimizes the wiring method of the display board, reduces production costs, and improves production efficiency, and can be used to produce display boards for backlight technology, direct-view technology, etc.

Description

Technical Field

[0001] This utility model relates to the field of overall structure of LED display panels. Specifically, this utility model relates to a display panel with optimized driver chip and wiring. Background Technology

[0002] In LED dot matrix display applications, LEDs and LED driver chips are often integrated onto a single substrate (usually a PCB or aluminum substrate). Therefore, power lines, driver signal lines, and control signal lines intersect, requiring a large number of trace layers. When heat dissipation or substrate limitations necessitate a single or fewer trace layers, jumpers are frequently used. Both increasing the number of trace layers and using jumpers increase system complexity and production costs. These drawbacks are particularly pronounced in scenarios with stringent requirements for thinness and low cost, such as small-pitch LED displays and backlight modules, severely restricting the application expansion of LED dot matrix display technology.

[0003] Therefore, there is an urgent need for a display board that can reduce the use of jumpers on single-layer or fewer wiring layers, reduce the number of traces on the board, and optimize the wiring space structure. Utility Model Content

[0004] Based on the existing technology, the objective of this utility model is to provide a driver chip and a display board with optimized wiring, which can reduce the number of jumpers and traces on a single-layer or fewer-layer display board and optimize the wiring space structure.

[0005] In a first aspect, this utility model provides a driver chip, which internally includes at least one set of signal transmission pipeline components. The signal transmission pipeline assembly is used to receive one signal input to the driver chip, and split the one signal into at least two signals and send them out from at least two directions to the driver chip, so as to provide signals to multiple cascaded groups of driver chips connected to the driver chip in the at least two directions respectively; Among them, the at least two directions include a first routing direction and a second routing direction that are perpendicular to each other.

[0006] Furthermore, the signal transmission conduit assembly includes at least two signal transmission conduits having a first signal transmission conduit and a second signal transmission conduit; The first signal transmission channel includes a first input port, a first output port, and a first transmission line connecting the first input port and the first output port; The second signal transmission channel includes a second input port, a second output port, and a second transmission line connecting the second input port and the second output port; The first input port and the second input port are respectively used to receive the one-channel signal; The first output port is used to send one of the at least two signals from one of the at least two directions, and the second output port is used to send the other of the at least two signals from the other of the at least two directions.

[0007] Furthermore, the first transmission line and / or the second transmission line includes a crossing section of wiring; Alternatively, the first transmission line and / or the second transmission line may further include a transmission control function component for implementing at least one of the following: controlling the on / off state of the transmission line, controlling the output delay time of the transmission line, and adjusting the performance parameters of the transmission line.

[0008] Furthermore, the driver chip includes input pins and an input interface; The input pin is used to input the signal. The input interface includes one input terminal and at least two output terminals; the input terminal is connected to the input pin; the at least two output terminals are respectively connected to at least two signal transmission channels of the signal transmission channel assembly.

[0009] Furthermore, the driver chip includes output pins and an output interface; The output pin is located on the side of the driver chip housing in any one of the at least two directions; The output interface is connected to the output pin and one of the at least two signal transmission channels of the signal transmission channel assembly, so as to output one of the at least two signals corresponding to any one of the directions from the output pin.

[0010] A second aspect of this utility model provides a display panel with optimized wiring, the display panel comprising: substrate; The driver chip as described in the first aspect of this utility model; and On-board traces are arranged on the substrate beside and / or below the driver chip, forming a plurality of driver chip cascade groups that are respectively connected to the driver chip in at least two directions having a first trace direction and a second trace direction, wherein the projections of the first trace direction and the second trace direction on the plane of the substrate intersect.

[0011] Furthermore, the on-board traces include: The first type of routing includes: Connecting segment traces are arranged on the substrate between the driver chips and do not intersect with other traces. These connecting segment traces connect to the crossing segment traces inside the driver chips. The second type of trace is arranged on the substrate below the driver chip along the first trace direction and / or the second trace direction.

[0012] Furthermore, the display panel includes: The power cord is arranged along the direction of the first trace via the second type of trace; and The display data signal lines are arranged along the first routing direction and the second routing direction via the first type of trace.

[0013] Furthermore, the display panel includes: The power cord is arranged along the first routing direction via the first type of routing and / or the second type of routing. The ground wire is arranged along the direction of the first wiring via the first type of wiring and / or the second type of wiring; and The display data signal lines are arranged along the first routing direction and the second routing direction via the first type of trace.

[0014] Furthermore, the display panel includes: The power cord is arranged along the first routing direction via the first type of routing and / or the second type of routing. The ground wire is arranged along the direction of the first wiring via the first type of wiring and / or the second type of wiring; Display data signal lines are arranged along the first routing direction and / or the second routing direction via the first type of trace; and Control signal lines are arranged along the first routing direction and / or the second routing direction via the first type of routing and / or the second type of routing.

[0015] This invention proposes a display board with optimized driver chip and wiring, which has at least the following advantages: First, it solves the problem of requiring a large number of jumpers on display boards with single or few wiring layers, while simplifying the structure and reducing the number of traces on the board, thereby reducing system complexity. Second, LEDs can be arranged on both sides of the driver chip, increasing the system integration of the display board. Finally, the traces can be used for bidirectional communication, reducing the number of return lines, further optimizing the structure of the display board, and reducing production costs. Attached Figure Description

[0016] To further illustrate the advantages and other features of the various embodiments of this utility model, a more specific description of the embodiments of this utility model will be presented with reference to the accompanying drawings. It is understood that these drawings depict only typical embodiments of this utility model and are therefore not intended to limit its scope. In the drawings, for clarity, identical or corresponding parts will be indicated by identical or similar reference numerals.

[0017] Figure 1 A schematic diagram of a driver chip in one embodiment of the present invention is shown.

[0018] Figure 2 A schematic diagram of a signal transmission pipe assembly in one embodiment of the present invention is shown.

[0019] Figure 3 A schematic diagram of the internal wiring and control components of the driver chip in one embodiment of the present invention is shown.

[0020] Figure 4 The diagram shows the input and output interfaces and pins of the driver chip in one embodiment of the present invention.

[0021] Figure 5 The diagram illustrates a wiring-optimized display panel that reduces the number of return lines through bidirectional communication signal lines, according to one embodiment of the present invention.

[0022] Figure 6 The diagram shows a preferred embodiment of the present invention, illustrating the arrangement of the driver chip, power lines, and display data signal lines in a wiring-optimized display panel.

[0023] Figure 7 The diagram shows a preferred embodiment of the present invention, illustrating the arrangement of the driver chip, power lines, ground lines, and display data signal lines of a wiring-optimized display panel.

[0024] Figure 8 This illustrates the wiring method of a single-layer / few-layer display panel in the prior art.

[0025] List of reference numerals 100 driver chip 101 Signal Transmission Pipe Assembly 102 chip pins 201 First Signal Transmission Pipe 201-1 First Input Port 201-2 First Output Port 201-3 First Transmission Line 201-4 First Crossing Section Route 201-5 First Transmission Control Function Component 202 Second Signal Transmission Pipe 202-1 Second Input Port 202-2 Second Output Port 202-3 Second Transmission Line 202-4 Second Crossing Section Route 202-5 Second Transmission Control Function Component 203 Input Interface 204 Input Pin 205 First Output Interface 206 First output pin 207 Second Output Interface 208 Second Output Pin 300 First Driver Chip 301 Display data signal line 302 power cord 303 Grounding wire 400 Second Driver Chip 500 Third Driver Chip 600 Fourth Driver Chip Detailed Implementation In this utility model, the various embodiments are merely intended to illustrate the solution of this utility model and should not be construed as limiting.

[0026] In the description of this utility model, unless otherwise explicitly specified and limited, the terms "connected," "linked," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0027] In this invention, unless otherwise specified, "arranged on," "arranged above," and "arranged on top of" do not exclude the possibility of an intermediate element between them. Furthermore, "arranged on or above" merely indicates the relative positional relationship between two components, and in certain cases, such as when the product orientation is reversed, it can also be converted to "arranged below or under," and vice versa.

[0028] It should be noted that the components in the various figures may be shown exaggeratedly for illustrative purposes and are not necessarily to scale. In each figure, the same reference numerals are used for components that are identical or have the same function.

[0029] In this utility model, unless otherwise specified, the quantifiers “one” and “one” do not exclude scenarios involving multiple elements.

[0030] In this invention, the terms "first side" to "fourth side" refer to the sides containing the four edges in the two-dimensional structure of the driver chip. Specifically, the first side is opposite to the second side, and the third side is opposite to the fourth side. Furthermore, the third side is adjacent to both the first and second sides, and the fourth side is adjacent to both the first and second sides.

[0031] It should also be noted that, in the embodiments of this utility model, for clarity and simplicity, only a portion of the components or parts may be shown. However, those skilled in the art will understand that, under the teachings of this utility model, necessary components or parts can be added according to specific scenario requirements. Furthermore, unless otherwise stated, features in different embodiments of this utility model can be combined with each other. For example, a feature in the second embodiment can replace a corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment will also fall within the scope of disclosure or description of this application.

[0032] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0033] In a first aspect, this utility model provides a driver chip that includes at least one set of signal transmission pipe components. The signal transmission pipeline assembly is used to receive one signal input to the driver chip, and split the one signal into at least two signals and send them out from at least two directions to the driver chip, so as to provide signals to multiple cascaded groups of driver chips connected to the driver chip in the at least two directions respectively; Among them, the at least two directions include a first routing direction and a second routing direction that are perpendicular to each other.

[0034] The driver chip described above has at least the following advantages: The signal transmission pipeline assembly can split one signal into at least two signals and output the signal to the driver chip from at least two directions, thereby providing signals to multiple driver chips in a cascaded group connected to the driver chip in these two directions.

[0035] Figure 1 A schematic diagram of a driver chip in one embodiment of this utility model is shown. Figure 1As shown, in one embodiment of this utility model, the driver chip 100 internally has at least one signal transmission channel assembly 101. The signal transmission channel assembly 101 is connected to a chip pin 102 on one side of the driver chip, receives one signal input to the driver chip 100, and internally divides the signal into at least two mutually perpendicular routing directions, outputting them to the driver chip 100. For example, as... Figure 1 As shown, the first routing direction can be +X, and the second routing direction can be +Y. One signal is input to the driver chip 100 and output at least along the first and second routing directions, providing signals to multiple driver chips in a cascaded group connected to the driver chip 100 in the at least two directions.

[0036] In one embodiment of this utility model, the signal transmission pipeline assembly 101 is connected to a chip pin 102 on one side of the driver chip, receives one signal input to the driver chip 100, and internally divides this signal into at least three signals along a first routing direction, a second routing direction, and a third routing direction, outputting them to the driver chip 100. The first routing direction is +X, the second routing direction is +Y, and the third routing direction is -X. The input signal to the driver chip 100 and output along the first, second, and third routing directions provides signals to multiple driver chips in a cascaded group connected to the driver chip 100 in each of the three directions.

[0037] Those skilled in the art should understand that, in other embodiments of this utility model, in addition to the mutually perpendicular first routing direction (+X), second routing direction (+Y), and third routing direction (-X), the newly added signal transmission channels can split a single input signal into multiple signals for other preset directions within the substrate plane (such as specific angle directions set based on the display board wiring requirements), and output them to the corresponding cascaded driver chip groups, providing signal support for cascaded chips in more directions. Such adjustments in quantity and expansion of direction do not depart from the core concept of this utility model and remain within the protection scope of this utility model.

[0038] In one embodiment of the present invention, the signal transmission pipe assembly includes at least two signal transmission pipes having a first signal transmission pipe and a second signal transmission pipe; The first signal transmission channel includes a first input port, a first output port, and a first transmission line connecting the first input port and the first output port; The second signal transmission channel includes a second input port, a second output port, and a second transmission line connecting the second input port and the second output port; The first input port and the second input port are respectively used to receive the one-channel signal; The first output port is used to send one of the at least two signals from one of the at least two directions, and the second output port is used to send the other of the at least two signals from the other of the at least two directions.

[0039] In one embodiment of this utility model, the signal transmission pipe assembly has at least the following advantages: By using the signal transmission channel components arranged inside the driver chip as described above, it is possible to achieve... The driving chip outputs the same or different signals in two mutually perpendicular directions.

[0040] Figure 2 A schematic diagram of a signal transmission pipe assembly according to one embodiment of the present invention is shown. Figure 2 As shown, in one embodiment of this utility model, the signal transmission channel assembly 101 includes a first signal transmission channel 201 and a second signal transmission channel 202. Specifically, the first signal transmission channel 201 includes a first input port 201-1 disposed on a first side of the driver chip, a first output port 201-2 disposed on a second side of the driver chip opposite to the first side, and a first transmission line 201-3 connecting the first input port 201-1 and the first output port 201-2. The second signal transmission channel 202 includes a second input port 202-1 disposed on the first side of the driver chip, a second output port 202-2 disposed on a third side of the driver chip adjacent to the first side, and a second transmission line 202-3 connecting the second input port 202-1 and the second output port 202-2.

[0041] In one embodiment of this invention, the signal transmission pipe assembly 101 described above can be used to output at least two signals from two mutually perpendicular directions. For example, as Figure 2 As shown, the signal output directions are +X and +Y. In an embodiment of this invention (not shown), the signal output directions are -X and +Y.

[0042] In one embodiment of the present invention, at least two signals include a first signal, a second signal, and a third signal output in different directions, and the first signal to the third signal may be the same or different.

[0043] In one embodiment of this utility model, the first signal is transmitted along the +Y direction through the first output port 201-2.

[0044] In one embodiment of the present invention, the second signal is sent along the +X direction through the second output port 202-2, or the third signal is sent from the -X direction through the second output port 202-2.

[0045] Those skilled in the art should understand that in other embodiments of this utility model, the signal transmission pipe assembly 101 may include three or more signal transmission pipes. The structural design of these signal transmission pipes can refer to the core logic of the first signal transmission pipe 201 and the second signal transmission pipe 202, that is, each newly added signal transmission pipe includes an independent input port, an output port, and a transmission line connecting the two, and the input ports of all signal transmission pipes are connected to the input interface of the driver chip 100 to receive the same input signal. Such adjustments in quantity do not depart from the core concept of this utility model and still fall within the protection scope of this utility model.

[0046] In one embodiment of the present invention, the first transmission line and / or the second transmission line includes a crossing section of wiring.

[0047] In one embodiment of this utility model, the first transmission line and / or the second transmission line may further include a transmission control function component to achieve fine-grained control of the line operating status. This type of control function achieves at least one of the following three: First, it controls the on / off state of transmission lines. For example, by embedding one or more high-performance switching elements (such as semiconductor relays, MOSFET switches, etc.) in the transmission lines, rapid switching of line connection states can be achieved. This function is particularly important in system redundancy design—when the main line fails, it can switch to the backup line to ensure the continuity of signal transmission; in low-power scenarios, it can also cut off the power supply path of idle lines to reduce unnecessary energy consumption.

[0048] Second, it controls the output delay time of the transmission line. For example, with the help of registers or other similar dedicated delay control devices, the signal output time of the transmission line can be calibrated at the microsecond or even nanosecond level. This feature plays a crucial role in high-speed synchronous systems, ensuring time alignment of multiple signals at the receiving end by compensating for the transmission delay of different lines. In timing-sensitive communication protocols, the stability of data transmission can be improved by dynamically adjusting the delay parameters to optimize signal setup and hold times.

[0049] Third, the performance parameters of the transmission line can be adjusted. By integrating components such as configurable resistor networks and variable capacitor arrays, core parameters such as the characteristic impedance and bandwidth of the transmission line can be adjusted in real time. In high-frequency signal transmission, the parasitic capacitance of the line can be adjusted to expand the bandwidth; while in noise-sensitive environments, electromagnetic interference (EMI) can be reduced and signal integrity improved by optimizing impedance matching.

[0050] In one embodiment of this utility model, the crossing section routing and transmission control function component has at least the following advantages: The first transmission line and / or the second transmission line can be installed inside the driver chip through hardware and / or software, and the transmission lines and signal transmission can be controlled through the transmission control function component.

[0051] Figure 3 This diagram illustrates the internal wiring and control components of the driver chip in one embodiment of the present invention. Figure 3 As shown, in one embodiment of the present invention, the first transmission line 201-3 includes a first crossing section trace 201-4 and a first transmission control function component 201-5, and the second transmission line 202-3 includes a second crossing section trace 202-4 and a second transmission control function component 202-5. The first crossing section trace 201-4 is configured to connect to a first input port 201-1 and a first output port 201-2, and is connected thereto to the first transmission control function component 201-5. The second crossing section trace 202-4 is configured to connect to a second input port 202-1 and a second output port 202-2, and is connected thereto to the second transmission control function component 202-5. The first transmission control function component 201-5 and the second transmission control function component 202-5 are configured to implement at least one of the following: Controlling the on / off state of the transmission line, for example, the first transmission control function component 201-5 and / or the second transmission control function component 202-5 can be a switching unit; The output delay time of the control transmission line can be, for example, the first transmission control function component 201-5 and / or the second transmission control function component 202-5 can be an RC delay circuit structure, a delay phase-locked loop and / or a register; Adjusting the performance parameters of the transmission line, for example, the first transmission control function component 201-5 and / or the second transmission control function component 202-5 can be resistors or capacitors.

[0052] In one embodiment of this utility model, the driver chip includes an input pin and an input interface. The input pin is used to input the one-channel signal; The input interface includes one input terminal and at least two output terminals; the input terminal is connected to the input pin; the at least two output terminals are respectively connected to at least two signal transmission channels of the signal transmission channel assembly.

[0053] In one embodiment of this utility model, the input interface can adopt diverse structural designs to adapt to different application scenarios and signal access requirements. Specifically, the input interface may include a pad structure. This type of direct physical connection component can achieve a stable electrical connection with an external signal source through wire bonding, soldering, or other methods. It is particularly suitable for scenarios requiring a reliable fixed connection, and its structure is simple while ensuring good signal transmission integrity.

[0054] Furthermore, the input interface can also integrate switching control elements such as multiplexers (MUX). Through the configuration of the multiplexer, the input interface can selectively access multiple signals, allowing for flexible signal switching without frequent hardware changes. By controlling the selection state of the multiplexer, signals can be received and transmitted in an orderly manner, simplifying the external wiring complexity of the system and improving the interface's expandability and flexibility.

[0055] The two structural forms mentioned above can be used individually or in combination according to actual needs, so that the input interface can maintain structural simplicity while having stronger adaptability to different scenarios.

[0056] In one embodiment of this utility model, the driver chip includes output pins and an output interface; The output pin is located on the side of the driver chip housing in any one of the at least two directions; The output interface is connected to the output pin and one of the at least two signal transmission channels of the signal transmission channel assembly, so as to output one of the at least two signals corresponding to any one of the directions from the output pin.

[0057] In one embodiment of this utility model, the configuration of the input interface, output interface, input pins, and output pins has at least the following advantages: The above configuration enables the driver chip to output signals in multiple directions.

[0058] Figure 4 This diagram illustrates the input and output interfaces and pins of the driver chip in one embodiment of the present invention. Figure 4 As shown, in one embodiment of this utility model, the input interface 203 is connected to the input pin 204, and is also connected to the first input port 201-1 and the second input port 202-1.

[0059] like Figure 4 As shown, in one embodiment of this utility model, the first output interface 205 is connected to the first output port 201-2 and is connected to the first output pin 206. The second output interface 207 is connected to the second output port 202-2 and is connected to the second output pin 208.

[0060] The first output interface 205 and the first output pin 206 are arranged on the second side of the driver chip near the +Y direction, so that the first output pin 206 outputs a signal along the +Y direction, and the second output interface 207 and the second output pin 208 are arranged on the third side of the driver chip near the +X direction, so that the second output pin 208 outputs a signal along the +X direction.

[0061] Alternatively, in one embodiment of the present invention, the first output interface 205 and the first output pin 206 are arranged on the second side of the driver chip near the +Y direction, so that the first output pin 206 outputs a signal along the +Y direction, and the second output interface 207 and the second output pin 208 are arranged on the fourth side of the driver chip near the -X direction, so that the second output pin 208 outputs a signal along the -X direction.

[0062] Those skilled in the art should understand that in other embodiments of this utility model, the number of output interfaces and output pins of the driver chip can be expanded to three or more groups according to the actual distribution requirements of the cascaded driver chip group on the display board, and the signal transmission pipe assembly 101 can be simultaneously equipped with supporting sub-units such as a third signal transmission pipe and a fourth signal transmission pipe. The design logic of these newly added output interfaces and output pins can refer to the structure of the first output interface 205, the second output interface 207 and their corresponding pins. Such expansion of quantity and adjustment of position based on actual application scenarios do not depart from the core concept of this utility model and still fall within the protection scope of this utility model.

[0063] A second aspect of this utility model provides a display panel with optimized wiring, the display panel comprising: substrate; The driver chip as described in the first aspect of this utility model; and On-board traces are arranged on the substrate beside and / or below the driver chip, forming a plurality of driver chip cascade groups that are respectively connected to the driver chip in at least two directions having a first trace direction and a second trace direction, wherein the projections of the first trace direction and the second trace direction on the plane of the substrate intersect.

[0064] The second aspect of this utility model provides a display panel with optimized wiring, which has at least the following advantages: By driving the internal wiring of the chip and the wiring on the board, the problem of wiring crossings that necessitate the use of jumpers can be reduced (or preferably avoided).

[0065] In one embodiment of this utility model, the substrate is an aluminum substrate or a printed circuit board.

[0066] In one embodiment of the present invention, the driver chip includes at least one set of signal transmission pipeline components. The signal transmission pipeline components are used to receive one signal input to the driver chip, and split the one signal into at least two signals and send them out from at least two directions to the driver chip, so as to provide signals to a plurality of driver chip cascade groups connected to the driver chip in a first routing direction and a second routing direction respectively.

[0067] In one embodiment of this utility model, the signal transmission channel assembly of the driver chip includes at least two signal transmission channels having a first signal transmission channel and a second signal transmission channel. The first signal transmission channel includes a first input port, a first output port, and a first transmission line connecting the first input port and the first output port. The second signal transmission channel includes a second input port, a second output port, and a second transmission line connecting the second input port and the second output port. The first input port and the second input port are respectively used to receive one of the at least two signals; the first output port is used to transmit one of the at least two signals from one of the at least two directions, and the second output port is used to transmit the other of the at least two signals from the other of the at least two directions.

[0068] In one embodiment of the present invention, the first transmission line and / or the second transmission line includes a crossing section; or, the first transmission line and / or the second transmission line further includes a transmission control function component for implementing at least one of the following: controlling the on / off state of the transmission line, controlling the output delay time of the transmission line, and adjusting the performance parameters of the transmission line.

[0069] In one embodiment of this invention, multiple driver chips are cascaded in the first routing direction, and the multiple driver chips are connected to each other via on-board traces. Similarly, multiple driver chips are cascaded in the second routing direction, and the multiple driver chips are connected to each other via on-board traces. This forms a two-dimensional transmission link structure for the cascaded driver chips. Compared to the case where all driver chips are connected in series to form a single cascade string, the two-dimensional transmission link structure of this invention can reduce the number of cascaded driver chips, reduce signal transmission distortion, and does not require increasing the number of interfaces of the control chip, thus reducing the number of traces and the wiring difficulty. For example, for an m×n driver chip array, if connected in series to form a single cascade string, the longest cascade string is m×n (the total number of driver chips in the array). If the two-dimensional transmission link structure of this invention is used, the longest cascade string can be reduced to m+n-1.

[0070] Specifically, along the first routing direction, the output pin of the preceding driver chip is connected to the input pin of the following driver chip via on-board traces, and in the second routing direction perpendicular to the first routing direction, the output pin of the preceding driver chip is connected to the input pin of the following driver chip via on-board traces. Alternatively, in the first routing direction, the on-board traces connect the input terminals of all driver chips cascaded in that direction, and in the second routing direction, the on-board traces connect the input terminals of all driver chips cascaded in that direction. Through one of these methods, a cascaded series of multiple driver chips connected to the driver chip in at least two directions, namely the first and second routing directions, is formed.

[0071] In one embodiment of this utility model, the on-board traces include: The first type of routing includes: Connecting segment traces are arranged on the substrate between the driver chips and do not intersect with other traces. These connecting segment traces connect to the crossing segment traces inside the driver chips. The second type of trace is arranged on the substrate below the driver chip along the first trace direction and / or the second trace direction.

[0072] The on-board wiring according to one embodiment of the present invention has at least the following advantages: By using the first type of routing and / or the second type of routing, the number of traces on the board is reduced, and the use of jumpers is reduced (or preferably avoided).

[0073] In one embodiment of the present invention, the plurality of driver chips are cascaded along a first trace direction and / or a second trace direction and are configured to control and manage LEDs. The driver chips are interconnected by traces on the board and the traces do not intersect each other.

[0074] In one embodiment of this utility model, the driver chip receives externally input display data signals (such as RGB color data) and control signals (timing signals, enable signals), and converts them into driving signals that the LEDs can recognize; it transmits synchronization signals (such as timing signals) through traces to ensure that the LED arrays controlled by adjacent chips "simultaneously light up / turn off", avoiding display gaps.

[0075] The driver chip receives various external input signals through different pins, and the signal source is strongly correlated with the trace type. Specifically, the various signals may include: Power signal: Receives external power input through the chip's power pin to power the chip's internal circuitry; Ground signal: Grounded through the grounding pin to reduce signal interference and ensure power supply stability; Display data signals / control signals: Receives signals output from an external controller via communication pins; and Distribution of display data signals: The cascaded chips receive the display data of their respective areas according to the "segmentation control" logic, realizing modular control of large-area display panels.

[0076] In this invention, the trace also includes a third type of trace, which is arranged on one and / or both sides of the driver chip and configured to connect to the LED and / or ground. It has at least the following advantages: LEDs can be placed on both sides of the driver chip, increasing the system integration and space utilization of the display panel.

[0077] Figure 5 A schematic diagram of a wiring-optimized display panel according to one embodiment of the present invention is shown. Specifically, as... Figure 5 As shown, in one embodiment of the present invention, the display panel further includes a third type of trace for connecting to each LED, or the third type of trace may also be connected to ground GND.

[0078] like Figure 5 As shown, in one embodiment of the present invention, a display board with optimized wiring is provided, in which the driver chips are connected by bidirectional signal lines, and the chip pins of the driver chips on opposite sides of the second routing direction are connected to third-type traces, thereby allowing multiple LEDs to be symmetrically arranged on both sides of the driver chips.

[0079] In this invention, the term "LED" refers to any system capable of receiving an electrical signal and generating light color in response to that signal. Therefore, the term "LED" should be understood to include all types of light-emitting diodes, light-emitting polymers, semiconductor dies that generate light in response to current, organic LEDs, electroluminescent strips, light-emitting silicon-based structures, and other such systems. In one embodiment, "LED" may refer to a single light-emitting diode package having multiple individually controlled semiconductor dies. It should also be understood that the term "LED" does not limit the type of LED package. The term "LED" includes packaged LEDs, unpackaged LEDs, surface-mount LEDs, chip-on-a-board LEDs, and all other configurations of LEDs. The term "LED" also includes LEDs packaged with or associated with a phosphor, wherein the phosphor can convert energy from the LED into different wavelengths. The LED can be implemented as an RGB LED, and an RGB LED can include red, green, and blue LEDs. Furthermore, in addition to RGB LEDs, the LED may also include a white LED. In some examples, the LED can be implemented as a microLED. Here, a microLED is an LED with a size of approximately 5 to 100 micrometers, which is a microLED that emits light independently without a color filter.

[0080] In one embodiment of the present invention, the first type of trace and / or the second type of trace are configured for bidirectional communication.

[0081] In this invention, the first type of trace and / or the second type of trace can be used for bidirectional communication, which has at least the following advantages: In traditional trace designs, signal lines are mostly for unidirectional communication, requiring separate return lines for signal transmission. In this invention, the first type of trace and / or the second type of trace can be configured for bidirectional communication, reducing additional return lines, lowering trace density on the board, and reducing production costs.

[0082] In one embodiment of this utility model, the display panel includes: A power line, arranged along the direction of the first trace via the second type of trace, and configured to transmit a power signal; and The display data signal line is arranged along the first routing direction and / or the second routing direction via the first type of trace, and is configured to transmit display data signals.

[0083] The display panel according to the above embodiments has at least the following advantages: This system enables routing of power signal lines and display data signal lines among cascaded driver chips, with no direct intersections and no need for jumpers. Simultaneously, it achieves efficient transmission of power signals and display data signals.

[0084] Figure 6 This diagram illustrates a preferred embodiment of the present invention, showing the arrangement of the driver chip, power lines, and display data signal lines in a wiring-optimized display panel. Specifically, as shown... Figure 6 As shown: The driver chips are cascaded along the first trace direction and the second trace direction.

[0085] Specifically, the driver chip includes at least a first driver chip 300, a second driver chip 400, a third driver chip 500, and a fourth driver chip 600. The first driver chip 300 and the second driver chip 400 are arranged sequentially along a first trace direction, the third driver chip 500 is arranged relative to the first driver chip 300 in a second trace direction, and the fourth driver chip 600 is arranged relative to the second driver chip 400 in the second trace direction.

[0086] The power cable 302 is configured as a second type of trace and is arranged along the first trace direction.

[0087] Specifically, one power line 302 connects to the chip pins on the first side of the first driver chip 300 and the chip pins on the first side of the second driver chip 400, and is arranged on the substrate below the driver chip; and another power line 302 connects to the chip pins on the first side of the third driver chip 500 and the chip pins on the first side of the fourth driver chip 600, and is arranged on the substrate below the driver chip. The display data signal line 301 is configured as a first type of trace and is arranged along the first trace direction and the second trace direction.

[0088] Specifically, in the first routing direction, the display data signal line 301 is arranged as follows: it connects the chip pins on the first side and the second side of the first driver chip 300, and is routed internally within the chip via a crossover trace. Subsequently, it connects the chip pins on the second side of the first driver chip 300 and the chip pins on the first side of the second driver chip 400. It also connects the chip pins on the first side and the second side of the second driver chip 400, and is routed internally within the chip via a crossover trace. This achieves the transmission of the display data signal in the first routing direction.

[0089] In the second routing direction, the display data signal lines are arranged as follows: connecting the chip pins on the first side and the third side of the first driver chip 300, and routing them internally within the chip via crossover traces. Subsequently, they are connected via the chip pins on the third side of the first driver chip 300 and the chip pins on the fourth side of the third driver chip 500. Similarly, connecting the chip pins on the fourth side of the third driver chip 500 and the chip pins on the third side of the third driver chip 500, and routing them internally within the chip via crossover traces. The display data signal lines between the second driver chip 400 and the fourth driver chip 600 are arranged in the same manner to achieve the transmission of display data signals in the second routing direction.

[0090] In one embodiment of this utility model, the display panel includes: A power line, arranged along the first routing direction via the first type of routing and / or the second type of routing, and configured to transmit power signals; A ground wire, arranged along the direction of the first trace via the first type of trace and / or the second type of trace, and configured for grounding; and The display data signal line is arranged along the first routing direction and / or the second routing direction via the first type of trace, and is configured to transmit display data signals.

[0091] The display panel according to the above embodiments has at least the following advantages: The wiring method described above enables the routing of power signal lines, ground lines, and display data signal lines among cascaded driver chips. The wiring does not cross directly and does not require jumpers, further optimizing the wiring method of the display board.

[0092] Figure 7 This diagram illustrates a preferred embodiment of the present invention, showing the arrangement of the driver chip, power lines, ground lines, and display data signal lines of a wiring-optimized display panel. Specifically, as shown... Figure 7 As shown: The driver chip includes at least a first driver chip 300, a second driver chip 400, a third driver chip 500, and a fourth driver chip 600. The first driver chip 300 and the second driver chip 400 are arranged sequentially along a first trace direction, the third driver chip 500 is arranged relative to the first driver chip 300 in a second trace direction, and the fourth driver chip 600 is arranged relative to the second driver chip 400 in a second trace direction.

[0093] Power line 302 connects the chip pins on the first side and the second side of the first driver chip 300, and is routed internally within the chip via a crossover trace. Subsequently, it connects the chip pins on the second side of the first driver chip 300 and the chip pins on the first side of the second driver chip 400. It also connects the chip pins on the first and second sides of the second driver chip 400, and is routed internally within the chip via a crossover trace. Another power line 302 connects the chip pins on the first side of the third driver chip 500 and the chip pins on the first side of the fourth driver chip 600, and is disposed on the substrate below the driver chips.

[0094] The ground wire 303 is arranged in the same manner as the power wire 302, and the power wire 302 and the ground wire 303 do not cross each other.

[0095] The display data signal line 301 is configured as a first-type trace, arranged along the first trace direction and / or the second trace direction in different driver chips. The specific arrangement of the display data signal line and... Figure 6 The arrangement of the data signal lines is the same as that shown in the middle.

[0096] In a preferred embodiment of this utility model, the display panel includes: A power line, arranged along the first routing direction via the first type of routing and / or the second type of routing, and configured to transmit power signals; The ground wire is arranged along the direction of the first trace through the first type of trace and / or the second type of trace, and is configured to be used for grounding, serving as an isolation barrier to avoid signal crosstalk, thereby improving signal transmission quality; Display data signal lines are arranged along the first trace direction and / or the second trace direction via the first type of trace, and are configured to transmit display data signals; Control signal lines are arranged along the first and / or second routing directions via the first and / or second type of traces, and are configured to transmit control signals, including timing signals and / or enable signals.

[0097] The display panel according to the above embodiments has at least the following advantages: The wiring method described above enables the routing of power signal lines, ground lines, control signal lines, display data signal lines, and LEDs and their connecting lines among cascaded driver chips. The wiring does not have direct intersections and does not require jumpers, further optimizing the wiring method of the display board.

[0098] Specifically, in one embodiment of this utility model, the arrangement of the first to fourth driver chips, power line VCC, ground line GND, and display data signal line is the same as... Figure 7 The same as shown in the image.

[0099] The display data signal lines are configured as first-class traces and / or second-class traces, and are arranged in different driver chips along the first trace direction and / or the second trace direction.

[0100] Specifically, the control signal lines are arranged in the first routing direction as follows: connecting the chip pins on the first side and the chip pins on the second side of the first driver chip, and routing them internally within the chip via crossover traces. Subsequently, they are connected via chip pins on the second side of the first driver chip and chip pins on the first side of the second driver chip. Similarly, connecting the chip pins on the first side and the chip pins on the second side of the second driver chip, and routing them internally within the chip via crossover traces. This achieves the transmission of the display control signal in the first routing direction.

[0101] The control signal lines are arranged in the second routing direction as follows: they connect the chip pins on the first side of the first driver chip and the chip pins on the fourth side of the third driver chip, and are arranged on the substrate below the driver chips. Subsequently, the control signal lines are connected to the pins on the third side of the third driver chip, and are routed internally within the third driver chip via cross-tracking traces. The control signal lines of the second and fourth driver chips are arranged in the same manner to achieve the transmission of control signals in the second routing direction.

[0102] The following details the limitations of the wiring methods in existing display panels with single or few wiring layers, and the advantages of the wiring-optimized display panel proposed in this invention.

[0103] Figure 8 This illustrates the wiring method of single-layer / few-layer display panels in the prior art. Jumpers are flexible components in electronic circuits used for temporary or fixed connections between circuit nodes. When display panels require a single layer or a few wiring layers due to limitations in heat dissipation, substrate, or space requirements, a large number of jumpers are needed. For example... Figure 8 As shown, due to the first set of opposite sides of the driver chip (such as...) Figure 8 The two sides of the middle longitudinal axis (as shown) need to be connected to the LED and ground GND respectively, and the second set of opposite sides (as shown) Figure 8 (As shown on both sides horizontally) cascaded communication lines are needed to transmit various control signals, display data signals, etc. Therefore, both horizontal and vertical routing paths are blocked. If routing on the same layer of the board is still required, jumpers must be used at line intersections to bridge the gaps. For example... Figure 8The power supply line VCC shown requires jumpers at its intersection with the ground line GND. The use of jumpers has the following drawbacks and limitations: jumpers have poor reliability and are susceptible to environmental influences. In scenarios involving vibration, temperature changes, and / or humidity fluctuations, jumpers are prone to oxidation and loosening, leading to circuit breaks or poor contact. Jumpers introduce additional parasitic inductance and capacitance, which can cause signal delay, reflection, or interference in high-speed LED matrix driving scenarios. Jumpers need to cross other lines and / or components on the display board surface, inevitably occupying additional planar and vertical space. The use of jumpers increases the assembly, quality inspection, and material costs of the display board, with the cost increase being more pronounced with the number of jumpers. Furthermore, the presence of numerous jumpers makes the display board surface cluttered, affecting heat dissipation and increasing the difficulty of later maintenance and troubleshooting. Additionally, existing technologies often limit the connection between the driver chip and LEDs to single-sided routing. If LEDs are placed on both sides of the chip, additional routing layers or jumpers are required to avoid signal crossings, further increasing production costs. In addition, signal lines in traditional cabling designs are mostly for one-way communication. To achieve signal return, a separate return line needs to be set up, which leads to a further increase in cabling density and greatly compresses the limited cabling space.

[0104] The present invention proposes a display board with optimized driver chip and wiring, which reduces production costs and improves production efficiency. It can be used to produce display boards (backlight boards) for backlight technology, direct display technology, etc.

[0105] Although various embodiments of the present invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A driver chip, characterized in that, The driver chip includes at least one set of signal transmission pipeline components; The signal transmission pipeline assembly is used to receive one signal input to the driver chip, and split the one signal into at least two signals and send them out from at least two directions to the driver chip, so as to provide signals to multiple cascaded groups of driver chips connected to the driver chip in the at least two directions respectively; The at least two directions include a first routing direction and a second routing direction that are perpendicular to each other.

2. The driver chip according to claim 1, characterized in that, The signal transmission conduit assembly includes at least two signal transmission conduits having a first signal transmission conduit and a second signal transmission conduit; The first signal transmission channel includes a first input port, a first output port, and a first transmission line connecting the first input port and the first output port; The second signal transmission channel includes a second input port, a second output port, and a second transmission line connecting the second input port and the second output port; The first input port and the second input port are respectively used to receive the one-channel signal; The first output port is used to send one of the at least two signals from one of the at least two directions, and the second output port is used to send the other of the at least two signals from the other of the at least two directions.

3. The driver chip according to claim 2, characterized in that, The first transmission line and / or the second transmission line includes a crossing section of the wiring; Alternatively, the first transmission line and / or the second transmission line may further include a transmission control function component for implementing at least one of the following: controlling the on / off state of the transmission line, controlling the output delay time of the transmission line, and adjusting the performance parameters of the transmission line.

4. The driver chip according to any one of claims 1-3, characterized in that, The driver chip includes input pins and an input interface; The input pin is used to input the signal. The input interface includes one input terminal and at least two output terminals; the input terminal is connected to the input pin; the at least two output terminals are respectively connected to at least two signal transmission channels of the signal transmission channel assembly.

5. The driver chip according to any one of claims 1-3, characterized in that, The driver chip includes output pins and an output interface; The output pin is located on the side of the driver chip housing in any one of the at least two directions; The output interface is connected to the output pin and one of the at least two signal transmission channels of the signal transmission channel assembly, so as to output one of the at least two signals corresponding to any one of the directions from the output pin.

6. A display panel with optimized wiring, characterized in that, The display panel includes: substrate; The driver chip as described in any one of claims 1-3; and On-board traces are arranged on the substrate beside and / or below the driver chip, forming a plurality of driver chip cascade groups that are respectively connected to the driver chip in at least two directions having a first trace direction and a second trace direction, wherein the projections of the first trace direction and the second trace direction on the plane of the substrate intersect.

7. The display panel according to claim 6, characterized in that, The on-board wiring includes: The first type of routing includes: Connecting segment traces are arranged on the substrate between the driver chips and do not intersect with other traces. These connecting segment traces connect to the crossing segment traces inside the driver chips. The second type of trace is arranged on the substrate below the driver chip along the first trace direction and / or the second trace direction.

8. The display panel according to claim 7, characterized in that, The display panel includes: The power cord is arranged along the direction of the first trace via the second type of trace; and The display data signal lines are arranged along the first routing direction and the second routing direction via the first type of trace.

9. The display panel according to claim 7, characterized in that, The display panel includes: The power cord is arranged along the first routing direction via the first type of routing and / or the second type of routing. The ground wire is arranged along the direction of the first wiring via the first type of wiring and / or the second type of wiring; and The display data signal lines are arranged along the first routing direction and the second routing direction via the first type of trace.

10. The display panel according to claim 7, characterized in that, The display panel includes: The power cord is arranged along the first routing direction via the first type of routing and / or the second type of routing. The ground wire is arranged along the direction of the first wiring via the first type of wiring and / or the second type of wiring; Display data signal lines are arranged along the first routing direction and / or the second routing direction via the first type of trace; and Control signal lines are arranged along the first routing direction and / or the second routing direction via the first type of routing and / or the second type of routing.

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