Channel switching circuit, display panel and display device

Abstract

The application discloses a channel exchange circuit, a display panel and a display device, and relates to the technical field of thin film transistor liquid crystal display. The channel exchange module in the circuit comprises a bipolar transistor array, a P-channel end of the bipolar transistor array is electrically connected with a positive input end of an output buffer amplifier, and an N-channel end of the bipolar transistor array is electrically connected with a negative input end of the output buffer amplifier. The complementary switch module comprises a switch control unit and a current source correction unit, a first passage end of the complementary switch module is electrically connected with a voltage source, and two side current ends of the current source correction unit are respectively electrically connected with the first passage end of the complementary switch module and a P-channel control end of the bipolar transistor array. Two side control ends of the complementary switch module are respectively electrically connected with a high-frequency signal end and an inverse signal end of the high-frequency signal end. The application aims to effectively eliminate the offset voltage and avoid display defects caused by the high-frequency clock signal to improve the display quality.

Description

Technical Field

[0001] This application relates to the field of TFT-LCD technology, and in particular to a channel switching circuit, a display panel, and a display device. Background Technology

[0002] In TFT-LCD (Thin-Film Transistor Liquid Crystal Display) driving technology, the output buffer (OP) of the driver IC (display driver chip) may experience input stage transistor mismatch due to manufacturing process deviations or environmental factors (such as temperature), resulting in an offset voltage V. OS This causes the driving voltage output to the liquid crystal cell via the OP to change from V. Line-n Offset to V Line-n ±V OS This can cause display defects such as bright and dark spots and bright and dark lines on LCD (Liquid Crystal Display) screens.

[0003] Existing technologies typically employ Figure 1 The channel switching method, labeled CC1, introduces a high-frequency clock signal f. CH To eliminate offset voltage, specifically, when a certain row of V data When the total time of the connected OPs is T, the clock signal f is set appropriately. CH The OP output voltage can be made V during the first half-cycle T / 2. OUT+ =V data +V OS During the second half of the cycle T / 2, the output voltage of the OP is V. OUT- =V data -V OS Thus, the average output voltage (V) is achieved within a complete cycle T. OUT+ +V OUT- ) / 2=V data， To achieve offset voltage V OS The elimination of this. However, this involves introducing a high-frequency clock signal f. CH The channel switching method has significant technical flaws. First, Figure 1 The inherent parasitic capacitance of the MOSFET shown in the figure is affected by the high-frequency clock signal f. CHSignificant dynamic power consumption is generated during rapid switching; secondly, the coupling effect of parasitic capacitance causes signal delay of output voltage, which directly affects the response speed of liquid crystal molecules, resulting in ghosting when the image is displayed dynamically; finally, high-frequency signals are coupled to the output channel through parasitic capacitance, generating obvious high-frequency ripple, which may not only exceed the limits of electromagnetic compatibility standards, but also form visible interference stripes on the display screen, ultimately affecting the overall display quality of the display device.

[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Utility Model Content

[0005] The main purpose of this invention is to provide a channel switching circuit, a display panel, and a display device, which aims to effectively eliminate offset voltage while avoiding display defects caused by high-frequency clock signals, thereby improving display quality.

[0006] To achieve the above objectives, this application provides a channel switching circuit, the channel switching circuit comprising: Output buffer amplifier; A channel switching module, comprising a bipolar transistor array, wherein the P-channel terminal of the bipolar transistor array is electrically connected to the positive input terminal of the output buffer amplifier, and the N-channel terminal of the bipolar transistor array is electrically connected to the negative input terminal of the output buffer amplifier; A complementary switching module includes a switch control unit and a current source correction unit. The first path terminal of the complementary switching module is electrically connected to a voltage source. The two current terminals of the current source correction unit are respectively electrically connected to the first path terminal of the complementary switching module and the P-channel control terminal of the bipolar transistor array. The two control terminals of the complementary switching module are respectively electrically connected to a high-frequency signal terminal and the inverting signal terminal of the high-frequency signal terminal.

[0007] In one embodiment, the complementary switching module includes a P-type MOSFET and an N-type MOSFET; The gate terminal of the N-type MOS transistor is electrically connected to the high-frequency signal terminal, the gate terminal of the P-type MOS transistor is electrically connected to the inverting signal terminal, the first path terminal of the P-type MOS transistor is electrically connected to the first path terminal of the N-type MOS transistor, and the second path terminal of the P-type MOS transistor is electrically connected to the second path terminal of the N-type MOS transistor. The connection point where the first path terminal of the P-type MOS transistor is electrically connected to the first path terminal of the N-type MOS transistor constitutes the first path terminal of the complementary switching module, and is electrically connected to the voltage source. The connection point where the second path terminal of the P-type MOS transistor is electrically connected to the second path terminal of the N-type MOS transistor constitutes the second path terminal of the complementary switching module, and one of the current terminals on both sides of the current source correction unit is electrically connected.

[0008] In one embodiment, the current source correction unit includes a mirror current element and a reference current element; The first current terminal of the mirror current element constitutes one of the two current terminals of the current source correction unit, and is electrically connected to the second path terminal of the complementary switch module. The second current terminal of the mirror current element constitutes the other current terminal of the two current terminals of the current source correction unit, and is electrically connected to the P channel terminal of the bipolar transistor array. The first control terminal of the mirror current device is electrically connected to the first control terminal of the reference current device, and the second control terminal of the mirror current device is electrically connected to the second control terminal of the reference current device.

[0009] In one embodiment, the current mirroring device includes a first MOSFET and a second MOSFET; The first path terminal of the first MOS transistor forms the first current terminal of the current mirror device and is electrically connected to the second path terminal of the complementary switching module. The second path terminal of the first MOS transistor is electrically connected to the first path terminal of the second MOS transistor. The second path terminal of the second MOS transistor forms the second current terminal of the current mirror device and is electrically connected to the P channel terminal of the bipolar transistor array. The gate terminal of the first MOS transistor forms the first control terminal of the current mirroring device and is electrically connected to the first control terminal and the first potential terminal of the reference current device, respectively. The gate terminal of the second MOS transistor forms the first control terminal of the current mirroring device and is electrically connected to the second control terminal and the first potential terminal of the reference current device, respectively.

[0010] In one embodiment, the reference current device includes a third MOSFET and a fourth MOSFET; The gate terminal of the third MOS transistor constitutes the first control terminal of the reference current device and is electrically connected to the first control terminal of the mirror current device and the first path terminal of the third MOS transistor. The gate terminal of the fourth MOS transistor constitutes the second control terminal of the reference current device and is electrically connected to the second control terminal of the mirror current device and the first path terminal of the fourth MOS transistor. The second path terminal of the third MOS transistor is electrically connected to the second path terminal of the fourth MOS transistor. The connection point where the second path terminal of the third MOS transistor is electrically connected to the second path terminal of the fourth MOS transistor constitutes the current adjustment terminal of the current source correction unit.

[0011] In one embodiment, the channel switching circuit includes an error correction module, the input terminal of which is electrically connected to the output terminal of the output buffer amplifier, and the error adjustment terminal of which is electrically connected to the current adjustment terminal of the current source correction unit.

[0012] In one embodiment, the error correction module includes an error correction component and a fifth MOS transistor; The input terminal of the error correction component forms the input terminal of the error correction module and is electrically connected to the output terminal of the output buffer amplifier. The output terminal of the error correction component is electrically connected to the gate terminal of the fifth MOS transistor. The first path terminal of the fifth MOS transistor is electrically connected to the second potential terminal. The second path terminal of the fifth MOS transistor forms the error adjustment terminal of the error correction module and is electrically connected to the current adjustment terminal of the current source correction unit.

[0013] In one embodiment, the bipolar transistor array includes a P-channel, an N-channel, a first bipolar junction transistor, a second bipolar junction transistor, a third bipolar junction transistor, and a fourth bipolar junction transistor; The input terminal of the P channel is electrically connected to the collector of the first bipolar junction transistor, the collector of the third bipolar junction transistor, and the display driver chip, respectively. The output terminal of the P channel constitutes the P channel terminal of the bipolar transistor array and is electrically connected to the emitter of the first bipolar junction transistor, the collector of the second bipolar junction transistor, and the positive input terminal, respectively. The base of the first bipolar junction transistor constitutes the P channel control terminal of the bipolar transistor array and is electrically connected to the other end of the two current terminals of the current source correction unit. The input terminal of the N-channel is electrically connected to the emitter of the second bipolar junction transistor and the collector of the fourth bipolar junction transistor, respectively. The output terminal of the N-channel forms the N-channel terminal of the bipolar transistor array and is electrically connected to the emitter of the third bipolar junction transistor, the emitter of the fourth bipolar junction transistor, and the inverting input terminal, respectively.

[0014] In addition, to achieve the above objectives, a display panel is also provided, the display panel including a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer being disposed between the array substrate and the color filter substrate, and the array substrate including the channel switching circuit described in any of the above claims.

[0015] In addition, to achieve the above objectives, a display device is also provided, wherein the channel switching circuit described above is provided.

[0016] This application configures the channel switching circuit of the display device to integrate a bipolar transistor array channel switching module at the input of the output buffer amplifier. By using a bipolar transistor array instead of traditional MOS transistors, the parasitic capacitance effect is significantly reduced, thereby reducing dynamic power consumption and signal delay during high-frequency switching, improving the response speed of liquid crystal molecules, and effectively avoiding image ghosting. At the same time, the complementary switching module, which integrates a switch control unit and a current source correction unit, can effectively isolate the interference of the high-frequency clock signal provided by the high-frequency signal terminal on the back-end output voltage (i.e., the output voltage of the output buffer amplifier), suppress the generation of high-frequency ripple, ensure the stability of the output signal of the output buffer amplifier, and significantly improve the display quality of the display device. Attached Figure Description

[0017] Figure 1 This is a connection diagram of an existing channel switching method; Figure 2 This is a schematic diagram of the data-driven processing logic of backend data involved in this application; Figure 3 This is a schematic diagram of the basic structure of the OP input terminal involved in this application; Figure 4 This is a schematic diagram of the output of the OP involved in this application in a real-world scenario; Figure 5 This is a schematic diagram of the framework of the first embodiment of the channel switching circuit of this application; Figure 6 This is a schematic diagram of the channel switching circuit involved in the embodiments of this application.

[0018] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings.

[0019] Explanation of icon numbers: 10. Output buffer amplifier; 20. Channel switching module; 21. Bipolar transistor array; 30. Complementary switching module; 31. Switch control unit; 32. Current source correction unit; PM1. P-type MOSFET; NM1. N-type MOSFET; M1. First MOSFET; M2. Second MOSFET; M3. Third MOSFET; M4. Fourth MOSFET; M5. Fifth MOSFET; Er1. Error correction component; Q1. First bipolar junction transistor; Q2. Second bipolar junction transistor; Q3. Third bipolar junction transistor; Q4. Fourth bipolar junction transistor; 40. Error correction module; VCC1. First potential terminal; VCC2. Second potential terminal. Detailed Implementation

[0020] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0021] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0022] In TFT-LCD (Thin-Film Transistor Liquid Crystal Display) driving technology, the Source Driver's (data driver) processing logic for backend data is as follows: Figure 2 As shown, the data (digital pixel signal) is first synchronously buffered and shifted through the Input Register, and then frozen by the data Latch within the row scan cycle. The latched digital pixel signal is intelligently routed to the P-DAC / N-DAC (P / N digital-to-analog converter) through the Input MUX (input multiplexer). The analog voltage generated by the conversion is amplified and offset voltage compensated by the Output Buffer (output buffer amplifier), and finally output to the panel source line S with precise timing through the Output MUX (output multiplexer). 2n-1 and S 2n In other words, in TFT-LCD driving technology, the OP is an indispensable unit in data driving. It can receive the analog voltage output from the front-end digital-to-analog converter, process the voltage, and output it to the in-plane, thereby driving the liquid crystal to rotate.

[0023] The basic structure of the OP's input is as follows: Figure 3 As shown, Figure 3 Chinese V IN+ and V IN- The positive and negative input terminals shown are the gates of the MOS transistors in the CMOS differential amplifier. Figure 3 In theory, the two MOSFETs M3 and M4 at the input stage should have consistent MOSFET parameters (such as carrier mobility and channel width-to-length ratio), and the output voltage of the op-operated (OP) should accurately reproduce the input voltage of the OP, that is, equal to the analog voltage output by the front-end digital-to-analog converter. However, in practical applications, the OP's output voltage may differ from its input voltage. Figure 4 As shown, due to manufacturing process deviations of the MOSFET inside the OP, or the influence of environmental factors such as temperature on the MOSFET, the positive and negative terminals of the OP's input become mismatched, causing the actual output voltage of the OP to change from V... Line-n Change to V Line-n ±V OS V OS This offset voltage further causes the voltage supplied by the Driver IC to the liquid crystal to deviate.

[0024] Since the maximum value of the Gamma voltage is generally around 14V, the offset voltage VOS (Generally tens to hundreds of mV) can have an adverse effect on the display, which may cause bright spots, dark spots, or bright or dark lines to be observed on the screen, all of which will affect the human viewing experience.

[0025] To improve the above problems, existing technologies often employ... Figure 1 The channel switching method shown introduces a high-frequency clock signal f. CH To control the switching of channels. If the V of a certain row is changed... data Let the total time for the connected OP be T, as long as the high-frequency clock signal f CH If configured correctly, then the output voltage of the OP can be V within the first T / 2 seconds. OUT+ =V data +V OS During the second T / 2 interval, the output voltage of the OP is V. OUT- =V data -V OS Then the average output within one period T is (V OUT+ +V OUT- V / 2 = V data This enables the control of offset voltage V OS The elimination of [something] is due to the introduction of a high-frequency clock signal f. CH This will cause the following problems: (1) Increased dynamic power consumption. Due to inherent process defects in MOSFETs, parasitic capacitance C always exists. GS and Miller capacitance C GD And power consumption P∝f CH CV 2 Obviously, in the clock signal f CH Under this effect, dynamic power consumption will increase sharply.

[0026] (2) Slower liquid crystal response. Due to the coupling effect of parasitic capacitance, the output voltage is delayed, which increases the response time of the liquid crystal, affects the rotation of liquid crystal molecules, reduces the difference between bright and dark states, and affects the contrast ratio.

[0027] (3) High-frequency ripple is generated. Due to the large parasitic capacitance of the MOSFET, f CH The signal is coupled to the output voltage on the channel. When the ripple is too large, it will exceed the electromagnetic compatibility (EMC) standard and cause problems such as EMI.

[0028] Therefore, based on the shortcomings of the above channel switching methods, the channel switching circuit of this application is proposed: The channel switching circuit of this application integrates a bipolar transistor array channel switching module at the input of the output buffer amplifier. By using a bipolar transistor array to replace the traditional MOS transistor, the parasitic capacitance effect is significantly reduced, thereby reducing dynamic power consumption and signal delay during high-frequency switching, improving the response speed of liquid crystal molecules, and effectively avoiding image ghosting. At the same time, the complementary switching module integrating a switch control unit and a current source correction unit can effectively isolate the interference of the high-frequency clock signal provided by the high-frequency signal terminal on the back-end output voltage (i.e., the output voltage of the output buffer amplifier), suppress the generation of high-frequency ripple, ensure the stability of the output signal of the output buffer amplifier, and significantly improve the display quality of the display device.

[0029] Based on this, the embodiments of this application provide a channel switching circuit, referring to... Figure 5 , Figure 5 This is a schematic diagram of the framework of the first embodiment of the channel switching circuit of this application.

[0030] Reference Figure 5 This application provides a channel switching circuit, which includes: Output buffer amplifier 10.

[0031] In this embodiment, the digital pixel signal output by the display driver chip is converted from digital to analog by the digital-to-analog converter and then output as an analog voltage to the channel switching module 20. At this time, the channel switching module 20 processes the analog voltage to generate a correction voltage signal (i.e., the corrected analog voltage) to offset the offset voltage of the output buffer amplifier 10. Subsequently, the input side (i.e., the positive input terminal and the negative input terminal) of the output buffer amplifier 10 receives the correction voltage signal from the channel switching module 20, and the output terminal of the output buffer amplifier 10 is electrically connected to the pixel driving terminal of the TFT-LCD display panel. This allows the correction voltage signal to be transmitted to the source line electrically connected to the pixel driving terminal after processing by the output buffer amplifier 10, thereby driving each liquid crystal molecule on the source line to rotate according to the correction signal processed by the output buffer amplifier 10. This improves the bright and dark spots and bright and dark lines caused by the input stage mismatch of the output buffer amplifier 10, and ensures the stability of the display effect.

[0032] The channel switching module 20 includes a bipolar transistor array 21, the P-channel terminal of the bipolar transistor array 21 being electrically connected to the positive input terminal of the output buffer amplifier 10, and the N-channel terminal of the bipolar transistor array 21 being electrically connected to the negative input terminal of the output buffer amplifier 10.

[0033] In this embodiment, the channel switching module 20 is located between the front-end signal source (i.e., the output of the digital-to-analog converter) and the input side of the output buffer amplifier 10. A bipolar transistor array 21 is used in the channel switching module 20 instead of a traditional MOSFET solution, solving the problems of high dynamic power consumption and signal delay caused by the large parasitic capacitance of the traditional MOSFET solution. Next, the voltage V is transmitted in stages within the circuit's operating cycle T by controlling the on / off state of the bipolar transistor array 21. data +V OS and voltage V data -V OS The output of the output buffer amplifier 10 can be used to offset the failure voltage V by the average voltage over one circuit operating cycle T. OS This addresses the root cause of display defects such as poor brightness and dark lines.

[0034] The complementary switching module 30 includes a switch control unit 31 and a current source correction unit 32. The first path terminal of the complementary switching module 30 is electrically connected to a voltage source. The two current terminals of the current source correction unit 32 are respectively electrically connected to the first path terminal of the complementary switching module 30 and the P-channel control terminal of the bipolar transistor array 21. The two control terminals of the complementary switching module 30 are respectively electrically connected to a high-frequency signal terminal and the inverting signal terminal of the high-frequency signal terminal.

[0035] In this embodiment, the complementary switching module 30 integrates a switch control unit 31 and a current source correction unit 32. The switch control unit 31 avoids interference from the high-frequency clock signal f provided by the high-frequency signal terminal through the complementary structure of the P-type MOS transistor PM1 and the N-type MOS transistor NM1. CH Directly coupled to the P-channel control terminal of the back-end bipolar transistor array 21, effectively isolating the high-frequency clock signal f. CH To reduce interference with the output voltage at the back end and decrease the frequency clock signal f CH The coupling effect with the output voltage is used to suppress the generation of high-frequency ripple, and when the switch control unit 31 is turned on, the unstable voltage that may exist in the voltage source is converted into a stable current through the current source correction unit 32, so as to provide a stable current drive for the precise on and off control of the subsequent bipolar transistor array 21.

[0036] Furthermore, based on the first embodiment of this application described above, a second embodiment of the channel switching circuit of this application is proposed, referring to... Figure 6 , Figure 6This is a schematic diagram of the channel switching circuit involved in the embodiment of this application. The switch control unit 31 includes a P-type MOS transistor PM1 and an N-type MOS transistor NM1. The gate terminal of the N-type MOS transistor NM1 is electrically connected to the high-frequency signal terminal, and the gate terminal of the P-type MOS transistor PM1 is electrically connected to the inverting signal terminal. The first path terminal of the P-type MOS transistor PM1 is electrically connected to the first path terminal of the N-type MOS transistor NM1, and the second path terminal of the P-type MOS transistor PM1 is electrically connected to the second path terminal of the N-type MOS transistor NM1. The connection node between the first path terminal of the P-type MOS transistor PM1 and the first path terminal of the N-type MOS transistor NM1 forms the first path terminal of the complementary switch module 30, which is electrically connected to the voltage source. The connection node between the second path terminal of the P-type MOS transistor PM1 and the second path terminal of the N-type MOS transistor NM1 forms the second path terminal of the complementary switch module 30. One of the two current terminals of the current source correction unit 32 is electrically connected.

[0037] In this embodiment, the switch control unit 31 achieves low-impedance turn-on, high-impedance cut-off, and high-frequency isolation functions through the complementary characteristics of the P-type MOSFET PM1 and the N-type MOSFET NM1. Specifically, this application constructs a complementary switch structure with the parallel P-type MOSFET PM1 and N-type MOSFET NM1 as the core. First, the first path terminal of the P-type MOSFET PM1 is connected to the first path terminal of the N-type MOSFET NM1 to form the first path terminal of the complementary switch module 30 and connected to a voltage source. Then, the second path terminal of the P-type MOSFET PM1 is connected to the second path terminal of the N-type MOSFET NM1 to form the second path terminal of the complementary switch module 30 and connected to one side of the current terminal of the current source correction unit 32. Subsequently, the high-frequency clock signal f output from the high-frequency signal terminal is... CH Connect to the gate of N-type MOSFET NM1 and synchronously connect it to the high-frequency clock signal f. CH Inverted clock signal with opposite phase / f CH By connecting to the gate of the P-type MOS transistor PM1, the direct coupling of the high-frequency clock signal to the back-end bipolar transistor array 21 and the output voltage path is blocked from the hardware structure level, which greatly suppresses the generation of high-frequency ripple, significantly reduces electromagnetic interference (EMI), ensures that the circuit complies with electromagnetic compatibility standards, and reduces interference to peripheral circuits and display signals.

[0038] In a specific embodiment, the switch control unit 31 relies on the complementary on / off logic of the P-type MOSFET PM1 and the N-type MOSFET NM1 to achieve dead-time-free switching of the switching state, completely avoiding current interruption or signal distortion caused by switching delay. Even in high-frequency operating scenarios, it can still ensure the continuity and stability of current transmission, and can fully adapt to the high refresh rate display requirements of TFT-LCD. For example, when the high-frequency clock signal fCH When high, the inverted clock signal / f CH When the signal is low, the high-frequency clock signal f is activated. CH To trigger the N-type MOSFET NM1 to turn on simultaneously with a high-level signal, an inverted clock signal / f is used. CH To trigger a low-level synchronous operation, the P-type MOSFET PM1 is turned on, thereby placing the switch control unit 31 in a low-impedance state. This allows the current from the voltage source to flow into the first path terminal of the complementary switch module 30, splitting into two paths through the P-type MOSFET PM1 and the N-type MOSFET NM1, before converging at the second path terminal of the complementary switch module 30 to be transmitted to the current source correction unit 32. Conversely, when the high-frequency clock signal f... CH When low, the inverted clock signal / f CH When the signal is high, both the N-type MOSFET NM1 and the P-type MOSFET PM1 remain in the off state, enabling the switch control unit 31 to effectively open the circuit and block current transmission.

[0039] Furthermore, in some other feasible embodiments, reference is made to... Figure 6 The current source correction unit 32 includes a mirror current element and a reference current element; the first current terminal of the mirror current element constitutes one of the two current terminals of the current source correction unit 32 and is electrically connected to the second path terminal of the complementary switch module 30; the second current terminal of the mirror current element constitutes the other current terminal of the two current terminals of the current source correction unit 32 and is electrically connected to the P channel terminal of the bipolar transistor array 21; the first control terminal of the mirror current element is electrically connected to the first control terminal of the reference current element, and the second control terminal of the mirror current element is electrically connected to the second control terminal of the reference current element.

[0040] In this embodiment, the current source correction unit 32 provided in this application includes a mirror current element and a reference current element. When the error correction module 40, which is electrically connected to the output terminal of the output buffer amplifier 10, detects a deviation between the actual output voltage of the output buffer amplifier 10 and the preset ideal output voltage, the error correction module 40 generates an error correction signal corresponding to the voltage deviation and feeds it back to the reference current element in the current source correction unit 32. At this time, the reference current element responds to the error correction signal and automatically adjusts the reference current I of the reference current element. REF And through the potential signal provided by the first potential terminal VCC1, the reference current element and the mirror current element are triggered and controlled synchronously, so that the mirror current I flowing through the mirror current element SS Adjusted to match the reference current I REFThe same output is sent to the P-channel terminal of the bipolar transistor array 21 to regulate the conduction level of the P-channel in the bipolar transistor array 21, thereby adjusting the change in the correction signal input to the output buffer amplifier 10, and finally canceling the offset voltage V of the output buffer amplifier 10. OS This is to pull the actual output voltage of the output buffer amplifier 10 back to the same level as the ideal output voltage.

[0041] It should be noted that the voltage deviation can be understood as the voltage difference between the actual output voltage and the ideal output voltage. This ideal output voltage can be the analog voltage output by the digital-to-analog converter.

[0042] The current source correction unit 32 can be understood as a high-swing common-source common-gate current mirror composed of a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, and a fourth MOSFET M4. For example, the first MOSFET M1 and the second MOSFET M2 form the main current transmission path, and the third MOSFET M3 and the fourth MOSFET M4 form a cascaded structure as common-source common-gate transistors of the first MOSFET M1 and the second MOSFET M2, respectively. That is, the gate terminal of the third MOSFET M3 is connected to its own first path terminal and the gate terminal of the first MOSFET M1, and the gate terminal of the fourth MOSFET M4 is connected to its own first path terminal and the gate terminal of the second MOSFET to form a self-biased loop; when the voltage source outputs the original mirror current I... SS When the original mirror current I is controllable at 100μA or less, SS After flowing into the first MOSFET M1, the drain voltage of the first MOSFET M1 is stabilized by the common-source and common-gate structure of the third MOSFET M3. The voltage is then transmitted through the second MOSFET M2. Simultaneously, the drain voltage of the second MOSFET M2 is stabilized by the fourth MOSFET M4 through the common-source and common-gate structure, ensuring that the first MOSFET M1 and the second MOSFET M2 always operate at the minimum voltage V required for saturation. MIN (Can be less than 1V), which significantly reduces power consumption while ensuring the normal operation of the current mirror.

[0043] Furthermore, in some feasible embodiments, reference is made to Figure 6The current mirroring device includes a first MOSFET M1 and a second MOSFET M2; the first path terminal of the first MOSFET M1 forms the first current terminal of the current mirroring device and is electrically connected to the second path terminal of the complementary switch module 30; the second path terminal of the first MOSFET M1 is electrically connected to the first path terminal of the second MOSFET M2; the second path terminal of the second MOSFET M2 forms the second current terminal of the current mirroring device and is electrically connected to the P-channel terminal of the bipolar transistor array 21; the gate terminal of the first MOSFET M1 forms the first control terminal of the current mirroring device and is electrically connected to the first control terminal and the first potential terminal VCC1 of the reference current device; the gate terminal of the second MOSFET M2 forms the first control terminal of the current mirroring device and is electrically connected to the second control terminal and the first potential terminal VCC1 of the reference current device.

[0044] In this embodiment, the first MOSFET M1 and the second MOSFET M2 form the current transmission path. When the voltage source outputs the original mirror current I through the turned-on switch control unit 31... SS At that time, the original mirror current I SS When the first MOSFET M1 and the second MOSFET M2 are turned on, the current characteristics of the reference current device are accurately replicated, that is, the original mirror current I. SS The current values ​​flowing through the first conducting MOSFET M1 and the second conducting MOSFET M2 will be related to the reference current I output by the reference current device. REF Maintain consistency and ensure that the mirror current I SS During transmission, it is unaffected by factors such as voltage fluctuations and temperature drift, maintaining the magnitude and stability of the current. Furthermore, the cascaded structure of the first MOS transistor M1 and the second MOS transistor M2 eliminates current distortion caused by single-transistor characteristic deviations, providing precise drive current for the bipolar transistor array 21.

[0045] Furthermore, in some feasible embodiments, reference is made to Figure 6 The reference current device includes a third MOSFET M3 and a fourth MOSFET M4. The gate terminal of the third MOSFET M3 constitutes the first control terminal of the reference current device and is electrically connected to the first control terminal of the mirror current device and the first path terminal of the third MOSFET M3. The gate terminal of the fourth MOSFET M4 constitutes the second control terminal of the reference current device and is electrically connected to the second control terminal of the mirror current device and the first path terminal of the fourth MOSFET M4. The second path terminal of the third MOSFET M3 is electrically connected to the second path terminal of the fourth MOSFET M4. The connection point between the second path terminal of the third MOSFET M3 and the second path terminal of the fourth MOSFET M4 constitutes the current adjustment terminal of the current source correction unit 32.

[0046] In this embodiment, the gate terminal of the third MOSFET M3 serves as both the first control terminal of the reference current device and the first control terminal of the mirror current device, and is also electrically connected to the first path terminal of the third MOSFET M3 to form a diode connection structure. The gate terminal of the fourth MOSFET M4 serves as both the second control terminal of the reference current device and the second control terminal of the mirror current device, and is also electrically connected to the first path terminal of the fourth MOSFET M4 to form a diode connection structure. Simultaneously, the second path terminals of the third MOSFET M3 and the fourth MOSFET M4 are connected, and their connection point constitutes the current adjustment terminal of the current source correction unit 32. Therefore, when the reference current device is operating, the third MOSFET M3 and the fourth MOSFET M4, through the diode connection structure (i.e., the gate terminal is short-circuited to the first path terminal), ensure that the reference current I... REF The current characteristics are stable and unaffected by external voltage fluctuations, thus providing a precise reference for the current mirror device. The potential signal provided by the first potential terminal VCC1 is used as the gate drive signal for the third MOSFET M3 and the fourth MOSFET M4, and connected to the first and second control terminals of the current mirror device. This ensures the mirror current I of the current mirror device. SS It can replicate the reference current I in real time. REF The current characteristics improve the accuracy of the current mirror.

[0047] Furthermore, in some other feasible embodiments, reference is made to... Figure 6 The channel switching circuit includes an error correction module 40. The input terminal of the error correction module 40 is electrically connected to the output terminal of the output buffer amplifier 10, and the error adjustment terminal of the error correction module 40 is electrically connected to the current adjustment terminal of the current source correction unit 32.

[0048] In this embodiment, the input terminal of the error correction module 40 acquires the actual output voltage of the output buffer amplifier 10 in real time, compares the actual output voltage with the preset ideal output voltage, calculates the voltage deviation between the actual output voltage and the ideal output voltage through the error detection circuit inside the error correction module 40, and generates an error correction signal corresponding to the voltage deviation. The reference current I is adjusted by adjusting the conduction level of the fifth MOS transistor M5 set at the error adjustment terminal. REF This enables the control of the mirror current I. SS The precise adjustment provides a precise drive current for the bipolar transistor array 21.

[0049] Furthermore, in some feasible embodiments, reference is made to Figure 6The error correction module 40 includes an error correction component Er1 and a fifth MOS transistor M5. The input terminal of the error correction component Er1 is electrically connected to the output terminal of the output buffer amplifier 10. The output terminal of the error correction component Er1 is electrically connected to the gate terminal of the fifth MOS transistor M5. The first path terminal of the fifth MOS transistor M5 is electrically connected to the second potential terminal VCC2. The second path terminal of the fifth MOS transistor M5 is electrically connected to the error adjustment terminal of the error correction module 40 and the current adjustment terminal of the current source correction unit 32.

[0050] In this embodiment, the input terminal of the error correction component Er1 is electrically connected to the output terminal of the output buffer amplifier 10, which can acquire the actual output voltage of the output buffer amplifier 10 in real time and compare the actual output voltage with the preset ideal output voltage. The error detection circuit inside the error correction module 40 calculates the voltage deviation between the actual output voltage and the ideal output voltage, and generates an error correction signal corresponding to the voltage deviation. This signal is then transmitted to the gate terminal of the fifth MOSFET M5 to change the gate voltage of the fifth MOSFET M5, thereby changing the conduction degree of the fifth MOSFET M5 and thus changing the reference current I flowing out of the reference current device. REF Size, the reference current I REF The mirror current I SS The output voltage of the output buffer amplifier 10 is precisely calibrated via the bipolar transistor array 21.

[0051] It should be noted that the fifth MOSFET M5 is a BIAS MOSFET (Bias Metal-Oxide-Semiconductor Transistor) with a high swing common-source common-gate current mirror.

[0052] Furthermore, in some other feasible embodiments, reference is made to... Figure 6The bipolar junction transistor array 21 includes a P-channel, an N-channel, a first bipolar junction transistor Q1, a second bipolar junction transistor Q2, a third bipolar junction transistor Q3, and a fourth bipolar junction transistor Q4. The input terminal of the P-channel is electrically connected to the collector of the first bipolar junction transistor Q1, the collector of the third bipolar junction transistor Q3, and the display driver chip, respectively. The output terminal of the P-channel constitutes the P-channel terminal of the bipolar junction transistor array 21, which is respectively connected to the emitter of the first bipolar junction transistor Q1, the collector of the second bipolar junction transistor Q2, and the positive output terminal of the display driver chip. The base of the first bipolar junction transistor Q1 forms the P-channel control terminal of the bipolar transistor array 21 and is electrically connected to the other end of the two current terminals of the current source correction unit 32. The input terminal of the N-channel is electrically connected to the emitter of the second bipolar junction transistor Q2 and the collector of the fourth bipolar junction transistor Q4, respectively. The output terminal of the N-channel forms the N-channel terminal of the bipolar transistor array 21 and is electrically connected to the emitter of the third bipolar junction transistor Q3, the emitter of the fourth bipolar junction transistor Q4, and the inverting input terminal, respectively.

[0053] In this embodiment, the first bipolar junction transistor Q1, the second bipolar junction transistor Q2, the third bipolar junction transistor Q3, and the fourth bipolar junction transistor Q4 are all BJTs (Bipolar Junction Transistors). BJTs conduct electricity through a combination of minority carrier diffusion (base region) and majority carrier drift (collector region), resulting in high electron and hole mobility in silicon (especially in NPN BJTs, where electron mobility is faster than hole mobility). In contrast, traditional MOS transistors rely on majority carrier drift (electrons or holes in the channel), but the formation of their conductive channel requires a strong gate electric field, and carrier migration is limited by surface scattering effects, resulting in lower equivalent mobility. That is, at the same high-frequency clock signal f... CH Under this application, BJT transistors are used to replace MOS transistors in traditional channel switching circuits for channel switching. The higher carrier mobility and more efficient conduction mechanism of BJT transistors can reduce delay and loss in high-frequency signal transmission, improve the response speed of channel switching module 20 to high-frequency timing, and ensure that channel switching module 20 can still accurately realize switching control and current transmission in high-frequency scenarios. This ensures effective cancellation of the offset voltage of output buffer amplifier 10, avoids LCD display deviation caused by insufficient high-frequency response, and adapts to the high refresh rate driving requirements of TFT-LCD.

[0054] It should be noted that, Figure 6 In this context, N Channel refers to the Nth channel. Figure 6In this context, P Channel refers to the P channel. The potential of the second potential terminal VCC2 is lower than that of the first potential terminal VCC1.

[0055] Furthermore, the display panel provided in this application includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate, and the array substrate includes the channel switching circuit described in any of the above embodiments. While effectively eliminating offset voltage, it overcomes the display defects caused by high-frequency clock signals in traditional MOS transistor solutions. Compared with the prior art, the beneficial effects of the device provided in this application are the same as those of the channel switching circuit provided in the above embodiments, and will not be repeated here.

[0056] The display device (or other device) provided in this application offers a novel display panel that effectively eliminates offset voltage while overcoming display defects caused by high-frequency clock signals in traditional MOS transistor solutions. Compared to the prior art, the beneficial effects of the device provided in this application are the same as those of the channel switching circuit provided in the above embodiments, and will not be elaborated upon here.

[0057] The above are only some embodiments of this application and do not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A pass-through switching circuit, characterized by, The channel switching circuit includes: Output buffer amplifier; A channel switching module, comprising a bipolar transistor array, wherein the P-channel terminal of the bipolar transistor array is electrically connected to the positive input terminal of the output buffer amplifier, and the N-channel terminal of the bipolar transistor array is electrically connected to the negative input terminal of the output buffer amplifier; A complementary switching module includes a switch control unit and a current source correction unit. The first path terminal of the complementary switching module is electrically connected to a voltage source. The two current terminals of the current source correction unit are respectively electrically connected to the first path terminal of the complementary switching module and the P-channel control terminal of the bipolar transistor array. The two control terminals of the complementary switching module are respectively electrically connected to a high-frequency signal terminal and the inverting signal terminal of the high-frequency signal terminal.

2. The pass-through switching circuit of claim 1, wherein, The complementary switching module includes a P-type MOSFET and an N-type MOSFET; The gate terminal of the N-type MOS transistor is electrically connected to the high-frequency signal terminal, the gate terminal of the P-type MOS transistor is electrically connected to the inverting signal terminal, the first path terminal of the P-type MOS transistor is electrically connected to the first path terminal of the N-type MOS transistor, and the second path terminal of the P-type MOS transistor is electrically connected to the second path terminal of the N-type MOS transistor. The connection point where the first path terminal of the P-type MOS transistor is electrically connected to the first path terminal of the N-type MOS transistor constitutes the first path terminal of the complementary switching module, and is electrically connected to the voltage source. The connection point where the second path terminal of the P-type MOS transistor is electrically connected to the second path terminal of the N-type MOS transistor constitutes the second path terminal of the complementary switching module, and one of the current terminals on both sides of the current source correction unit is electrically connected.

3. The pass-through switching circuit of claim 1, wherein, The current source correction unit includes a mirror current element and a reference current element; The first current terminal of the mirror current element constitutes one of the two current terminals of the current source correction unit, and is electrically connected to the second path terminal of the complementary switch module. The second current terminal of the mirror current element constitutes the other current terminal of the two current terminals of the current source correction unit, and is electrically connected to the P channel terminal of the bipolar transistor array. The first control terminal of the mirror current device is electrically connected to the first control terminal of the reference current device, and the second control terminal of the mirror current device is electrically connected to the second control terminal of the reference current device.

4. The pass-through switching circuit of claim 3, wherein, The current mirroring device includes a first MOSFET and a second MOSFET; The first path terminal of the first MOS transistor forms the first current terminal of the current mirror device and is electrically connected to the second path terminal of the complementary switching module. The second path terminal of the first MOS transistor is electrically connected to the first path terminal of the second MOS transistor. The second path terminal of the second MOS transistor forms the second current terminal of the current mirror device and is electrically connected to the P channel terminal of the bipolar transistor array. The gate terminal of the first MOS transistor forms the first control terminal of the current mirroring device and is electrically connected to the first control terminal and the first potential terminal of the reference current device, respectively. The gate terminal of the second MOS transistor forms the first control terminal of the current mirroring device and is electrically connected to the second control terminal and the first potential terminal of the reference current device, respectively.

5. The pass-through switching circuit of claim 3, wherein, The reference current device includes a third MOSFET and a fourth MOSFET; The gate terminal of the third MOS transistor constitutes the first control terminal of the reference current device and is electrically connected to the first control terminal of the mirror current device and the first path terminal of the third MOS transistor. The gate terminal of the fourth MOS transistor constitutes the second control terminal of the reference current device and is electrically connected to the second control terminal of the mirror current device and the first path terminal of the fourth MOS transistor. The second path terminal of the third MOS transistor is electrically connected to the second path terminal of the fourth MOS transistor. The connection point where the second path terminal of the third MOS transistor is electrically connected to the second path terminal of the fourth MOS transistor constitutes the current adjustment terminal of the current source correction unit.

6. The pass-through switching circuit of claim 1, wherein, The channel switching circuit includes an error correction module. The input terminal of the error correction module is electrically connected to the output terminal of the output buffer amplifier, and the error adjustment terminal of the error correction module is electrically connected to the current adjustment terminal of the current source correction unit.

7. The pass-through switching circuit of claim 6, wherein, The error correction module includes an error correction component and a fifth MOSFET; The input terminal of the error correction component forms the input terminal of the error correction module and is electrically connected to the output terminal of the output buffer amplifier. The output terminal of the error correction component is electrically connected to the gate terminal of the fifth MOS transistor. The first path terminal of the fifth MOS transistor is electrically connected to the second potential terminal. The second path terminal of the fifth MOS transistor forms the error adjustment terminal of the error correction module and is electrically connected to the current adjustment terminal of the current source correction unit.

8. The channel switching circuit as described in claim 1, characterized in that, The bipolar transistor array includes a P-channel, an N-channel, a first bipolar junction transistor, a second bipolar junction transistor, a third bipolar junction transistor, and a fourth bipolar junction transistor; The input terminal of the P channel is electrically connected to the collector of the first bipolar junction transistor, the collector of the third bipolar junction transistor, and the display driver chip, respectively. The output terminal of the P channel constitutes the P channel terminal of the bipolar transistor array and is electrically connected to the emitter of the first bipolar junction transistor, the collector of the second bipolar junction transistor, and the positive input terminal, respectively. The base of the first bipolar junction transistor constitutes the P channel control terminal of the bipolar transistor array and is electrically connected to the other end of the two current terminals of the current source correction unit. The input terminal of the N-channel is electrically connected to the emitter of the second bipolar junction transistor and the collector of the fourth bipolar junction transistor, respectively. The output terminal of the N-channel forms the N-channel terminal of the bipolar transistor array and is electrically connected to the emitter of the third bipolar junction transistor, the emitter of the fourth bipolar junction transistor, and the inverting input terminal, respectively.

9. A display panel, characterized by, The display panel includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate. The array substrate includes a channel switching circuit as described in any one of claims 1 to 8.

10. A display device, characterized by comprising: The display device includes the display panel as described in claim 9.

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