A vertical cavity surface emitting laser
Patent Information
- Application Number
- CN202521603380.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-30
- Publication Date
- 2026-09-18
- Estimated Expiration
- 2035-07-30
AI Technical Summary
如图1所示，垂直腔面发射激光器包括依次层叠的N型电极11、衬底12、N型DBR层13、N型SCH层14(Separate ConfinementHeterostructure，分别限制异质结结构)、MQW层15(Multiple Quantum Well layer，多量子阱层)、P型SCH层16、氧化层17、P型DBR层18和P型电极19，P型电极19位于P型DBR层18的表面，P型电极19与P型DBR层18的接触面积有限，使得串联电阻增大，而且一部分P型DBR层18会被氧化形成氧化层17，进一步压缩P型电极19的有效面积，同时降低了器件的热导率，使得器件性能降低
[0016] The P-type DBR layer of this invention adopts a special structure combining a mesa and a frustum. The P-type electrode covers the top and bottom surfaces and sides of the frustum, which greatly increases the contact area of the P-type electrode, reduces the series resistance of the device, and increases the thermal conductivity of the device, thereby improving the high-temperature performance of the device.
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Figure CN224774380U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of optoelectronic technology, and more specifically, to a vertical cavity surface-emitting laser. Background Technology
[0002] Vertical-cavity surface-emitting lasers (VCSELs), also known as vertical resonant surface-emitting lasers, emit laser light perpendicularly to the top surface, unlike edge-emitting lasers which are typically produced using diced, independent chip manufacturing processes. VCSELs offer advantages such as low threshold current, circular spot size, low cost, high modulation rate, and ease of two-dimensional integration, playing a crucial role in short-range data communication and laser detection.
[0003] Therefore, most current VCSEL structures employ oxidation to form an oxide layer on a P-type DBR (Distributed Bragg Reflector) layer to achieve current limiting. For example... Figure 1 As shown, the vertical-cavity surface-emitting laser includes an N-type electrode 11, a substrate 12, an N-type DBR layer 13, an N-type SCH layer 14 (Separate Confinement Heterostructure), an MQW layer 15 (Multiple Quantum Well layer), a P-type SCH layer 16, an oxide layer 17, a P-type DBR layer 18, and a P-type electrode 19, which are stacked sequentially. The P-type electrode 19 is located on the surface of the P-type DBR layer 18. The limited contact area between the P-type electrode 19 and the P-type DBR layer 18 increases the series resistance. Furthermore, a portion of the P-type DBR layer 18 is oxidized to form an oxide layer 17, further compressing the effective area of the P-type electrode 19 and reducing the thermal conductivity of the device, thus degrading the device performance. Utility Model Content
[0004] This invention provides a vertical cavity surface-emitting laser that increases the contact area between the P-type electrode and the P-type DBR layer, reduces the series resistance of the device, and increases the thermal conductivity of the device, thereby improving the high-temperature performance of the device.
[0005] A vertical cavity surface-emitting laser includes, from bottom to top, an N-type electrode, a substrate, an N-type DBR layer, an MQW layer, a P-type DBR layer and a P-type electrode, wherein the P-type DBR layer has a first oxide layer and a first oxide confinement hole, and a light-emitting hole is provided on the N-type electrode or the P-type electrode, wherein the aperture of the light-emitting hole is larger than the aperture of the first oxide confinement hole.
[0006] The P-type DBR layer has a mesa and a frustum layer stacked sequentially from bottom to top. The first oxide layer is located on the mesa. The mesa has a mesa and a sidewall. The frustum has a top bottom and a side. The P-type electrode covers the top bottom and side of the frustum and extends to the mesa of the mesa.
[0007] Furthermore, the angle between the side of the frustum and the surface of the frustum is 60° to 80°.
[0008] Furthermore, it also includes an N-type SCH layer and a P-type SCH layer, which are located on both sides of the MQW layer. The N-type SCH layer is connected to the N-type DBR layer, and the P-type SCH layer is connected to the P-type DBR layer.
[0009] Furthermore, the first oxide layer is located at the junction of the platform surface and the P-type SCH.
[0010] Furthermore, the surface of the platform also has a second oxide layer and a third oxide layer, which are located above the first oxide layer from bottom to top. The second oxide layer has a second oxide limiting hole, and the third oxide layer has a third oxide limiting hole. The diameter of the second oxide limiting hole is larger than the diameter of the first oxide limiting hole, and the diameter of the third oxide limiting hole is larger than the diameter of the first oxide limiting hole.
[0011] Furthermore, the diameter of the third oxidation-restricted pore is larger than that of the second oxidation-restricted pore.
[0012] Furthermore, it also includes a passivation layer that covers the table surface and sidewalls of the table surface, and the passivation layer extends the N-type DBR layer, covering part of the N-type DBR layer.
[0013] Furthermore, it also includes a metal layer that completely covers the P-type electrode, completely covers the passivation layer located on the mesa, and at least partially covers the passivation layer located on the N-type DBR layer.
[0014] Furthermore, the thickness of the metal layer is 3–6 μm.
[0015] Furthermore, it also includes a cap layer, which is located between the P-type DBR layer and the P-type electrode.
[0016] The P-type DBR layer of this invention adopts a special structure combining a mesa and a frustum. The P-type electrode covers the top and bottom surfaces and sides of the frustum, which greatly increases the contact area of the P-type electrode, reduces the series resistance of the device, and increases the thermal conductivity of the device, thereby improving the high-temperature performance of the device. Attached Figure Description
[0017] The specific embodiments of this utility model will now be described in detail with reference to the accompanying drawings. The drawings are only used to illustrate the spatial relationship of the various structural parts and do not represent the actual thickness, dimensions, or relative proportions of the structural parts.
[0018] Figure 1 This is a schematic diagram of the existing structure;
[0019] Figure 2 This is a schematic diagram of the structure of this utility model;
[0020] Figure 3 This is a schematic diagram of the structure of the P-type DBR layer of this utility model;
[0021] Figure 4 This is a schematic diagram of another embodiment of the present invention.
[0022] Label Explanation
[0023] 11 N-type electrode 12 Substrate 13 N-type DBR layer 14 N-type SCH layer 15 MQW layer
[0024] 16. P-type SCH layer; 17. First oxide layer; 18. First oxide confinement pore; 19. P-type DBR layer; 10.
[0025] Tabletop 181, Tabletop 1811, Side Wall 1812, Frustum 182, Top Surface 1821, Side Surface 1822
[0026] 19 P-type electrode; 20 Light exit aperture; 21 Passivation layer; 22 Second oxide layer
[0027] Second oxide confinement hole 221, third oxide layer 23, third oxide confinement hole 231
[0028] Metal layer 24, cap layer 25 Detailed Implementation
[0029] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the terms "upper," "lower," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings, or the orientation or positional relationships commonly used when the product is in use, and are merely for ease of description and should not be construed as limiting the present invention. It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of the present invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. It should also be noted that the division of multiple embodiments in the present invention is merely for the convenience of description and should not constitute a special limitation; features in various embodiments can be combined and mutually referenced without contradiction.
[0030] This utility model discloses a vertical cavity surface-emitting laser, such as... Figure 2 , Figure 3 and Figure 4 As shown, this is a preferred embodiment of the present invention, which includes an N-type electrode 11, a substrate 12, an N-type DBR layer 13, an MQW layer 15, a P-type DBR layer 18, and a P-type electrode 19 stacked sequentially from bottom to top. The P-type DBR layer 18 has a first oxide layer 17, and the first oxide layer 17 has a first oxide limiting hole 171. A light emitting hole 20 is provided on the P-type electrode 19, and the aperture of the light emitting hole 20 is larger than the aperture of the first oxide limiting hole 171.
[0031] The P-type DBR layer 18 has a mesa 181 and a frustum 182 stacked sequentially from bottom to top. The first oxide layer 17 is located on the mesa 181. The mesa 181 has a mesa 1811 and a sidewall 1812. The frustum 182 has an upper bottom surface 1821 and a side surface 1822. The P-type electrode 19 covers the upper bottom surface 1821 and the side surface 1822 of the frustum 182. The P-type electrode 19 extends onto the mesa 1811 of the mesa 181.
[0032] Because the first oxide layer 17 is retained on the platform surface 181, this utility model only needs to perform one oxidation process. Moreover, its unique platform surface 1811 facilitates the subsequent processes to fabricate the P-type electrode 19 and the passivation layer 21 in the horizontal direction. The frustum portion 182 provides a flat side surface 1822, which is conducive to the adhesion of the P-type electrode 19 to it.
[0033] like Figure 3 As shown, the angle θ between the side surface 1822 of the frustum portion 182 and the platform surface 1811 of the platform portion 181 is 60° to 80°. This angle setting makes it easier for the P-type electrode 19 to attach to the frustum portion 182.
[0034] The P-type electrode 19 extends onto the table surface 1811 of the table surface 181, and can partially or completely cover the table surface 1811 as needed.
[0035] Furthermore, separate confinement heterostructures (SCHs) are separately confined within the active region to limit charge carriers (electrons and holes) while reducing interaction losses between the optical field and charge carriers, thereby improving the luminous efficiency and performance of the device. Therefore, this invention also includes an N-type SCH layer 14 and a P-type SCH layer 16, located on either side of the MQW layer 15. The N-type SCH layer 14 is connected to the N-type DBR layer 13, and the P-type SCH layer 16 is connected to the P-type DBR layer 18.
[0036] Furthermore, the first oxide layer 17 is located on the mesa 181 and in contact with the P-type SCH16, reducing the lateral diffusion of current and increasing the carrier injection efficiency. Of course, the first oxide layer 17 can also be located where it is not in contact with the P-type SCH16, depending on the actual needs of the device.
[0037] Furthermore, the platform surface also has a second oxide layer 22 and a third oxide layer 23, which are located above the first oxide layer 17 from bottom to top. The second oxide layer 22 has a second oxide limiting hole 221, and the third oxide layer 23 has a third oxide limiting hole 231. The aperture φ2 of the second oxide limiting hole 221 is larger than the aperture φ1 of the first oxide limiting hole 171, and the aperture φ3 of the third oxide limiting hole 231 is larger than the aperture φ1 of the first oxide limiting hole 171. The multi-oxide layer structure can better prevent current from diffusing to the edges, thus playing a current limiting role. Current concentration can also reduce the threshold current, reduce useless power consumption, and improve the energy conversion efficiency of the device.
[0038] Furthermore, such as Figure 3 As shown, the aperture φ3 of the third oxide limiting aperture 231 is larger than the aperture φ2 of the second oxide limiting aperture 221. The cross-section of the three oxide apertures forms a conductive region similar to an inverted trapezoid, which can concentrate the light emitted from the MQW layer 15 and also limit the current.
[0039] Furthermore, it also includes a passivation layer 21, which covers the mesa 1811 and sidewall 1812 of the mesa 181, and extends the N-type DBR layer 13, covering part of the exposed surface of the N-type DBR layer 13. Common materials for the passivation layer 21 include SiO2, Si3N4, Al2O3, etc. Its core function is to cover the device surface (especially the edges, sidewalls, mesa, or oxide layer interfaces) to improve the stability, reliability, and efficiency of the VCSEL through physical and chemical protection, electrical isolation, and performance optimization.
[0040] Furthermore, it also includes a metal layer 24, which completely covers the P-type electrode 19, completely covers the passivation layer 21 located on the mesa 181, and at least partially covers the passivation layer 21 located on the N-type DBR layer 13. The thickness of the metal layer 24 is 3–6 μm. The metal layer 24 is made of a material with high thermal and electrical conductivity, serving to conduct electricity and dissipate heat. In this embodiment, the material of the metal layer 24 is gold (Au), but other metal materials can also be used, such as silver (Ag) and copper (Cu). The appropriate material of the metal layer 24 can be selected according to the actual use of the device.
[0041] Furthermore, it also includes a cap layer 25, which is located between the P-type DBR layer 18 and the P-type electrode 19. For example, the material of the P-type DBR layer 18 is AlGaAs, and the material of the cap layer 25 is GaAs, with a doping concentration of 1-3E19cm⁻¹. -3 The high doping of the cap layer 25 facilitates the formation of ohmic contacts, reduces resistance, and protects the P-type DBR layer 18 from oxidation. In this embodiment, the cap layer 25 and the P-type DBR layer 18 are grown in a single epitaxial growth process, with the cap layer 25 covering the top surface 1821 of the P-type DBR layer 18. Alternatively, a secondary epitaxial growth process can be used, where the cap layer 25 covers both the top surface 1821 and the side surface 1822 of the P-type DBR layer 18.
[0042] This invention also provides a method for fabricating a vertical cavity surface-emitting laser, comprising the following steps: Step 1, sequentially epitaxially growing an N-type DBR layer 13, an N-type SCH layer 14, an MQW layer 15 (quantum well active region), a P-type SCH layer 16, a P-type DBR layer 18, and a cap layer 25 on a GaAs substrate 12.
[0043] Step 2: Using dry etching (ICP) technology, the N-type DBR layer 13 is etched to the MQW layer 15, exposing the P-type DBR layer 18. The P-type DBR layer 18 is then oxidized using wet oxidation technology to form a first oxide layer 17 and other multiple oxide layers. The aperture of the oxide-restricted vias in the other oxide layers is larger than the aperture of the first oxide-restricted via 171 in the first oxide layer 17.
[0044] Step 3: Use ICP etching to form the mesa 181 and the frustum 182 of the P-type DBR layer 18, etching up to the third oxide layer 23 of the mesa 181, with an etching angle of 60-80°, to clean the oxidized DBR in the frustum 182.
[0045] Step four: deposit a P-type electrode 19 on the frustum portion 182 and the cap layer 25, and leave a light-emitting hole 20 on top, the diameter of the light-emitting hole 20 being larger than the diameter of the first oxide limiting hole 171.
[0046] Step 5: Deposit a passivation layer 21 on the mesa 1811, sidewall 1812, and partially exposed N-type DBR layer 13 of the mesa 181. Deposit a metal layer 24 over the P-type electrode 19 and the passivation layer 25.
[0047] Step 6: Thin the substrate 12 to 100-150 μm and deposit an N-type electrode 11 on the back side of the substrate 12.
[0048] like Figure 4As shown, another preferred embodiment of the present invention is a back-emitting light structure, which includes an N-type electrode 11, a substrate 12, an N-type DBR layer 13, an N-type SCH layer 14, an MQW layer 15, a P-type SCH layer 16, a P-type DBR layer 18, and a P-type electrode 19 stacked sequentially from bottom to top. The P-type DBR layer 18 has a first oxide layer 17, and the first oxide layer 17 has a first oxide limiting hole 171. A light-emitting hole 20 is provided on the N-type electrode 11, and the aperture of the light-emitting hole 20 is larger than the aperture of the first oxide limiting hole 171. The P-type DBR layer 18 has a mesa 181 and a frustum 182 stacked sequentially from bottom to top. A first oxide layer 17 is located on the mesa 181. The mesa 181 has a mesa 1811 and a sidewall 1812. The frustum has a top surface 1821 and a side surface 1822. A P-type electrode 19 covers the top surface 1821 and the side surface 1822 of the frustum 182 and extends onto the mesa 1811 of the mesa 181. A passivation layer 21 covers the mesa 1811 and the sidewall 1812 of the mesa 181 and extends into the N-type DBR layer 13, covering part of the exposed surface of the N-type DBR layer 13. A metal layer 24 completely covers the P-type electrode 19, completely covers the passivation layer 21 located on the mesa 181, and at least partially covers the passivation layer 21 located on the N-type DBR layer 13. The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Although the present utility model has been disclosed above with reference to a preferred embodiment, it is not intended to limit the present utility model. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present utility model. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present utility model without departing from the scope of the present utility model shall still fall within the scope of the present utility model.
Claims
1. A vertical cavity surface emitting laser, characterized by: The device comprises, from bottom to top, an N-type electrode, a substrate, an N-type DBR layer, an MQW layer, a P-type DBR layer, and a P-type electrode. The P-type DBR layer has a first oxide layer with a first oxide limiting hole. A light-emitting hole is provided on either the N-type electrode or the P-type electrode, and the diameter of the light-emitting hole is larger than the diameter of the first oxide limiting hole. The P-type DBR layer has a mesa portion and a frustum portion stacked from bottom to top. The first oxide layer is located on the mesa portion, which has a mesa surface and sidewalls. The frustum portion has a top bottom surface and sidewalls. The P-type electrode covers the top bottom surface and sidewalls of the frustum portion and extends to the mesa surface of the mesa portion.
2. A vertical-cavity surface-emitting laser according to claim 1, characterized in that: The angle between the side of the frustum and the table surface is 60° to 80°.
3. The vertical cavity surface emitting laser of claim 1, wherein: It also includes an N-type SCH layer and a P-type SCH layer, which are located on both sides of the MQW layer. The N-type SCH layer is connected to the N-type DBR layer, and the P-type SCH layer is connected to the P-type DBR layer.
4. The vertical cavity surface emitting laser of claim 3, wherein: The first oxide layer is located at the junction of the platform surface and the P-type SCH.
5. The vertical cavity surface emitting laser of claim 1, wherein: The surface also has a second oxide layer and a third oxide layer, which are located above the first oxide layer from bottom to top. The second oxide layer has a second oxide limiting hole, and the third oxide layer has a third oxide limiting hole. The diameter of the second oxide limiting hole is larger than the diameter of the first oxide limiting hole, and the diameter of the third oxide limiting hole is larger than the diameter of the first oxide limiting hole.
6. The vertical cavity surface emitting laser of claim 5, wherein: The diameter of the third oxidation-restricted pore is larger than that of the second oxidation-restricted pore.
7. The vertical cavity surface emitting laser of claim 1, wherein: It also includes a passivation layer that covers the tabletop and sidewalls of the tabletop, and the passivation layer extends the N-type DBR layer, covering part of the N-type DBR layer.
8. The vertical cavity surface emitting laser of claim 1, wherein: It also includes a metal layer that completely covers the P-type electrode, a metal layer that completely covers the passivation layer located on the mesa, and a metal layer that at least partially covers the passivation layer located on the N-type DBR layer.
9. The vertical cavity surface emitting laser of claim 8, wherein: The thickness of the metal layer is 3–6 μm.
10. The vertical cavity surface emitting laser of claim 1, wherein: It also includes a cap layer, which is located between the P-type DBR layer and the P-type electrode.