Intelligent substation bay layer mistake prevention logic verification device

Abstract

The utility model discloses an intelligent substation interval layer mistake prevention logic verification device, including central processing module, ethernet module, display module, man -machine interaction module, data storage module, SOC coordination processing module and optical module, central processing module is connected with data storage module each other through LVDS that is low voltage differential signal interface pin, central processing module is connected with communication module each other through PHY that is physical layer interface pin. The utility model discloses portable single machine design, portable, can be suitable for various extension and new substation interval layer mistake prevention logic acceptance scene of flexible. Through the collaborative design of multi -light -port hardware acceleration processing and industrial -grade portable structure, the traditional artificial verification efficiency low, the reliability poor industry pain point is conquered, realizes the efficient accurate verification to the mistake prevention interlock logic, and provides a set of high reliability, portable standardization verification tool for intelligent substation interval layer mistake prevention logic verification.

Description

Technical Field

[0001] This utility model relates to the field of electrical equipment maintenance technology, and in particular to a smart substation bay layer anti-misoperation logic verification device. Background Technology

[0002] In the field of substation automation control, preventing electrical maloperation (five preventions) is a core requirement for ensuring the safe operation of the power grid. The National Energy Administration's "Twenty-Five Key Requirements for Preventing Power Production Accidents" and the "Technical Specification for Relay Protection of Intelligent Substations" (Q / GDW 441-2010) both emphasize the extreme importance of bay-level anti-maloperation interlocking logic. However, existing verification methods for the five-prevention interlocking logic heavily rely on manual operation, resulting in complex, lengthy, inefficient, and unreliable processes. This cumbersome situation, coupled with a lack of dedicated verification tools, severely restricts the efficiency of operation and maintenance debugging, necessitating a portable hardware verification device to fundamentally solve the bottleneck problems of verification efficiency and reliability. Utility Model Content

[0003] The purpose of this invention is to provide an intelligent substation bay layer anti-misoperation logic verification device that can achieve fast and accurate verification through multi-optical port hardware acceleration.

[0004] The technical solution adopted in this utility model is as follows: A smart substation bay layer anti-misoperation logic verification device includes a central processing module for executing anti-misoperation logic algorithms and system scheduling, an Ethernet module for connecting to the station control layer network, a display module for visualizing verification results, a human-machine interaction module for inputting operation commands, a data storage module for storing test data and a rule base, a SOC co-processing module for hardware-accelerated preprocessing of network data, and an optical module for accessing the process layer network and acquiring real-time messages via fiber optic network. The central processing module is interconnected with the data storage module via an LVDS (Low Voltage Differential Signaling) interface pin, interconnected with the communication module via a PHY (Physical Layer) interface pin, interconnected with the input terminal of the display module via its LVDS (Low Voltage Differential Signaling) interface pin, interconnected with the output terminal of the human-machine interaction module via its USB expansion interface, interconnected with the SOC co-processing module via an SPI control interface and a PCIe 2.0 ×4 data interface, and interconnected with the optical module.

[0005] The central processing module is based on a modular hardware design and uses an Intel i3 processor and 8GB of DDR4 high-speed memory.

[0006] The data storage module includes an mSATA driver chip and a solid-state drive that communicates with it. The mSATA driver chip is an SM2246XT chip.

[0007] The Ethernet module includes a network interface card (NIC) and an Ethernet interface connected thereto. The NIC is an I219-LM chip.

[0008] The display module uses an industrial-grade 10.4-inch IPS screen (1920x1200) to facilitate high-definition display of the relevant operation interface and test results of the interval layer error prevention logic verification software.

[0009] The SOC coprocessor module uses a Xilinx Zynq-7010 chip, integrating a PS processing system and a PL programmable logic unit: the PS unit is connected to the central processing module via an SPI control interface; the PL unit is connected to the central processing module via a PCIe 2.0×4 data interface. The PL unit of the SOC coprocessor module integrates 4 independent MII channels and supports the expansion connection of 1-4 SFP optical modules.

[0010] The USB expansion chip is a USB2514 chip.

[0011] The PHY driver chip is a KSZ8041FTL chip.

[0012] The optical module in question is a GTLS-1312-20-DXU optical module.

[0013] This utility model adopts a portable, stand-alone design, making it lightweight and easy to carry. It can be flexibly applied to various substation renovation, expansion, and new construction scenarios for bay-level anti-misoperation logic acceptance. Internally, it integrates a central processing module and directly connected Ethernet interface modules, display modules, human-machine interaction modules, and data storage modules. It also features a SOC co-processing module and expands multi-optical port communication capabilities. Through the collaborative design of multi-optical port hardware acceleration processing and an industrial-grade portable structure, it overcomes the industry pain points of low efficiency and poor reliability of traditional manual verification, achieving efficient and accurate verification of anti-misoperation interlocking logic. This provides a highly reliable, portable, and standardized verification tool for bay-level anti-misoperation logic verification in intelligent substations. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the principle of this utility model; Figure 2 This is a structural schematic diagram of a specific example of the present utility model; Figure 3 This is the circuit diagram of the LCD of this utility model. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of this application provided below with reference to the accompanying drawings is not intended to limit the scope of protection of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. The present invention will be further described below with reference to the accompanying drawings.

[0017] like Figure 1 , 2As shown in Figure 3, this utility model includes a central processing module for executing anti-error logic algorithms and system scheduling, an Ethernet interface module for connecting to the station control layer network, a display module for visualizing verification results, a human-machine interaction module for inputting operation commands, a data storage module for storing test data and rule bases, a SOC co-processing module for hardware-accelerated preprocessing of network data, and an optical module for accessing the process layer network and acquiring real-time messages via fiber optic network. The central processing module is interconnected with the data storage module via an LVDS (Low Voltage Differential Signaling) interface pin, with the communication module via a PHY (Physical Layer) interface pin, with the input terminal of the display module via its LVDS interface pin, with the output terminal of the human-machine interaction module via its USB expansion interface, and with the SOC co-processing module via an SPI control interface and a PCIe 2.0 ×4 data interface. The SOC co-processing module is interconnected with the optical module.

[0018] Combined with appendix Figure 2 This embodiment presents a technical solution using an Intel i3 processor as the central processing module and a Zynq-7010 SOC coprocessor. Its advantages are: the i3 processor supports a wide operating temperature range of -40℃ to 85℃, matching the harsh environment of substations; the Zynq-7010's PS unit achieves stable control communication with the main processor via the SPI interface, ensuring zero-interruption system scheduling; the PL unit connects to the optical module via the MII interface to transmit and receive messages, and transmits pre-processed messages to the central processing module via the PCIe 2.0×4 interface.

[0019] In this embodiment, the Ethernet interface module includes a network card and an Ethernet interface. The verification device connects to the Ethernet network through the Ethernet interface for service data communication. The data storage module includes an mSATA driver chip and a solid-state drive (SSD). The mSATA driver chip is used to implement signal level conversion between the central processing module and the SSD. The human-machine interface module includes a USB expansion chip and a USB communication interface. The USB expansion chip is used to implement signal level conversion between the central processing module and the USB interface device. The display module uses an industrial-grade high-resolution 10.4-inch IPS screen (1920x1200). The optical module includes a PHY driver chip and an SFP optical module interface. The PHY driver chip is used to convert the analog signals of the input and output SFP optical modules into digital signals for communication with the Zynq-7010 SOC coprocessor module.

[0020] As an optional embodiment, the PL unit of the SOC coprocessor module integrates 4 independent MII channels, supporting the expansion connection of 1-4 SFP optical modules.

[0021] Figure 2 This is the case where two optical modules are connected. The structure of the other connected optical modules is exactly the same, consisting of a PHY driver chip and an SFP optical module. As an optional embodiment, the PHY driver chip is a KSZ8041FTL chip: its adaptive impedance matching technology optimizes the integrity of long-distance transmission signals and effectively suppresses signal attenuation; at the same time, the integrated port-level short-circuit / overcurrent protection mechanism avoids the spread of single-point faults to the entire communication system through physical isolation, providing high stability assurance for network links in the harsh environment of substations.

[0022] This embodiment provides the implementation scheme of the optical module in the previous embodiment, that is, the PHY driver chip is the KSZ8041FTL chip.

[0023] It is worth noting that this embodiment only provides one specific implementation scheme for the optical module and does not exclude other feasible implementation schemes. Similarly, the following embodiments also only provide one specific implementation scheme and do not exclude other feasible implementation schemes, which will not be described separately.

[0024] As an optional embodiment, preferably, the network card is an I219-LM chip, which ensures stable operation in harsh substation environments through a wide temperature design (-40℃~85℃). Its IEEE 802.3 certification ensures full compatibility with power protocols such as IEC 61850 / MMS. At the same time, it relies on a hardware-level TCP / IP checksum and offload engine to reduce CPU load by more than 20%, achieving high real-time message processing.

[0025] As an optional embodiment, the mSATA driver chip is the SM2246XT chip, which has mature SATA6Gbps interface support and 4-channel flash memory control architecture, can provide sequential read performance of up to 540MB / s, and ensures data reliability through hardware-level LDPC error correction and dynamic temperature control mechanism.

[0026] As an optional embodiment, the USB expansion chip is a USB2514 chip: it ensures the stability and low power consumption of USB 2.0 expansion through a four-port industrial-grade integrated design, natively supports port charging control, electrostatic protection, and multi-layer topology management functions; at the same time, it relies on USB-IF certification to ensure full protocol compatibility, can be directly adapted to the native drivers of mainstream operating systems to reduce development and debugging risks, and provides long-term supply assurance in combination with a mature mass production system, building a highly reliable hardware foundation for multi-device expansion scenarios.

[0027] As an optional embodiment, the optical module is a GTLS-1312-20-DXU optical module, which enables plug-and-play operation of the substation optical port through multi-protocol adaptive capability (compatible with 100BASE-LX / SX standards), and covers the entire substation area with a 20km single-mode fiber transmission distance, ensuring flexible deployment and reliable communication of the verification device in complex substation environments.

[0028] The anti-misoperation logic verification process in this embodiment is achieved through a combination of hardware preprocessing and software analysis: the optical module collects GOOSE / SV messages from the substation process layer via the SFP interface, which are received in parallel by the PL unit of the Zynq-7010 through four independent MII channels, performing hardware-level message filtering based on features such as MAC address and application identifier (APPID); the preprocessed data is transmitted to the Intel i3 central processing module via a PCIe 2.0×4 high-speed channel (theoretical bandwidth 20Gbps). This module calls the five-prevention rule base embedded in the storage module to drive the anti-misoperation logic simulation engine to simulate circuit breaker opening and closing, disconnector position changes, and other operations, comparing the compliance of the device status to be verified with the interlocking logic in real time, generating a verification report and outputting it through a 10.4-inch IPS screen, while the solid-state drive managed by the SM2246XT main control chip stores the test data. The data collected by the software in this application is all existing technology. Manual judgment also requires software collection. Furthermore, the data transmission, processing, and rule invocation are all existing technologies. This application merely automates the judgment process by combining hardware structure with existing program comparison. Moreover, the processing trigger after comparison is replaced by processor control instead of manual control. Therefore, the methods involved are all existing software programming techniques and do not belong to the core inventive point of this application.

[0029] Combined with appendix Figure 3This invention also includes an LCD module for visualizing the verification results. The LCD schematic specifically includes an LCD socket U2 (U2A and U2B), surface-mount capacitors C6 and C8, surface-mount resistors R4-R6, surface-mount diode D1, surface-mount inductor L1, and a power chip U3. Pins 3, 4, 6, 7, 9, 10, 12, 13, 15, and 16 of the U2A portion of the LCD socket U2 are connected to the LVDS output of the central processing module for LCD differential signal transmission. Pins 4 and 5 of the U2B portion of the LCD socket U2 are connected to the LCD control I / O of the central processing module, where pin 4 controls the LCD brightness and pin 5 controls the LCD backlight on and off. Pins 1 and 2 of the U2B portion of the LCD socket U2 are connected to the LED_VCCS output driver of the power chip U3. Pin 5 of the power chip U3 is connected to one side of the surface-mount resistor R4 and surface-mount inductor L1; pin 4 of the power chip U3 is connected to the other side of the surface-mount resistor R4; pin 1 of the power chip U3 is connected to one side of the surface-mount inductor L1 and the surface-mount diode; pin 3 of the power chip U3 is connected to one side of the surface-mount resistors R5 and R6; the other side of the surface-mount resistor R5 is connected to one side of the surface-mount diode D1 and the surface-mount capacitor C8. The surface-mount capacitor C6 filters the input power supply VCC5V, while the surface-mount capacitor C8 primarily stores charge for the LCD backlight power supply.

[0030] This utility model fundamentally solves the industry pain point of error prevention logic verification in smart substations through the collaborative innovation of "multi-optical port hardware acceleration architecture" and "fully industrial-grade modular design": 1. Improved efficiency: Relying on the dynamic collaborative mechanism of hardware preprocessing and software analysis, millisecond-level real-time closed-loop verification is achieved, completely replacing traditional inefficient manual operations; 2. Reliability Reconstruction: The industrial-grade wide-temperature characteristics and anti-interference architecture of key chipsets (such as I219-LM network card and KSZ8041FTL physical layer chip) ensure the continuous and stable operation of the device in harsh environments such as extreme temperature changes and strong electromagnetic interference in substations. 3. Flexible deployment: The portable standalone design integrates an adaptive optical communication module, supporting flexible deployment across regions and significantly improving operational mobility; 4. Full-chain functional integration: From process layer optical message acquisition and hardware-accelerated rule analysis to result visualization output, a complete closed loop of anti-misoperation logic verification is built, seamlessly covering the five core scenarios of circuit breaker opening and closing, and disconnector interlocking. 5. Standardization empowerment: As a verification tool for the implementation of power five-prevention interlocking, it promotes the transformation of anti-misoperation verification from discrete manual operation to automated and standardized operation mode.

[0031] In the description of this invention, it should be noted that directional terms such as "center", "lateral", "longitudinal", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", and "counterclockwise" indicate the orientation and positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. They should not be construed as limiting the specific protection scope of this invention.

[0032] It should be noted that the terms "comprising" and "having" and any variations thereof in the specification and claims of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.

[0033] Note that the above description is merely a preferred embodiment and application of the technical principles of the present invention. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the specific embodiments described herein, and may include many other effective embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A smart substation bay layer anti-error logic verification device, characterized in that: The system includes a central processing module for executing anti-error logic algorithms and system scheduling, an Ethernet module for connecting to the station control layer network, a display module for visualizing verification results, a human-machine interaction module for inputting operation commands, a data storage module for storing test data and rule bases, a SOC co-processing module for hardware-accelerated preprocessing of network data, and an optical module for accessing the process layer network and acquiring real-time messages via fiber optic network. The central processing module is interconnected with the data storage module via LVDS (Low Voltage Differential Signaling) interface pins, with the communication module via PHY (Physical Layer Interface) pins, with the input terminal of the display module via its LVDS interface pins, with the output terminal of the human-machine interaction module via its USB expansion interface, with the SOC co-processing module via an SPI control interface and a PCIe 2.0 ×4 data interface, and the optical module is interconnected with the optical module.

2. The intelligent substation bay layer anti-misoperation logic verification device according to claim 1, characterized in that: The central processing module is based on a modular hardware design and uses an Intel i3 processor and 8GB of DDR4 high-speed memory.

3. The intelligent substation bay layer anti-misoperation logic verification device according to claim 1, characterized in that: The data storage module includes an mSATA driver chip and a solid-state drive that communicates with it. The mSATA driver chip is an SM2246XT chip.

4. The intelligent substation bay layer anti-misoperation logic verification device according to claim 1, characterized in that: The Ethernet module includes a network interface card (NIC) and an Ethernet interface connected thereto. The NIC is an I219-LM chip.

5. The intelligent substation bay layer anti-misoperation logic verification device according to claim 1, characterized in that: The display module uses an industrial-grade 10.4-inch IPS screen, which facilitates the high-definition display of the relevant operation interface and test results of the interval layer error prevention logic verification software.

6. The intelligent substation bay layer anti-misoperation logic verification device according to claim 1, characterized in that: The SOC coprocessor module uses a Xilinx Zynq-7010 chip, integrating a PS processing system and a PL programmable logic unit: the PS unit is connected to the central processing module via an SPI control interface; the PL unit is connected to the central processing module via a PCIe 2.0×4 data interface.

7. The intelligent substation bay layer anti-misoperation logic verification device according to claim 6, characterized in that: The PL unit of the SOC coprocessor module integrates 4 independent MII channels and supports the expansion connection of 1-4 SFP optical modules.

8. The intelligent substation bay layer anti-misoperation logic verification device according to claim 1, characterized in that: The USB expansion chip is a USB2514 chip.

9. The intelligent substation bay layer anti-misoperation logic verification device according to claim 1, characterized in that: The PHY uses the KSZ8041FTL chip.

10. The intelligent substation bay layer anti-misoperation logic verification device according to claim 1, characterized in that: The optical module in question is a GTLS-1312-20-DXU optical module.

Images