Low stress three-phase Vienna circuit

Abstract

The utility model belongs to the field of power electronics, disclose a kind of low stress three-phase Vienna circuit, inductance L2 connects the drain of MOS tube Q21, the grid of MOS tube Q21 is connected with the one end of resistance R237 and the one end of inductance L31, the other end of inductance L31 connects the negative end of diode D71 and the one end of resistance R248, the positive end of diode D71 connects the one end of resistance R247 and the base of triode Q52, the other end of resistance R247 connects port DRVA2, the other end of resistance R248 connects the emitter of triode Q52, the source of MOS tube Q21 connects the source of MOS tube Q22, the other end of resistance R237, the one end of resistance R249, the collector of triode Q52, the collector of triode Q53 and port GNDA.The utility model has the beneficial effects: the scheme simple structure can effectively suppress switch tube turn-off overvoltage, improve system reliability.

Description

Technical Field

[0001] This utility model relates to the field of power electronics technology, and in particular to a low-stress three-phase Vienna circuit. Background Technology

[0002] Three-phase Vienna topology is widely used in new energy grid-connected systems. Due to wiring loop issues, the parasitic inductance (L≈di / dt) in the loop can cause high-voltage spikes when the switching transistor is turned on and off, leading to: 1. MOSFETs exceeding their withstand voltage and breaking down. 2. The need to select higher voltage-resistant devices, resulting in higher costs. 3. Traditional RC snubber circuits have high losses and low efficiency. Existing solutions involve increasing the drive resistor, but this results in problems such as response delay and severe heat generation.

[0003] Therefore, it is necessary to provide a low-stress three-phase Vienna circuit and create a simple, low-cost, and low-stress three-phase Vienna circuit scheme, which has important practical significance and broad market prospects. Utility Model Content

[0004] This utility model discloses a low-stress three-phase Vienna circuit, which relates to a protection circuit that reduces MOSFET turn-off voltage stress by optimizing capacitor layout, and can effectively solve the technical problems involved in the background art.

[0005] To achieve the above objectives, the technical solution of this utility model is as follows:

[0006] A low-stress three-phase Vienna circuit includes port A, port B, and port C. Port A is connected to one end of inductor L2, and the other end of inductor L2 is connected to the positive terminal of diode D56 and the negative terminal of diode D27. Port B is connected to one end of inductor L4, and the other end of inductor L4 is connected to the positive terminal of diode D23 and the negative terminal of diode D7. Port C is connected to one end of inductor L6, and the other end of inductor L6 is connected to the positive terminal of diode D21 and the negative terminal of diode D30.

[0007] The negative terminal of diode D56 is connected to the negative terminals of diode D23 and D21, one end of capacitor C46, ​​one end of capacitor C84, one end of capacitor C20, one end of capacitor C53, and port OUT+. The other end of capacitor C46 is connected to one end of capacitor C7. The other end of capacitor C7 is connected to one end of capacitor C5, one end of capacitor C4, one end of capacitor C84, one end of capacitor C65, one end of capacitor C20, one end of capacitor C101, one end of capacitor C53, one end of capacitor C9, and port GND. The other end of capacitor C5 is connected to one end of capacitor C25. The other end of capacitor C4 is connected to one end of capacitor C45. The positive terminal of diode D27 is connected to the positive terminal of diode D7, the positive terminal of diode D30, the other end of capacitor C25, the other end of capacitor C45, the other end of capacitor C65, the other end of capacitor C101, the other end of capacitor C9, and port OUT-.

[0008] The other end of inductor L2 is connected to the drain of MOSFET Q21. The gate of MOSFET Q21 is connected to one end of resistor R237 and one end of inductor L31. The other end of inductor L31 is connected to the negative terminal of diode D71 and one end of resistor R248. The positive terminal of diode D71 is connected to one end of resistor R247 and the base of transistor Q52. The other end of resistor R247 is connected to port DRVA2. The other end of resistor R248 is connected to the emitter of transistor Q52. The source of MOSFET Q21 is connected to the source of MOSFET Q22, the other end of resistor R237, and resistor R249. One end of the transistor Q52, the collector of the transistor Q53, and the port GNDA; the gate of the MOSFET Q22 is connected to the other end of the resistor R249 and one end of the inductor L21; the other end of the inductor L21 is connected to one end of the resistor R543 and the negative terminal of the diode D102; the other end of the resistor R543 is connected to the emitter of the transistor Q53; the base of the transistor Q53 is connected to the positive terminal of the diode D102 and one end of the resistor R544; the other end of the resistor R544 is connected to the port DRVA1; the drain of the MOSFET Q22 is connected to the other end of the capacitor C7.

[0009] The other end of inductor L4 is connected to the drain of MOSFET Q54. The gate of MOSFET Q54 is connected to one end of resistor R239 and one end of inductor L22. The other end of inductor L22 is connected to the negative terminal of diode D68 and one end of resistor R241. The positive terminal of diode D68 is connected to one end of resistor R242 and the base of transistor Q56. The other end of resistor R242 is connected to port DRVB1. The other end of resistor R241 is connected to the emitter of transistor Q56. The source of MOSFET Q54 is connected to the source of MOSFET Q55, the other end of resistor R239, and resistor R243. One end of the transistor Q55 is connected to the collector of transistor Q56, the collector of transistor Q57, and port GNDB. The gate of transistor Q55 is connected to the other end of resistor R243 and one end of inductor L24. The other end of inductor L24 is connected to one end of resistor R545 and the negative terminal of diode D103. The other end of resistor R545 is connected to the emitter of transistor Q57. The base of transistor Q57 is connected to the positive terminal of diode D103 and one end of resistor R546. The other end of resistor R546 is connected to port DRVB2. The drain of transistor Q55 is connected to the other end of capacitor C7.

[0010] The other end of inductor L6 is connected to the drain of MOSFET Q27. The gate of MOSFET Q27 is connected to one end of resistor R222 and one end of inductor L27. The other end of inductor L27 is connected to the negative terminal of diode D58 and one end of resistor R223. The positive terminal of diode D58 is connected to one end of resistor R224 and the base of transistor Q58. The other end of resistor R224 is connected to port DRVC1. The other end of resistor R223 is connected to the emitter of transistor Q58. The source of MOSFET Q27 is connected to the source of MOSFET Q28, the other end of resistor R222, and resistor R223. One end of 5, the collector of transistor Q58, the collector of transistor Q59, and port GNDC; the gate of MOSFET Q28 is connected to the other end of resistor R225 and one end of inductor L32; the other end of inductor L32 is connected to one end of resistor R228 and the negative terminal of diode D167; the other end of resistor R228 is connected to the emitter of transistor Q59; the base of transistor Q59 is connected to the positive terminal of diode D67 and one end of resistor R229; the other end of resistor R229 is connected to port DRVC2; and the drain of MOSFET Q28 is connected to the other end of capacitor C7.

[0011] This invention relates to a MOSFET voltage stress suppression circuit in a three-phase Vienna topology. The circuit includes three-phase input signals, a MOSFET switching group, a MOSFET drive signal circuit, freewheeling diodes, chip capacitors, and an output capacitor. At least one chip snubber capacitor is connected in parallel between the midpoint of each phase arm and the positive and negative terminals of the DC bus. This capacitor group is directly connected between the drain of the switching transistor (midpoint of the bus) and the positive and negative DC buses, forming a low-inductance loop. When the switching transistor is turned off, the high-frequency current is discharged nearby through the added capacitor, significantly reducing the voltage spikes caused by parasitic inductance in the loop. This solution has a simple structure and can effectively suppress switching transistor turn-off overvoltage, improving system reliability.

[0012] As a preferred improvement of this utility model: one end of capacitor C20 is connected to one end of resistor VR14, the other end of resistor VR14 is connected to one end of resistor VR15, the other end of resistor VR15 is connected to one end of resistor VR16, the other end of resistor VR16 is connected to one end of resistor VR17 and one end of capacitor C9, the other end of resistor VR17 is connected to one end of resistor VR18, the other end of resistor VR18 is connected to one end of resistor VR19, and the other end of resistor VR19 is connected to port OUT-.

[0013] As a preferred improvement of this utility model: port A, port B and port C are connected to three-phase power.

[0014] As a preferred improvement of this utility model, the OUT+ and OUT- ports output 400V voltage.

[0015] As a preferred improvement of this utility model, the ports GND, GNDA, GNDB, and GNDC are connected to different grounding terminals.

[0016] As a preferred improvement of this utility model: the low-stress three-phase Vienna circuit further includes a controller MCU, which is connected to ports DRVA1, DRVA2, DRVB1, DRVB2, DRVC1 and DRVC2.

[0017] As a preferred improvement of this utility model: MOS transistors Q21 and Q22 are simultaneously turned on and off, MOS transistors Q54 and Q55 are simultaneously turned on and off, and MOS transistors Q27 and Q28 are simultaneously turned on and off.

[0018] As a preferred improvement of this utility model: the capacitor C7 and the capacitor C46 are low ESL film capacitors or ceramic capacitors with a capacitance range of 100nF-10μF.

[0019] The beneficial effects of this utility model are as follows:

[0020] By connecting a chip capacitor in parallel between the drain (midpoint) of the MOSFET, which is far from the positive and negative busbars, an additional discharge circuit is added when the inductor discharges, reducing the stress on the MOSFET switch. This method is simple to operate, and the number of capacitors added can be adjusted according to the MOSFET with excessive stress. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0022] Figure 1 This is a schematic diagram of a low-stress three-phase Vienna circuit according to the present invention;

[0023] Figure 2 This is an enlarged schematic diagram of the circuit of this utility model;

[0024] Figure 3 This is a schematic diagram of the test results for this utility model. Figure 1 ;

[0025] Figure 4 This is a schematic diagram of the test results for this utility model. Figure 2 . Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0027] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0028] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0029] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0030] Furthermore, the technical solutions of the various embodiments of the present invention can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0031] Please see Figure 1 As shown, this utility model provides a low-stress three-phase Vienna circuit, including port A, port B, and port C. Port A is connected to one end of inductor L2, and the other end of inductor L2 is connected to the positive terminal of diode D56 and the negative terminal of diode D27. Port B is connected to one end of inductor L4, and the other end of inductor L4 is connected to the positive terminal of diode D23 and the negative terminal of diode D7. Port C is connected to one end of inductor L6, and the other end of inductor L6 is connected to the positive terminal of diode D21 and the negative terminal of diode D30. Ports A, B, and C are connected to three-phase power.

[0032] The negative terminal of diode D56 is connected to the negative terminals of diode D23 and D21, one end of capacitor C46, ​​one end of capacitor C84, one end of capacitor C20, one end of capacitor C53, and port OUT+. The other end of capacitor C46 is connected to one end of capacitor C7. The other end of capacitor C7 is connected to one end of capacitor C5, one end of capacitor C4, one end of capacitor C84, one end of capacitor C65, one end of capacitor C20, one end of capacitor C101, and the other end of capacitor C53. One end of capacitor C9 is connected to port GND. The other end of capacitor C5 is connected to one end of capacitor C25. The other end of capacitor C4 is connected to one end of capacitor C45. The positive terminal of diode D27 is connected to the positive terminals of diodes D7 and D30, the other ends of capacitors C25, C45, C65, and C101, the other end of capacitor C9, and port OUT-. Ports OUT+ and OUT- output a 400V voltage. One end of capacitor C20 is connected to one end of resistor VR14. The other end of resistor VR14 is connected to one end of resistor VR15. The other end of resistor VR15 is connected to one end of resistor VR16. The other end of resistor VR16 is connected to one end of resistor VR17 and one end of capacitor C9. The other end of resistor VR17 is connected to one end of resistor VR18. The other end of resistor VR18 is connected to one end of resistor VR19. The other end of resistor VR19 is connected to port OUT-.

[0033] Please see Figure 2As shown, the other end of inductor L2 is connected to the drain of MOSFET Q21. The gate of MOSFET Q21 is connected to one end of resistor R237 and one end of inductor L31. The other end of inductor L31 is connected to the negative terminal of diode D71 and one end of resistor R248. The positive terminal of diode D71 is connected to one end of resistor R247 and the base of transistor Q52. The other end of resistor R247 is connected to port DRVA2. The other end of resistor R248 is connected to the emitter of transistor Q52. The source of MOSFET Q21 is connected to the source of MOSFET Q22, the other end of resistor R237, and resistor R2. One end of 49, the collector of transistor Q52, the collector of transistor Q53, and port GNDA; the gate of MOSFET Q22 is connected to the other end of resistor R249 and one end of inductor L21; the other end of inductor L21 is connected to one end of resistor R543 and the negative terminal of diode D102; the other end of resistor R543 is connected to the emitter of transistor Q53; the base of transistor Q53 is connected to the positive terminal of diode D102 and one end of resistor R544; the other end of resistor R544 is connected to port DRVA1; and the drain of MOSFET Q22 is connected to the other end of capacitor C7.

[0034] The other end of inductor L4 is connected to the drain of MOSFET Q54. The gate of MOSFET Q54 is connected to one end of resistor R239 and one end of inductor L22. The other end of inductor L22 is connected to the negative terminal of diode D68 and one end of resistor R241. The positive terminal of diode D68 is connected to one end of resistor R242 and the base of transistor Q56. The other end of resistor R242 is connected to port DRVB1. The other end of resistor R241 is connected to the emitter of transistor Q56. The source of MOSFET Q54 is connected to the source of MOSFET Q55, the other end of resistor R239, and resistor R243. One end of the transistor Q55 is connected to the collector of transistor Q56, the collector of transistor Q57, and port GNDB. The gate of transistor Q55 is connected to the other end of resistor R243 and one end of inductor L24. The other end of inductor L24 is connected to one end of resistor R545 and the negative terminal of diode D103. The other end of resistor R545 is connected to the emitter of transistor Q57. The base of transistor Q57 is connected to the positive terminal of diode D103 and one end of resistor R546. The other end of resistor R546 is connected to port DRVB2. The drain of transistor Q55 is connected to the other end of capacitor C7.

[0035] The other end of inductor L6 is connected to the drain of MOSFET Q27. The gate of MOSFET Q27 is connected to one end of resistor R222 and one end of inductor L27. The other end of inductor L27 is connected to the negative terminal of diode D58 and one end of resistor R223. The positive terminal of diode D58 is connected to one end of resistor R224 and the base of transistor Q58. The other end of resistor R224 is connected to port DRVC1. The other end of resistor R223 is connected to the emitter of transistor Q58. The source of MOSFET Q27 is connected to the source of MOSFET Q28, the other end of resistor R222, and resistor R223. One end of 5, the collector of transistor Q58, the collector of transistor Q59, and port GNDC; the gate of MOSFET Q28 is connected to the other end of resistor R225 and one end of inductor L32; the other end of inductor L32 is connected to one end of resistor R228 and the negative terminal of diode D167; the other end of resistor R228 is connected to the emitter of transistor Q59; the base of transistor Q59 is connected to the positive terminal of diode D67 and one end of resistor R229; the other end of resistor R229 is connected to port DRVC2; and the drain of MOSFET Q28 is connected to the other end of capacitor C7.

[0036] In this embodiment, ports GND, GNDA, GNDB, and GNDC are connected to different grounding terminals. The low-stress three-phase Vienna circuit also includes a controller MCU, which is connected to ports DRVA1, DRVA2, DRVB1, DRVB2, DRVC1, and DRVC2. MOSFETs Q21 and Q22 are simultaneously on and off, MOSFETs Q54 and Q55 are simultaneously on and off, and MOSFETs Q27 and Q28 are simultaneously on and off. Capacitors C7 and C46 are low-ESL film capacitors or ceramic capacitors with a capacitance range of 100nF-10μF.

[0037] A voltage stress suppression circuit for MOSFETs in a three-phase Vienna topology includes three-phase input signal terminals, input inductors (L2, L4, L8), a freewheeling diode group (D56, D21, D3, D7, D27, D30), 400V DC link positive and negative buses (OUT+, OUT-), a switching transistor group (Q21, Q22, Q54, Q55, Q27, Q28), a chip capacitor group, and an output capacitor group. In the PCB layout, some MOSFETs are far from the large capacitors. Therefore, chip capacitors are connected in parallel between the drain (midpoint) of the far-distance MOSFETs and the positive and negative buses. This adds a discharge path during inductor discharge, reducing the stress on the MOSFET switches. This method is simple to operate, and the number of capacitors added only needs to be adjusted according to the MOSFETs with excessive stress. The chip capacitor group consists of low-ESL film capacitors or ceramic capacitors with a capacitance range of 100nF-10μF and a voltage rating 20% ​​higher than the DC bus voltage. The wiring distance between the chip-shaped absorption capacitor bank and the switching transistor pins should be small to minimize the loop area. Based on the three-phase Vienna circuit, a simple, low-cost, and low-stress three-phase Vienna circuit scheme is provided.

[0038] A three-phase Vienna low-stress circuit scheme includes a three-phase power input terminal, a three-phase PFC inductor, a diode freewheeling group, a MOSFET driver circuit, a MOSFET switching group, a chip capacitor group, and an output capacitor. When a three-phase signal is input, the switching transistors of each phase are connected in reverse series, and the switching transistors Q21 and Q22, Q54 and Q55, and Q27 and Q28 are simultaneously turned on and off. When this switching combination is open, the current of that phase can flow bidirectionally in this branch; when this switching combination is closed, the current of that phase cannot flow through this branch, nor can it flow through the parasitic diode of the MOSFET, that is, the branch is completely disconnected. Taking phase A as an example, when the phase A switch is on, point A is connected to the midpoint; when the phase A switch is off, if the phase A current is positive, diode D56 conducts and D27 is cut off, and the voltage level at point A is positive (relative to the midpoint); conversely, diode D27 conducts and D56 is cut off, and the voltage level at point A is negative (relative to the midpoint). Therefore, the PFC inductance affects the MOSFET every time it switches. The conduction circuit of phase A goes through the inductor to the MOSFET and then to the midpoint. The discharge circuit goes through the inductor to the freewheeling diode and then to the midpoint of the output capacitor. Since the conduction and discharge circuits have different lengths on the PCB, they directly affect the turn-on stress of the MOSFET. In order to solve the problem of high stress in some MOSFETs, a chip capacitor is directly connected in parallel between the drain near the midpoint of each phase and the positive and negative busbars. For example, if the stress of Q55 is too high, C7 and C46 are connected in parallel to +400V (OUT+) at the midpoint near it, and C5 and C25 are connected in parallel to -400V (OUT-) at the midpoint. This shortens the discharge circuit. The current goes through the inductor to the diode to the chip capacitor and then to the midpoint. It can be said that a new circuit is added. Moreover, the added chip capacitor effectively prevents the oscillation of parasitic inductance and effectively reduces the stress of the MOSFET when it is turned on.

[0039] Please see Figures 3-4 As shown, with Figure 1 Taking Q55 in the circuit as an example, because it is far from the positive and negative buses in the PCB layout, the voltage spikes generated when it is turned on are too high, such as... Figure 3 As shown, the voltage stress when the MOSFET is turned on is 613V, while the MOSFET's withstand voltage is 650V, which is less than 90% of the MOSFET's withstand voltage derating. Therefore, by connecting the chip capacitors C7, C46, ​​C5, and C25 in parallel with the positive and negative buses, the voltage stress after connecting the capacitors is as follows: Figure 4 The voltage is 581V, which is the derating voltage of the MOSFET. Therefore, this low-stress solution effectively reduces the voltage of the MOSFET by tens of volts, reduces costs, and has a simple structure.

[0040] Although the embodiments of this utility model have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for this utility model. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, this utility model is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A low stress three-phase Vienna circuit, characterized by: The circuit includes ports A, B, and C. Port A is connected to one end of inductor L2, and the other end of inductor L2 is connected to the positive terminal of diode D56 and the negative terminal of diode D27. Port B is connected to one end of inductor L4, and the other end of inductor L4 is connected to the positive terminal of diode D23 and the negative terminal of diode D7. Port C is connected to one end of inductor L6, and the other end of inductor L6 is connected to the positive terminal of diode D21 and the negative terminal of diode D30. The negative terminal of diode D56 is connected to the negative terminals of diode D23 and D21, one end of capacitor C46, ​​one end of capacitor C84, one end of capacitor C20, one end of capacitor C53, and port OUT+. The other end of capacitor C46 is connected to one end of capacitor C7. The other end of capacitor C7 is connected to one end of capacitor C5, one end of capacitor C4, one end of capacitor C84, one end of capacitor C65, one end of capacitor C20, one end of capacitor C101, one end of capacitor C53, one end of capacitor C9, and port GND. The other end of capacitor C5 is connected to one end of capacitor C25. The other end of capacitor C4 is connected to one end of capacitor C45. The positive terminal of diode D27 is connected to the positive terminal of diode D7, the positive terminal of diode D30, the other end of capacitor C25, the other end of capacitor C45, the other end of capacitor C65, the other end of capacitor C101, the other end of capacitor C9, and port OUT-. The other end of inductor L2 is connected to the drain of MOSFET Q21. The gate of MOSFET Q21 is connected to one end of resistor R237 and one end of inductor L31. The other end of inductor L31 is connected to the negative terminal of diode D71 and one end of resistor R248. The positive terminal of diode D71 is connected to one end of resistor R247 and the base of transistor Q52. The other end of resistor R247 is connected to port DRVA2. The other end of resistor R248 is connected to the emitter of transistor Q52. The source of MOSFET Q21 is connected to the source of MOSFET Q22, the other end of resistor R237, and resistor R249. One end of the transistor Q52, the collector of the transistor Q53, and the port GNDA; the gate of the MOSFET Q22 is connected to the other end of the resistor R249 and one end of the inductor L21; the other end of the inductor L21 is connected to one end of the resistor R543 and the negative terminal of the diode D102; the other end of the resistor R543 is connected to the emitter of the transistor Q53; the base of the transistor Q53 is connected to the positive terminal of the diode D102 and one end of the resistor R544; the other end of the resistor R544 is connected to the port DRVA1; the drain of the MOSFET Q22 is connected to the other end of the capacitor C7. The other end of inductor L4 is connected to the drain of MOSFET Q54. The gate of MOSFET Q54 is connected to one end of resistor R239 and one end of inductor L22. The other end of inductor L22 is connected to the negative terminal of diode D68 and one end of resistor R241. The positive terminal of diode D68 is connected to one end of resistor R242 and the base of transistor Q56. The other end of resistor R242 is connected to port DRVB1. The other end of resistor R241 is connected to the emitter of transistor Q56. The source of MOSFET Q54 is connected to the source of MOSFET Q55, the other end of resistor R239, and resistor R243. One end of the transistor Q55 is connected to the collector of transistor Q56, the collector of transistor Q57, and port GNDB. The gate of transistor Q55 is connected to the other end of resistor R243 and one end of inductor L24. The other end of inductor L24 is connected to one end of resistor R545 and the negative terminal of diode D103. The other end of resistor R545 is connected to the emitter of transistor Q57. The base of transistor Q57 is connected to the positive terminal of diode D103 and one end of resistor R546. The other end of resistor R546 is connected to port DRVB2. The drain of transistor Q55 is connected to the other end of capacitor C7. The other end of inductor L6 is connected to the drain of MOSFET Q27. The gate of MOSFET Q27 is connected to one end of resistor R222 and one end of inductor L27. The other end of inductor L27 is connected to the negative terminal of diode D58 and one end of resistor R223. The positive terminal of diode D58 is connected to one end of resistor R224 and the base of transistor Q58. The other end of resistor R224 is connected to port DRVC1. The other end of resistor R223 is connected to the emitter of transistor Q58. The source of MOSFET Q27 is connected to the source of MOSFET Q28, the other end of resistor R222, and resistor R223. One end of 5, the collector of transistor Q58, the collector of transistor Q59, and port GNDC; the gate of MOSFET Q28 is connected to the other end of resistor R225 and one end of inductor L32; the other end of inductor L32 is connected to one end of resistor R228 and the negative terminal of diode D167; the other end of resistor R228 is connected to the emitter of transistor Q59; the base of transistor Q59 is connected to the positive terminal of diode D67 and one end of resistor R229; the other end of resistor R229 is connected to port DRVC2; and the drain of MOSFET Q28 is connected to the other end of capacitor C7.

2. A low stress three-phase Vienna circuit according to claim 1, characterized in that: One end of capacitor C20 is connected to one end of resistor VR14, the other end of resistor VR14 is connected to one end of resistor VR15, the other end of resistor VR15 is connected to one end of resistor VR16, the other end of resistor VR16 is connected to one end of resistor VR17 and one end of capacitor C9, the other end of resistor VR17 is connected to one end of resistor VR18, the other end of resistor VR18 is connected to one end of resistor VR19, and the other end of resistor VR19 is connected to port OUT-.

3. A low stress three-phase Vienna circuit according to claim 1, characterized in that: Port A, port B, and port C are connected to three-phase electricity.

4. A low stress three-phase Vienna circuit according to claim 1, characterized in that: The OUT+ and OUT- ports output 400V voltage.

5. A low stress three-phase Vienna circuit according to claim 1, characterized in that: The ports GND, GNDA, GNDB, and GNDC are connected to different grounding terminals.

6. A low stress three-phase Vienna circuit according to claim 1, characterized in that: The low-stress three-phase Vienna circuit also includes a controller MCU, which is connected to ports DRVA1, DRVA2, DRVB1, DRVB2, DRVC1, and DRVC2.

7. A low stress three-phase Vienna circuit according to claim 1, characterized in that: MOSFETs Q21 and Q22 are simultaneously on and off, MOSFETs Q54 and Q55 are simultaneously on and off, and MOSFETs Q27 and Q28 are simultaneously on and off.

8. A low stress three-phase Vienna circuit according to claim 1, characterized in that: The capacitors C7 and C46 are low ESL film capacitors or ceramic capacitors with a capacitance range of 100nF-10μF.

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