Circuit configuration for a clock circuit

Abstract

The utility model discloses a kind of circuit structures for clock circuit, including asynchronous frequency divider, by multistage D flip-flop cascaded, be triggered by the output signal of clock circuit;Clock gating unit, when the count of the asynchronous frequency divider reaches setting parameter, and start output frequency division clock signal after, shield the signal output by current asynchronous frequency divider;Clock stable judgment logic circuit is used to carry out stability judgment to the signal shielded, wherein, when the judgment result is stable, the clock gating unit removes the shielding of current crystal oscillator clock signal, and current crystal oscillator clock signal is transmitted to digital circuit. Through the circuit structure for clock circuit of asynchronous frequency divider and gate clock technology, crystal oscillator clock is safely and reliably converted into the working clock of digital circuit.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuit technology, specifically to a circuit structure for a clock circuit. Background Technology

[0002] Chips typically use an internal clock (such as an RC oscillator) or an external clock (such as a crystal oscillator) as their system clock source. The clock, acting as the chip's "metronome," is the cornerstone of its efficient and reliable operation. During the process from power-on to stable operation, the clock circuit undergoes several stages: "oscillation startup - oscillation establishment - amplitude growth - stabilization." Due to factors such as power supply reliability, differences in power-on curves, and the characteristics of its own circuitry, the clock circuit's output frequency and amplitude exhibit significant uncertainty before stabilization. For the clock circuit, the "heart" of the chip, the clock output quality at this stage does not meet the standards required for safe and reliable chip operation.

[0003] To address the issue of unstable clock output during the initial power-up phase affecting chip reliability, a delay circuit is typically added internally to the chip to wait and shield against the unstable clock output phase. This delay circuit generally uses a clock-synchronous counter structure. Driven by the clock, the counter determines that the clock has reached a stable state once its count value reaches a certain level. The delay circuit then terminates, and the clock begins driving the chip's main circuit. Synchronous counter circuits are simple in structure and easy to implement.

[0004] During the chip power-on process, the synchronous counter delay circuit itself may have the following risks:

[0005] 1. Synchronous counter circuit failure. During the power-up voltage rise of the chip, the logic circuit module of the synchronous counter may start working before the voltage reaches the minimum normal operating voltage. Since the operation of the digital synchronous circuit requires strict adherence to timing requirements, an excessively low voltage will cause the entire synchronous counter circuit to fail and fail to achieve the timing delay effect.

[0006] Second: Synchronous counter counting error. In the initial stage of crystal oscillator startup, as the supply voltage is slowly rising, the signal amplitude of the crystal oscillator gradually increases. Before the clock outputs stably, some unexpected glitches or excessively fast clock edge signals will be generated. The abnormal clock may not meet the timing requirements of the synchronization circuit, causing the synchronous counter to count too fast or count incorrectly, thus losing its delay function. Summary of the Invention

[0007] The main objective of this invention is to provide a circuit structure for clock circuits to address the shortcomings in related technologies.

[0008] To achieve the above objectives, according to a first aspect of this utility model, a circuit structure for a clock circuit is provided, comprising: an asynchronous frequency divider, composed of multiple cascaded D flip-flops, triggered by the output signal of the clock circuit; a clock gating unit, which, when the count of the asynchronous frequency divider reaches a set parameter and begins to output a divided clock signal, shields the current output signal of the asynchronous frequency divider; and a clock stability judgment logic circuit, used to judge the stability of the shielded signal, wherein, when the judgment result is stable, the clock gating unit releases the shielding of the current crystal oscillator clock signal and transmits the current crystal oscillator clock signal to the digital circuit.

[0009] Optionally, in a cascaded multi-stage D flip-flop, the frequency-divided clock signal output by the previous stage flip-flop DFF_K is used as the clock input of the next stage flip-flop DFF_K+1; the inverted signal of the frequency-divided clock is fed back to the data input terminal of DFF_K.

[0010] Optionally, the number of cascaded stages is determined based on the time it takes for all circuit modules of the chip circuit to reach a voltage stability threshold during the power-on phase.

[0011] Optionally, when the clock stability judgment logic circuit detects that the clock output edge after the initial clock is divided by a multi-stage asynchronous frequency divider has a flipping edge, the stability is judged to be stable.

[0012] Optionally, if the clock stability judgment logic circuit detects that the clock output edge after the initial clock is divided by a multi-stage asynchronous frequency divider does not flip, the stability is judged as unstable.

[0013] This embodiment of the clock circuit structure includes an asynchronous frequency divider, composed of multiple cascaded D flip-flops, triggered by the output signal of the clock circuit; a clock gating unit, which shields the current output signal of the asynchronous frequency divider after the count of the asynchronous frequency divider reaches a set parameter and begins to output a divided clock signal; and a clock stability judgment logic circuit, used to judge the stability of the shielded signal. When the judgment result is stable, the clock gating unit releases the shielding of the current crystal oscillator clock signal and transmits the current crystal oscillator clock signal to the digital circuit. Through the asynchronous frequency divider and clock gating technology, the crystal oscillator clock is safely and reliably converted into the operating clock of the digital circuit. Attached Figure Description

[0014] To more clearly illustrate the specific embodiments of this utility model or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the circuit structure of a clock circuit according to an embodiment of the present invention;

[0016] Figure 2 This is a schematic diagram illustrating the application of the circuit structure for a clock circuit according to an embodiment of the present invention. Detailed Implementation

[0017] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0018] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the utility model described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0019] It should be noted that, where there is no conflict, the embodiments and features in the embodiments of this utility model can be combined with each other. The present utility model will now be described in detail with reference to the accompanying drawings and embodiments.

[0020] According to an embodiment of this utility model, a circuit structure for a clock circuit is provided. To avoid serious systemic risks caused by related technical problems, an asynchronous frequency divider and gated mode circuit structure are adopted in the power-on phase, thereby improving the safety and reliability of the chip clock circuit after startup.

[0021] like Figure 1As shown, the system includes an asynchronous frequency divider, which is composed of multiple cascaded D flip-flops. It is triggered by the output signal of a clock circuit. In the cascaded multi-stage D flip-flops, the divided clock signal output by the previous stage flip-flop DFF_K serves as the clock input for the next stage flip-flop DFF_K+1. The inverted signal of the divided clock is fed back to the data input of DFF_K. A clock gating unit blocks the current output signal of the asynchronous frequency divider when the count reaches a set parameter and the frequency divider starts outputting the divided clock signal. A clock stability judgment logic circuit is used to judge the stability of the blocked signal. When the judgment result is stable, the clock gating unit releases the blocking of the current crystal oscillator clock signal and transmits the current crystal oscillator clock signal to the digital circuit.

[0022] As an optional implementation of this embodiment, when the clock stability judgment logic circuit detects that the clock output edge after the initial clock is divided by a multi-stage asynchronous frequency divider has a flip, the stability is judged to be stable.

[0023] As an optional implementation of this embodiment, when the clock stability judgment logic circuit detects that the clock output edge after the initial clock is divided by a multi-stage asynchronous frequency divider does not flip, the stability is judged as unstable.

[0024] In the above-mentioned optional implementation, the clock stability determination circuit detects the clock output edge after the initial clock has been divided by a multi-stage asynchronous frequency divider, and determines clock stability based on this edge. For example, the edge of the output clock after multi-stage frequency divider division serves as a trigger for the clock stability determination circuit to drive the clock. Whether the clock flips determines if the asynchronous frequency divider has reached the set parameters. After detecting the clock edge, the clock stability determination circuit outputs a control signal to activate the clock gating unit.

[0025] As an optional implementation in this embodiment, in the cascaded multi-stage D flip-flops, the frequency-divided clock signal output by the previous stage flip-flop DFF_K is used as the clock input of the next stage flip-flop DFF_K+1; the inverted signal of the frequency-divided clock is fed back to the data input terminal of DFF_K.

[0026] As an optional implementation of this embodiment, the number of cascaded stages is determined based on the time it takes for all circuit modules of the chip circuit to reach a voltage stability threshold during the power-on phase.

[0027] During the critical power-on initialization phase of the chip, to ensure stable and reliable system operation, the frequency division factor of the system master clock must be scientifically set based on an accurate estimate of the time required for the power supply voltage to rise to the stable threshold of all modules. This ensures that the power supply voltage of all modules has reached the specified threshold during the clock frequency division period.

[0028] All circuit modules in the chip circuit are the chip's internal clock module (such as the RC oscillator) and circuits related to the internal clock power supply system (such as the chip's internal bandgap voltage reference and LDO voltage output module). The number of stages is related to the power-on stability characteristics of the clock IP, and generally an 8-16 stage asynchronous divider is used.

[0029] An asynchronous frequency divider is composed of multiple cascaded D flip-flops, with the output of the previous stage connected to the clock of the next stage. The clock circuit output drives the CLK of the first-stage D flip-flop, and each stage achieves frequency division by two when it flips on the effective edge of the clock. Output frequency = main frequency / 2^N (N is the number of stages).

[0030] After being processed by a frequency divider, the crystal oscillator clock signal is divided to a preset coefficient. To avoid interference and damage to subsequent digital circuit logic caused by timing instability (such as metastability, glitches, or frequency jitter) that may occur when the frequency divider powers on, a multi-stage asynchronous frequency divider is used. This exponentially reduces the interference of clock glitches, metastable states, and other problems on clock stability, significantly optimizing clock signal quality. Simultaneously, a gated clock mechanism is introduced. When the frequency divider count reaches the set parameter (based on the previous design, it is speculated that the corresponding CLK / 4 clock meets the basic requirements of a digital clock) and begins outputting the divided clock, the crystal oscillator clock signal is not immediately connected to the digital logic clock tree. Instead, it is temporarily shielded by the gated logic unit (CLK_EN is set to 0). The system monitoring logic continuously detects the stability of the divided clock. Only after the divided clock signal is confirmed to be running stably can the clock enable signal of the digital circuit be set through the gate (CLK_EN = 1). When the enable signal CLK_EN is active (CLK_EN=1), the gate logic is de-shielded, allowing the verified, stable crystal oscillator clock signal to pass through without glitches, thus safely transmitting it as the operating clock (CLK) for the digital circuit.

[0031] Considering that the chip may undergo multiple power-on and power-off cycles, the clock enable signal of the gated logic unit is set to an invalid value by default when the reset signal is valid. The crystal oscillator clock is shielded by the gated logic unit and is not provided to the digital circuit.

[0032] For example, after the crystal oscillator starts oscillating, its initial output signal serves as the clock input for the first-stage flip-flop (DFF_1). The output of DFF_1 contains two signals: a divided clock signal and its inverted signal. The divided clock signal serves as the clock input for the next-stage flip-flop (DFF_2). The inverted signal of the divided clock is fed back to the data input of DFF_1. This structure is cascaded and extended (and so on). The system determines the required number of division stages (i.e., the number of flip-flops) based on the clock accuracy requirements. After the division operation reaches a preset number of times, the stability of the divided clock signal is checked. If the divided clock is stable, it indicates that the original crystal oscillator clock has also reached a stable state (CLK_EN is set to 1), and only then can the source clock signal be safely transmitted to the digital circuit module. This process is one of the key steps to ensure reliable system startup.

[0033] This embodiment can precisely control the timing of clock activation, ensuring a clean, reliable, and interference-free timing reference for digital logic during the critical power-up phase before the power supply voltage is fully stable. This fundamentally avoids the risk of logic errors or system crashes that may be caused by unstable clocks.

[0034] refer to Figure 2 The diagram illustrates the digital clock waveform transmitted to the digital circuits after power-on. Due to potential instability during power-on, an asynchronous frequency divider circuit with a gating structure is employed. This diagram assumes that when the source clock REAL_CLK is divided to CLK / 4, a stable crystal oscillator output signal is detected. After the divided clock stabilizes, CLK_EN is set to 1, thereby releasing the stable crystal oscillator clock (CLK) to the digital circuits, providing a reliable and stable clock for the digital logic.

[0035] Compared to existing solutions, this design significantly reduces the probability of chip malfunctions and effectively avoids chip-level systemic risks that may be caused by power-on timing issues, thereby greatly improving the safety and reliability of the chip's internal clock circuit after startup. This design precisely controls the clock's activation timing, ensuring a clean, reliable, and interference-free timing reference for digital logic during the critical power-on phase before the power supply voltage is fully stable. For circuits with strict power-on timing requirements, the time it takes for all modules to reach the voltage stabilization threshold can be estimated in the early stages of the design. This reduces the required frequency division, simplifies the circuit structure, effectively reduces chip area, thereby lowering production costs and improving economic efficiency.

[0036] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A circuit structure for a clock circuit, characterized in that, The circuit structure operates within the chip's internal clock circuit and includes: An asynchronous frequency divider is composed of multiple cascaded D flip-flops and is triggered by the output signal of a clock circuit. In the cascaded multi-stage D flip-flops, the frequency-divided clock signal output by the previous stage flip-flop DFF_K serves as the clock input for the next stage flip-flop DFF_K+1; the inverted signal of the frequency-divided clock is fed back to the data input terminal of DFF_K. The clock gating unit, when the asynchronous frequency divider reaches the set parameter and starts outputting the frequency-divided clock signal, blocks the signal currently output by the asynchronous frequency divider; A clock stability judgment logic circuit is used to judge the stability of the shielded signal. When the judgment result is stable, the clock gating unit releases the shielding of the current crystal oscillator clock signal and transmits the current crystal oscillator clock signal to the digital circuit.

2. The circuit structure for a clock circuit according to claim 1, characterized in that, In a cascaded multi-stage D flip-flop, the divided clock signal output by the previous stage flip-flop DFF_K serves as the clock input for the next stage flip-flop DFF_K+1; the inverted signal of the divided clock is fed back to the data input of DFF_K.

3. The circuit structure for a clock circuit according to claim 2, characterized in that, The number of cascaded stages is determined based on the time it takes for all circuit modules of the chip circuit to reach a voltage stability threshold during the power-on phase.

4. The circuit structure for a clock circuit according to claim 1, characterized in that, When the clock stability judgment logic circuit detects that the clock output edge after the initial clock is divided by a multi-stage asynchronous frequency divider has a flipping edge, the stability is judged to be stable.

5. The circuit structure for a clock circuit according to claim 1, characterized in that, If the clock stability judgment logic circuit detects that the clock output edge after the initial clock is divided by a multi-stage asynchronous frequency divider does not flip, then the stability is judged as unstable.

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