A circuit for filtering echo signals from single-ended input signals of asynchronous serial communication

Abstract

The utility model provides a kind of circuit of filtering back read signal of asynchronous serial communication single-ended input signal, the circuit includes: input circuit, level delay circuit and output circuit;The input circuit is provided with an input port and an output port, the level delay circuit is provided with an input port and an output port, the output circuit is provided with at least two input ports and an output port;Its connection relationship is as follows: the single-ended input signal is connected with the input port of the input circuit, the output port of the input circuit is connected with the input interface of the level delay circuit, the output interface of the level delay circuit is connected with one of the input port of the output circuit, the back read signal is connected with another input port of the output circuit;The utility model can effectively filter back read signal of asynchronous serial communication single-ended input signal, applicable to the occasion without the back read signal.

Description

Technical Field

[0001] This utility model relates to the field of communication technology, specifically a circuit for filtering the readback signal of a single-ended input signal in asynchronous serial communication. Background Technology

[0002] Asynchronous serial communication interface chips are used to convert single-ended level signals such as TTL and CMOS, which are only suitable for short-distance transmission, into differential signals or single-ended signals with higher swing amplitude suitable for long-distance transmission, for the purpose of local area network (LAN) networking. In high-reliability scenarios, taking CAN bus interface chips and LIN bus interface chips as examples, in order to improve the reliability of LAN communication, the chip detects errors or whether arbitration has been lost during its own transmission process by reading back the data transmitted on the LAN bus. However, for example, in data pass-through applications, processing the read-back signal will bring additional workload to the product design.

[0003] Existing solutions include: Option 1 involves filtering the readback signal by programming a microprocessor or bus controller. This option increases the cost of both hardware and software and also introduces additional data transmission delays.

[0004] Option 2 filters out the readback signal by building a simple logic circuit and flip-flop digital circuit. However, there is a delay of tens or even hundreds of nanoseconds between the input of the single-ended input signal and the output of the readback signal. This requires multiple logic circuits and flip-flop circuits to be cascaded. Furthermore, the transmission delay of the logic circuit is affected by differences in voltage, temperature, and input high and low level thresholds, making it difficult to guarantee the consistency and stability of the circuit. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the purpose of this invention is to provide a circuit for filtering the readback signal of a single-ended input signal in asynchronous serial communication.

[0006] The circuit for filtering the readback signal of the single-ended input signal of asynchronous serial communication includes: an input circuit, a level delay circuit, and an output circuit; The input circuit is used to invert the level of the single-ended input signal, and the input circuit is provided with an input port and an output port; The level delay circuit is used to extend the high-level holding time of the inverted single-ended input signal. The level delay circuit is provided with an input port and an output port. The output circuit is used to output the readback signal after filtering out the single-ended input signal. The output circuit is provided with at least two input ports and one output port. The working logic of the output circuit is as follows: when all its input ports are low level, its output port outputs a low level; otherwise, its output port outputs a high level. The connection relationship between the single-ended input signal, the readback signal, the input circuit, the level delay circuit, and the output circuit is as follows: the single-ended input signal is connected to the input port of the input circuit, the output port of the input circuit is connected to the input interface of the level delay circuit, the output interface of the level delay circuit is connected to one of the input ports of the output circuit, and the readback signal is connected to the other input port of the output circuit.

[0007] Preferably, the input circuit is any one of the following: voltage / current inverting driver, voltage / current inverting amplifier, NOT gate / NAND gate / NOR gate circuit, Smith trigger, opto-isolator, magnetic coupling isolator, which can invert the level of the single-ended input signal.

[0008] Preferably, the level delay circuit includes a diode D1, a resistor R1, and a capacitor C1; The positive terminal of diode D1 serves as the input port of the level delay circuit. The negative terminal of diode D1 is connected to one end of resistor R1 and one end of capacitor C1, serving as the output port of the level delay circuit. The other end of resistor R1 and the other end of capacitor C1 are grounded. Preferably, the output circuit is an OR gate circuit or other circuits that can satisfy the working logic of the output circuit.

[0009] A further preferred embodiment is that the input port of the output circuit is connected in series with any one of the following circuits: a voltage comparator, a hysteresis comparator, or a Schmitt trigger. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A schematic diagram of the overall framework of the circuit for filtering the readback signal of the single-ended input signal of asynchronous serial communication provided by this utility model.

[0012] Figure 2The circuit provided by this utility model for filtering the readback signal of the single-ended input signal of asynchronous serial communication involves a first waveform, a second waveform, a third waveform, a fourth waveform, and a fifth waveform.

[0013] Figure 3 This invention provides a circuit implementation example for filtering the readback signal of a single-ended input signal in asynchronous serial communication.

[0014] Figure 4 This invention provides an example of an extended circuit implementation for the first type of circuit for filtering out readback signals from single-ended input signals in asynchronous serial communication.

[0015] Figure 5 This invention provides an example of an extended circuit implementation for the second type of asynchronous serial communication single-ended input signal filtering readback signal circuit.

[0016] Figure 6 The circuit provided by this utility model for filtering the readback signal of the single-ended input signal of asynchronous serial communication is used in the mutual transparent transmission of CAN bus signals and single-ended signals.

[0017] Figure 7 The circuit for filtering the readback signal of the single-ended input signal of asynchronous serial communication provided by this utility model is used in the mutual transparent transmission of LIN bus signals and single-ended signals. Detailed Implementation

[0018] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. It should be noted that while the description of these embodiments is intended to aid in understanding the present invention, it does not constitute a limitation thereof. The specific structural and functional details disclosed herein are only for describing exemplary embodiments of the present invention. However, the present invention may be embodied in many alternative forms and should not be construed as being limited to the embodiments described herein.

[0019] It should be understood that although the terms "first" and "second", etc., may be used herein to describe various objects, these objects should not be limited by these terms. These terms are only used to distinguish one object from another. For example, the first object may be referred to as the second object, and similarly, the second object may be referred to as the first object, without departing from the scope of the exemplary embodiments of this utility model.

[0020] It should be understood that the term "and / or" that may appear in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, B exists alone, or A and B exist simultaneously. The term " / and" that may appear in this document describes another relationship between related objects, indicating that two relationships can exist. For example, A / and B can mean: A exists alone or A and B exist simultaneously. In addition, the character " / " that may appear in this document generally indicates that the related objects before and after it are in an "or" relationship.

[0021] like Figure 1 As shown: Figure 1 A schematic diagram of the overall framework of the circuit for filtering the readback signal of the single-ended input signal of asynchronous serial communication provided by this utility model; The circuit for filtering the readback signal of the single-ended input signal of asynchronous serial communication includes: an input circuit, a level delay circuit, and an output circuit; The input circuit is provided with an input port and an output port; The level delay circuit has an input port and an output port. The output circuit is provided with at least two input ports and one output port; The connection relationship between the single-ended input signal, the readback signal, the input circuit, the level delay circuit, and the output circuit is as follows: the single-ended input signal is connected to the input port of the input circuit, the output port of the input circuit is connected to the input interface of the level delay circuit, the output interface of the level delay circuit is connected to one of the input ports of the output circuit, and the readback signal is connected to the other input port of the output circuit.

[0022] like Figure 2 As shown: Figure 2 The circuit provided by this utility model for filtering the readback signal of the single-ended input signal of asynchronous serial communication involves a first waveform, a second waveform, a third waveform, a fourth waveform, and a fifth waveform.

[0023] like Figure 3 As shown: Figure 3 This invention provides a circuit implementation example for filtering the readback signal of a single-ended input signal in asynchronous serial communication.

[0024] Depend on Figure 3 As shown: The circuit includes an input circuit implemented by NOT gate chip U1, a level delay circuit composed of resistor R1, capacitor C1 and diode D1, and an output circuit implemented by OR gate U2.

[0025] The connection relationship is as follows: the single-ended input signal is connected to the input pin of the NOT gate chip U1, the output pin of the NOT gate chip U1 is connected to the positive terminal of the diode D1, the negative terminal of the diode D1 is connected to one pin of the resistor R1, one pin of the capacitor C1, and one input pin of the OR gate U2, the other pin of the resistor R1 is connected to the reference ground, the other pin of the capacitor C1 is connected to the reference ground, the readback signal is connected to the other input pin of the OR gate U2, and the output pin of the OR gate U2 outputs a signal that filters out the readback signal of the asynchronous serial communication single-ended input signal.

[0026] like Figure 4 As shown: Figure 4 The first example provided is an extended circuit implementation of a circuit for filtering readback signals from single-ended input signals in asynchronous serial communication. Figure 3 Based on the circuit shown for filtering the readback signal of the single-ended input signal of asynchronous serial communication, a Schmitt trigger U3 is connected in series at one input pin of the output circuit U2. Specifically, the input pin of the Schmitt trigger U3 is connected to the negative terminal of the diode D1, one pin of the resistor R1, and one pin of the capacitor C1. The output pin of the Schmitt trigger U3 is connected to one input pin of the output circuit U2.

[0027] The advantages of the series Schmitt trigger U3 are: the Schmitt trigger is a threshold switching circuit with bistable and hysteretic characteristics, which can improve waveform shaping capability and strong anti-interference ability.

[0028] like Figure 5 As shown: Figure 5 This invention provides an example of an extended circuit implementation for the second type of asynchronous serial communication single-ended input signal filtering readback signal circuit. Figure 3 Based on the circuit shown for filtering the readback signal of the single-ended input signal of asynchronous serial communication, a voltage comparator U3 is connected in series at one input pin of the output circuit U2. Specifically, the positive terminal of the input pin of the voltage comparator U3 is connected to the negative terminal of the diode D1, one pin of the resistor R1, and one pin of the capacitor C1; the negative terminal of the input pin of the voltage comparator U3 is connected to one pin of R2 and R3, the other pin of R2 is connected to the power supply, and the other pin of R3 is connected to the reference ground; the output pin of the voltage comparator U3 is connected to one input pin of the output circuit U2.

[0029] The advantage of connecting the voltage comparator U3 in series is that the input voltage value that causes the voltage comparator output voltage to flip between high and low can be precisely set, avoiding the circuit parameter differences caused by the uncertain voltage region between the high and low levels of the digital circuit input, improving product consistency and facilitating mass production.

[0030] This embodiment, specifically the first circuit embodiment, is as follows: Figure 6 The circuit shown is for filtering the readback signal of the single-ended input signal in asynchronous serial communication, and is used to realize the mutual pass-through between CAN bus signals and single-ended signals.

[0031] like Figure 6 As shown: The SN65HVD232 chip U4 has two data ports, single-ended and differential. The single-ended port includes the DI pin and the RO pin. The differential port includes two CAN level input and output pins, CANH and CANL. U4 sends single-ended data to the CANH and CANL pins of the CAN bus through the DI pin. The RO pin is continuously read back by the monitor through the CANH and CANL pins on the CAN bus. The whole process has a time delay of tens to hundreds of nanoseconds.

[0032] like Figure 6 The circuit shown for filtering the readback signal of the single-ended input signal in asynchronous serial communication includes: an input circuit implemented by a NOT gate chip U1 (the input circuit can also be any one of the following circuits that can invert the single-ended input level: voltage / current inverting driver, voltage / current inverting amplifier, NAND gate / OR NOT gate circuit, Smith trigger, opto-isolator, magnetic coupling isolator), a level delay circuit composed of resistor R1, capacitor C1, and diode D1, and an output circuit implemented by an OR gate U2 (the operating logic of the output circuit is: when all input ports are low, the output port of the output circuit outputs a low level; otherwise, the output port of the output circuit outputs a high level; the output circuit can also be other circuits that can satisfy the operating logic of the output circuit).

[0033] The circuit for filtering the readback signal of the single-ended input signal of asynchronous serial communication is connected to the SN65HVD232 chip U4 as follows: the DI pin of U4 and the input pin of U1 are shorted together, designated as node A (node ​​A is...). Figure 2 The first waveform acquisition point is shown); short-circuit one of the input pins of U2 and the RO pin of U4, and set it as node D (node ​​D is...). Figure 2 (The fourth waveform acquisition point is shown); let the output pin of U2 be node E (node ​​E is...) Figure 2 The fifth waveform acquisition point is shown); additionally, let the output pin of U1 be node B (node ​​B is...). Figure 2 (The second waveform acquisition point shown), let the negative terminal of D1 be node C (node ​​C is...) Figure 2(The third waveform acquisition point shown).

[0034] The working principle of this circuit embodiment is as follows: The data to be sent is serially input to node A. When the data is in an idle state ( Figure 2 The first waveform shown is in the time period before the first falling edge: Node A is at a high level, Node B after U1 is inverted is at a low level, Diode D1 is in the off state, Capacitor C1 discharges through Resistor R1, the voltage of Node C drops, and after a discharge cycle, it finally stabilizes at a low level, Node D is at a high level in the idle state, and Node E (U2 or the voltage of Node C and Node D) outputs a high level.

[0035] When the data stream to be sent transmits valid low-level data, such as Figure 2 The first waveform shown, upon the arrival of the falling edge: node A flips to a low level, node B, after being inverted by U1, flips to a high level, capacitor C1 is charged through diode D1, and the voltage at node C rises exponentially according to a capacitor charging curve. Figure 2 (As shown in the third waveform), after a delay of time T1, node D flips to a low level. The parameters of capacitor C1 are set so that the time when point C rises to the high level threshold of U2 is earlier than the time when node D flips to a low level, so as to ensure that at least one of node C and node D is at a high level, and node E (the output of U2) remains at a high level. like Figure 2 When the rising edge of the first waveform shown arrives: node A flips to a high level, node B, after being inverted by U1, flips to a low level, the voltage of node C is higher than the voltage of node B, diode D1 is in the off state, capacitor C1 discharges through resistor R1, and the voltage of node C drops according to the capacitor discharge exponential curve. Figure 2 (As shown in the third waveform), node D flips to a high level after a time delay of T2. The parameters of resistor R1 are set so that the time when the voltage at point C drops to the low-level threshold of U2 is later than the time when node D flips to a high level, ensuring that at least one of nodes C and D is at a high level, while node E (and the output of U2) remains at a high level; thus completing the process. Figure 2 The fourth waveform shown is filtered out.

[0036] When the data stream to be sent has been completed (e.g.) Figure 2After the last rising edge of the first waveform shown arrives, when CAN bus data needs to be received: Node B, after being inverted by U1, remains at a low level. Node C, after a discharge cycle of capacitor C1 (setting the parameters of R1 to ensure that the voltage of node C is lower than the low voltage threshold of U2 before the falling edge of node D receives data), has a voltage lower than the low level threshold of U2 and remains at a low level. The output of node E (which calculates the voltages of node C and node D using U2) is consistent with the voltage of node D, ensuring effective reception of CAN bus data.

[0037] The circuit in this embodiment can effectively filter out readback signals from single-ended input signals in serial communication. Its advantages are: First: The delay generated by the circuit is only a few tens of nanoseconds at most, which will not affect the real-time performance of communication; Second: The circuit delay function is mainly accomplished by diodes, capacitors and resistors, which are stable, reliable and inexpensive.

[0038] In this embodiment, the specific implementation of the second circuit is as follows: Figure 7 As shown: The circuit provided is for filtering the readback signal of the single-ended input signal in asynchronous serial communication. This implementation example uses the following... Figure 4 The example shown is an extended circuit implementation of the first type of asynchronous serial communication single-ended input signal filtering readback signal circuit, which realizes the mutual pass-through of LIN bus signals and single-ended signals.

[0039] like Figure 7 As shown: The SIT1021 chip U4 has two data ports: a single-ended port and a LIN bus. The single-ended port includes an RXD pin and a TXD pin. The LIN bus includes a LIN pin, which has both input and output functions.

[0040] The U4 sends single-ended data to the LIN pin of the LIN bus via the TXD pin, and the RXD pin is continuously read back by the LIN pin monitor on the LIN bus. The whole process will have a delay of several microseconds.

[0041] like Figure 7 The circuit shown is for filtering the readback signal of the single-ended input signal of asynchronous serial communication: it includes an input circuit implemented by a NOT gate chip U1, a level delay circuit composed of a resistor R1, a capacitor C1, and a diode D1, and an output circuit composed of a Schmitt trigger U3 connected in series with an OR gate U2.

[0042] The circuit for filtering the readback signal of the single-ended input signal of asynchronous serial communication is connected to the SIT1021 chip U4 as follows: the DI pin of U4 and the input pin of U1 are shorted together, designated as node A (node ​​A is...). Figure 2The first waveform acquisition point is shown); short-circuit one of the input pins of U2 and the RO pin of U4, and set it as node D (node ​​D is...). Figure 2 (The fourth waveform acquisition point is shown); let the output pin of U2 be node E (node ​​E is...) Figure 2 The fifth waveform acquisition point is shown); additionally, let the output pin of U1 be node B (node ​​B is...). Figure 2 (The second waveform acquisition point shown), let the negative terminal of D1 be node C (node ​​C is...) Figure 2 (The third waveform acquisition point shown).

[0043] The working principle of this circuit embodiment is as follows: 1. The data to be sent is serially input to node A. When the data is in an idle state ( Figure 2 The first waveform shown is in the time period before the first falling edge: Node A is at a high level, Node B after U1 is inverted is at a low level, Diode D1 is in the off state, Capacitor C1 discharges through Resistor R1, the voltage of Node C drops, and after a discharge cycle, it finally stabilizes at a low level, Node D is at a high level in the idle state, and Node E (U2 or the voltage of Node C and Node D) outputs a high level.

[0044] 2. When the data stream to be sent transmits valid low-level data, such as... Figure 2 The first waveform shown, upon the arrival of the falling edge: node A flips to a low level, node B, after being inverted by U1, flips to a high level, capacitor C1 is charged through diode D1, and the voltage at node C rises exponentially according to a capacitor charging curve. Figure 2 (As shown in the third waveform), after a time delay of T1, node D flips to a low level. The parameters of capacitor C1 are set so that the time when point C rises to the high level threshold of Schmitt trigger U3 is earlier than the time when node D flips to a low level, so as to ensure that at least one of node C and node D is at a high level, and node E (the output of U2) remains at a high level. like Figure 2 When the rising edge of the first waveform shown arrives: node A flips to a high level, node B, after being inverted by U1, flips to a low level, the voltage of node C is higher than the voltage of node B, diode D1 is in the off state, capacitor C1 discharges through resistor R1, and the voltage of node C drops according to the capacitor discharge exponential curve. Figure 2(As shown in the third waveform), node D flips to a high level after a time delay of T2. The parameters of resistor R1 are set so that the time when the voltage at point C drops to the low-level threshold of Schmitt trigger U3 is later than the time when node D flips to a high level. This ensures that at least one of the outputs of Schmitt trigger U3 and node D is high, while node E (and the output of U2) remains high. This completes the process of... Figure 2 The fourth waveform shown is filtered out.

[0045] 3. When the data stream to be sent has been completed (e.g.) Figure 2 After the last rising edge of the first waveform shown arrives, when LIN bus data needs to be received: Node B, after being inverted by U1, remains at a low level. Node C, after the discharge cycle of capacitor C1 (setting the parameters of R1 to ensure that before the falling edge of data reception at node D arrives, the voltage of node C is already lower than the low voltage threshold of Schmitt trigger U3), has a voltage lower than the low level threshold of Schmitt trigger U3 and remains at a low level. The output of Schmitt trigger U3 remains at a low level. The output of node E (the output of U2 or the output of Schmitt trigger U3, and the voltage of node D) is consistent with the voltage of node D, ensuring effective reception of LIN bus data.

[0046] The circuit in this embodiment can effectively filter out readback signals from single-ended input signals in serial communication. Its advantages are: First: The delay generated by the circuit is only a few tens of nanoseconds at most, which will not affect the real-time performance of communication; Second: The circuit delay function is mainly achieved by diodes, capacitors and resistors, which are stable, reliable and inexpensive; Third: A Schmitt trigger is connected in series at the input of the output circuit, providing strong anti-interference capability.

[0047] Finally, it should be noted that this utility model is not limited to the above-described optional embodiments, and anyone can derive other various forms of products under the guidance of this utility model. The specific embodiments described above should not be construed as limiting the scope of protection of this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the scope of protection of this utility model. The scope of protection of this utility model shall be determined by the claims, and the description can be used to interpret the claims.

Claims

1. A circuit for filtering the readback signal of a single-ended input signal in asynchronous serial communication, characterized in that... The circuit includes: an input circuit, a level delay circuit, and an output circuit; The input circuit is used to invert the level of the single-ended input signal, and the input circuit is provided with an input port and an output port; The level delay circuit is used to extend the high-level holding time of the inverted single-ended input signal. The level delay circuit is provided with an input port and an output port. The output circuit is used to output the readback signal after filtering out the single-ended input signal. The output circuit is provided with at least two input ports and one output port. The working logic of the output circuit is as follows: when all its input ports are low level, its output port outputs a low level; otherwise, its output port outputs a high level. The connection relationships between the single-ended input signal, the readback signal, the input circuit, the level delay circuit, and the output circuit are as follows: the single-ended input signal is connected to the input port of the input circuit, the output port of the input circuit is connected to the input interface of the level delay circuit, the output interface of the level delay circuit is connected to one of the input ports of the output circuit, and the readback signal is connected to the other input port of the output circuit.

2. The circuit for filtering the readback signal of a single-ended input signal in asynchronous serial communication according to claim 1, characterized in that, The input circuit is any one of the following: voltage / current inverting driver, voltage / current inverting amplifier, NOT gate / NAND gate / OR NOT gate circuit, Smith trigger, opto-isolator, magnetic coupling isolator, which can invert the level of the single-ended input signal.

3. The circuit for filtering the readback signal of a single-ended input signal in asynchronous serial communication according to claim 1, characterized in that, The level delay circuit includes a diode D1, a resistor R1, and a capacitor C1; The positive terminal of diode D1 serves as the input port of the level delay circuit. The negative terminal of diode D1 is connected to one end of resistor R1 and one end of capacitor C1 to serve as the output port of the level delay circuit. The other end of resistor R1 and the other end of capacitor C1 are connected to the reference ground.

4. The circuit for filtering the readback signal of a single-ended input signal in asynchronous serial communication according to claim 1, characterized in that, The output circuit is specifically an OR gate circuit or other circuits that can satisfy the working logic of the output circuit.

5. The circuit for filtering the readback signal of a single-ended input signal in asynchronous serial communication according to claim 4, characterized in that, The input port of the output circuit is connected in series with any one of the following circuits: a voltage comparator, a hysteresis comparator, or a Schmitt trigger.

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