A multi-channel synchronously triggered photoelectric detection module driving circuit

Abstract

This invention relates to the field of photoelectric detection, specifically a multi-channel synchronously triggered photoelectric detection module driver circuit. It includes a reference trigger signal generation unit, a synchronous trigger signal generation unit, and a multi-channel trigger signal equalization transmission unit. The reference trigger signal generation unit comprises a signal generation circuit and a signal preprocessing circuit. The output of the signal generation circuit is connected to the input of the signal preprocessing circuit, and the output of the signal preprocessing circuit is connected to the inputs of the synchronous trigger signal generation circuit and the multi-channel trigger signal equalization transmission unit. The output of the synchronous trigger signal generation circuit is connected to the input of the multi-channel trigger signal equalization transmission unit. This invention achieves synchronous trigger signals by superimposing a reference trigger signal and a synchronous clock, and uses logic gate circuits to achieve timing binding of the two signals, ensuring complete alignment of the four trigger signals in the time dimension.

Description

Technical Field

[0001] This utility model relates to the field of photoelectric detection, specifically a multi-channel synchronously triggered photoelectric detection module drive circuit. Background Technology

[0002] In photoelectric detection systems, when multiple cameras need to be triggered in parallel to generate a video stream, a multi-channel photoelectric triggering module is required. Existing multi-channel photoelectric detection modules typically employ one of two design schemes: "single trigger source – multiple branches" or "multiple trigger sources – independent control".

[0003] Single trigger source-multi-branch scheme: A single trigger signal source is branched through wires and connected to each channel drive unit. Although the trigger signals can be from the same source, the difference in the length of the wires and parasitic parameters (such as capacitance and inductance) of each branch results in a delay in the arrival time of the trigger signal to each channel drive unit. This causes the acquisition start time of the multi-channel detection signals to be asynchronous. Especially in high-frequency scenarios (such as microsecond-level periods), the synchronization error can reach tens to hundreds of nanoseconds, which seriously affects the consistency and accuracy of camera triggering. Multi-trigger source-independent control scheme: Each channel is configured with an independent trigger signal generation unit. The output timing of each trigger source is coordinated by an external controller. Although the synchronization error can be reduced by software calibration, it requires additional computing load on the controller. It is also limited by the consistency of the trigger source hardware circuit (such as crystal oscillator accuracy and logic gate delay). During long-term operation, the synchronization accuracy is prone to decrease due to temperature drift and voltage fluctuation. At the same time, the circuit structure is complex and costly, making it unsuitable for miniaturized and low-cost devices. Utility Model Content

[0004] To address the shortcomings of existing technologies, this utility model discloses a multi-channel synchronously triggered photoelectric detection module driving circuit. The core logic is a logical combination of a reference trigger signal and a synchronous clock. The timing of the two signals is bound together through logic gate circuits to ensure that the multiple trigger signals are fully aligned in the time dimension.

[0005] To solve the aforementioned technical problem, the present invention adopts the following technical solution: a multi-channel synchronously triggered photoelectric detection module driving circuit, comprising a reference trigger signal generation unit, a synchronous trigger signal generation unit, and a multi-channel trigger signal equalization transmission unit. The reference trigger signal generation unit includes a signal generation circuit and a signal preprocessing circuit. The output terminal of the signal generation circuit is connected to the input terminal of the signal preprocessing circuit. The output terminal of the signal preprocessing circuit is connected to the input terminals of the synchronous trigger signal generation circuit and the multi-channel trigger signal equalization transmission unit. The output terminal of the synchronous trigger signal generation circuit is connected to the input terminal of the multi-channel trigger signal equalization transmission unit. The signal generation circuit generates a reference trigger signal and transmits it to the signal preprocessing circuit. The signal preprocessing circuit preprocesses the reference trigger signal and transmits the preprocessed reference trigger signal to the synchronous trigger signal generation unit and the multi-channel trigger signal equalization transmission unit. The synchronous trigger signal generation unit divides the reference trigger signal into multiple synchronous clocks and transmits them to the multi-channel trigger signal equalization transmission unit. Each clock corresponds to one channel of trigger signal. The multi-channel trigger signal equalization transmission unit performs AND operations between the preprocessed reference trigger signal and the multiple synchronous clocks to obtain the multi-channel trigger signal of the photoelectric detection module.

[0006] Furthermore, the signal generation circuit uses an STM32 microcontroller, which generates and outputs a clock signal as a reference trigger signal.

[0007] Furthermore, the signal preprocessing circuit is a Schmitt trigger, the input of which is connected to the output of the signal generation circuit, and the output of which is connected to the input of the synchronous trigger signal generation unit and the multi-channel trigger signal equalization transmission unit.

[0008] Furthermore, the synchronous trigger signal generation unit uses a clock distribution chip, specifically the CDCE62005.

[0009] Furthermore, the multi-channel trigger signal equalization transmission unit uses an AND gate chip; the AND gate chip has multiple AND gates, and the number of AND gates involved in the calculation is the same as the number of synchronous clock channels. The inputs of each AND gate are the preprocessed reference trigger signal and a single synchronous clock channel, respectively, and the output of each AND gate is a single-channel trigger signal.

[0010] Furthermore, the preprocessed reference trigger signal maintains the same level as the multi-channel trigger signal.

[0011] Furthermore, the synchronous trigger signal generation unit divides the reference trigger signal into four synchronous clocks.

[0012] The beneficial effects of this utility model are as follows: The multi-channel synchronous triggering photoelectric detection module driving circuit of this utility model fundamentally solves the pain points of the prior art through the integrated design of "logical combination of reference trigger signal and synchronous clock". The specific innovative differences and advantages are as follows: Multi-channel triggering is realized by adopting the hardware native synchronization method. The CDCE62005 is used as the core clock distribution chip. Its output multi-channel trigger signals are processed in coordination with the reference trigger signal to ensure that each effective pulse of the trigger signal is strictly synchronized with the clock edge of the reference trigger signal, avoiding timing offset of the trigger pulse, thereby generating a high-precision synchronous trigger signal. Attached Figure Description

[0013] Figure 1This is the schematic diagram of the reference trigger signal generation unit; Figure 2 This is a schematic diagram of the synchronous trigger signal generation unit; Figure 3 This is a schematic diagram of a multi-path trigger signal equalization transmission unit. Detailed Implementation

[0014] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0015] Example 1 This utility model discloses a multi-channel synchronously triggered photoelectric detection module driving circuit, including a reference trigger signal generation unit, a synchronous trigger signal generation unit, and a multi-channel trigger signal equalization transmission unit. The reference trigger signal generation unit includes a signal generation circuit and a signal preprocessing circuit. The output terminal of the signal generation circuit is connected to the input terminal of the signal preprocessing circuit. The output terminal of the signal preprocessing circuit is connected to the input terminals of the synchronous trigger signal generation circuit and the multi-channel trigger signal equalization transmission unit. The output terminal of the synchronous trigger signal generation circuit is connected to the input terminal of the multi-channel trigger signal equalization transmission unit.

[0016] The signal generation circuit generates a reference trigger signal and transmits it to the signal preprocessing circuit. The signal preprocessing circuit preprocesses the reference trigger signal and transmits the preprocessed signal to the synchronous trigger signal generation unit and the multi-channel trigger signal equalization transmission unit. The synchronous trigger signal generation unit divides the reference trigger signal into multiple synchronous clocks and transmits them to the multi-channel trigger signal equalization transmission unit. Each clock corresponds to one channel of the trigger signal. The multi-channel trigger signal equalization transmission unit performs AND operations between the preprocessed reference trigger signal and each of the multiple synchronous clocks to obtain the multi-channel trigger signal for the photoelectric detection module. In this embodiment, the synchronous trigger signal generation unit divides the reference trigger signal into four synchronous clocks and transmits them to the multi-channel trigger signal equalization transmission unit.

[0017] like Figure 1 As shown, the signal generation circuit uses an STM32 microcontroller, which generates and outputs a clock signal CLK as the reference trigger signal. The signal preprocessing circuit is a Schmitt trigger, with its input connected to the output of the signal generation circuit. The output of the Schmitt trigger is connected to the inputs of the synchronous trigger signal generation unit and the multi-channel trigger signal equalization transmission unit. The reference trigger signal is level-normalized by a Schmitt trigger 74HC14, outputting the preprocessed reference trigger signal PR1_REFP. The Schmitt trigger ensures that the high level of the trigger signal PR1_REFP is stable at 3.3V and the low level is stable at 0V, consistent with the level standard of the final multi-channel trigger signal CLK_OUT.

[0018] like Figure 2 As shown, the synchronous trigger signal generation unit uses the clock distribution chip CDCE62005. The clock distribution chip CDCE62005 divides the 1 reference trigger signal PR1_REFP into 4 synchronous clocks YP0, YP1, YP2 and YP3, with each clock corresponding to the trigger signal of one channel.

[0019] like Figure 3 As shown, the multi-channel trigger signal equalization transmission unit uses an AND gate chip, specifically a four-input AND gate chip 74HC08. The inputs of each AND gate are the pre-processed reference trigger signal and a single-channel synchronous clock, respectively, and the output of each AND gate is a single-channel trigger signal. The pre-processed reference trigger signal PR1_REFP is logically ANDed with the corresponding channel trigger signals YP0, YP1, YP2, and YP to generate synchronous trigger signals CLK_OUT0, CLK_OUT1, CLK_OUT2, and CLK_OUT3. The specific principle is as follows: the AND gate outputs a high level (trigger valid) only when both the reference trigger signal and the corresponding channel trigger signal are high; otherwise, it outputs a low level (trigger invalid). This design ensures that each valid pulse of the trigger signal is strictly synchronized with the clock edge of the reference trigger signal, avoiding timing offsets in the trigger pulses.

[0020] This invention achieves synchronous triggering of the photoelectric detection module by precisely superimposing a "reference trigger signal + synchronous clock", and uses logic gate circuits to achieve timing binding of the two signals, ensuring that the four trigger signals are completely aligned in the time dimension.

[0021] The above description is only the basic principle and preferred embodiment of this utility model. Any improvements and substitutions made by those skilled in the art based on this utility model shall fall within the protection scope of this utility model.

Claims

1. A driving circuit for a multi-channel synchronously triggered photoelectric detection module, characterized in that: It includes a reference trigger signal generation unit, a synchronous trigger signal generation unit, and a multi-channel trigger signal equalization transmission unit. The reference trigger signal generation unit includes a signal generation circuit and a signal preprocessing circuit. The output terminal of the signal generation circuit is connected to the input terminal of the signal preprocessing circuit. The output terminal of the signal preprocessing circuit is connected to the input terminals of the synchronous trigger signal generation circuit and the multi-channel trigger signal equalization transmission unit. The output terminal of the synchronous trigger signal generation circuit is connected to the input terminal of the multi-channel trigger signal equalization transmission unit. The signal generation circuit generates a reference trigger signal and transmits it to the signal preprocessing circuit. The signal preprocessing circuit preprocesses the reference trigger signal and transmits the preprocessed reference trigger signal to the synchronous trigger signal generation unit and the multi-channel trigger signal equalization transmission unit. The synchronous trigger signal generation unit divides the reference trigger signal into multiple synchronous clocks and transmits them to the multi-channel trigger signal equalization transmission unit. Each clock corresponds to one channel of trigger signal. The multi-channel trigger signal equalization transmission unit performs AND operations between the preprocessed reference trigger signal and the multiple synchronous clocks to obtain the multi-channel trigger signal of the photoelectric detection module.

2. The multi-channel synchronously triggered photoelectric detection module driving circuit according to claim 1, characterized in that: The signal generation circuit uses an STM32 microcontroller, which generates and outputs a clock signal as a reference trigger signal.

3. The multi-channel synchronously triggered photoelectric detection module driving circuit according to claim 1, characterized in that: The signal preprocessing circuit is a Schmitt trigger. The input of the Schmitt trigger is connected to the output of the signal generation circuit, and the output of the Schmitt trigger is connected to the input of the synchronous trigger signal generation unit and the multi-channel trigger signal equalization transmission unit.

4. The multi-channel synchronously triggered photoelectric detection module driving circuit according to claim 1, characterized in that: The synchronous trigger signal generation unit uses a clock distribution chip.

5. The multi-channel synchronously triggered photoelectric detection module driving circuit according to claim 1, characterized in that: The multi-channel trigger signal equalization transmission unit uses an AND gate chip; the AND gate chip has multiple AND gates, and the number of AND gates involved in the calculation is the same as the number of synchronous clock channels. The inputs of each AND gate are the preprocessed reference trigger signal and a single synchronous clock channel, respectively, and the output of each AND gate is a single-channel trigger signal.

6. The multi-channel synchronously triggered photoelectric detection module driving circuit according to claim 1, characterized in that: The preprocessed reference trigger signal maintains the same level as the multi-channel trigger signal.

7. The multi-channel synchronously triggered photoelectric detection module driving circuit according to claim 1, characterized in that: The synchronous trigger signal generation unit divides the reference trigger signal into four synchronous clocks.

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