Sar-assisted two-stage level-crossing adc circuit

Abstract

The utility model provides a two -segment type level cross ADC circuit of SAR auxiliary work can realize higher bandwidth through reducing the precision of LC ADC, and the precision is promoted in combination with the successive approximation method in SAR ADC, can realize 11 bit above effective bit number in 20kHz's bandwidth, can realize two -segment type level cross detection, first level cross detection is namely coarse quantization process, second level detection has met level cross, then start successive approximation fine quantization, compared with traditional architecture, can be according to the amplitude of input signal flexible adjustment second level cross detection's window when second segment level cross detection, thereby realizes arbitrary level cross detection precision, to solve the problem of effective signal loss brought by the window of first level detection is too wide.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit technology, and in particular to a two-stage level-crossing ADC circuit for SAR-assisted operation. Background Technology

[0002] In portable mobile Internet of Things (IoT) systems, signal acquisition and communication typically face challenges such as long-distance transmission, low data rates, and high-density terminal nodes. To meet the stringent requirements of these scenarios, system design must prioritize low-power optimization, and the analog-to-digital converter (ADC), as a core component, directly determines the overall device's battery life and networking capabilities through its energy efficiency. In LCD panel display driving, modern high-resolution displays require highly integrated source driver ICs, where each pixel channel relies on a high-precision ADC to digitize the input signal. The ADC's power consumption directly affects the overall system's energy efficiency. Optimizing the ADC's energy efficiency can effectively reduce screen heat generation and power consumption, extend the mobile device's battery life, reduce signal transmission noise, and improve display quality. On the other hand, in the healthcare field, the combination of IoT and cloud computing has given rise to a new generation of wearable physiological monitoring devices. These devices can continuously collect users' key physiological signals such as electrocardiograms (ECG) and electroencephalograms (EEGs) and transmit them to the cloud in real time via wireless networks for intelligent analysis. This all-weather, long-lasting health monitoring mode urgently requires low-power modules, including the ADC. As can be seen from the above application examples, low-power ADC technology is not only a core support for mobile IoT devices, but also a key driving force for promoting industrial intelligence and medical digitalization.

[0003] As a crucial link in the signal processing chain, the ADC (Analog-to-Digital Converter) undertakes the core function of converting analog signals into digital signals. Traditional ADCs generally employ a uniform sampling mechanism, which suffers from significant energy efficiency deficiencies when processing signals with marked time-domain sparsity (such as communication signals from digital electronic detonators and human physiological electrical signals). Because these signals exhibit rich frequency domain characteristics but bursty time domain characteristics, continuous sampling at a fixed frequency leads to numerous redundant conversions during silent periods, resulting in severe power waste. To address this issue, the event-driven level-crossing ADC (LC ADC) offers an innovative solution. This technology monitors signal level changes in real time and triggers sampling only when the signal amplitude exceeds a preset threshold, effectively avoiding invalid conversions during silent periods. This "on-demand sampling" mode significantly reduces system power consumption, making it particularly suitable for sparse signal processing scenarios. However, the traditional LC ADC architecture faces the "impossible triangle" challenge in engineering implementation—it is difficult to simultaneously achieve the three core performance indicators of high accuracy, high conversion rate, and ultra-low power consumption, often requiring a sacrifice of performance in one aspect during design. This technological bottleneck highlights the limitations of existing LC ADC architectures and points to the development direction of next-generation ADC technology: breaking through the performance boundaries of traditional architectures through innovative circuit design and intelligent sampling strategies, and achieving a systematic improvement in key indicators. Utility Model Content

[0004] The purpose of this invention is to provide a two-stage level-crossing ADC circuit for SAR-assisted operation, which can improve the bandwidth of LC ADC while achieving a certain level of accuracy and meeting the requirements of low power consumption.

[0005] This utility model provides a two-stage level-crossing ADC circuit for SAR-assisted operation, which includes:

[0006] The system clock generation module is used to generate control signal FS, clock signal COMP_CLK, and clock signal LC_CLK based on the external clock CP;

[0007] A capacitor-type DAC array includes capacitors C0 to C7, the upper plates of each of the capacitors C0 to C7 are connected together in sequence, and the control signal FS is used to control the on / off connection between the analog signal VIN and the upper plate of the capacitor C0.

[0008] The comparator has its non-inverting input connected to the upper plate of the capacitor C7, and its control terminal receives the clock signal COMP_CLK.

[0009] The level crossing control logic module generates signals SAR_EN, LC_EN, a level crossing switch control signal, and PW based on the comparator's output signal COUT and the clock signal LC_CLK. The level crossing switch control signal is used to control the level signal V. CM V H V L V LF On / off connection with the inverting input of the comparator;

[0010] The successive approximation control logic module generates the lower seven-bit digital signal D[6:0] based on the signal SAR_EN;

[0011] The counter generates the high three digital signals D[9:7] based on the signal LC_EN, and the low seven digital signals D[6:0] are combined with the high three digital signals D[9:7] to obtain the digital signal D[9:0].

[0012] The switch driving circuit generates a CDAC switch control signal based on the signal PW and the digital signal D[9:7]. The CDAC switch control signal is used to control the lower plate of the capacitor C0 and the level signal V. CM V SS The connection and disconnection between capacitors C1 to C4, and the voltage level signal V. CM V SS V H V L The connection and disconnection between capacitors C5 to C7, and the connection between the lower plates of each capacitor and the voltage level signal V. DD V CM V SS V H V L The connection or disconnection between them.

[0013] Optionally, the level crossing control logic module includes dynamic SAR logic unit SAR Cell1, dynamic SAR logic unit SAR Cell2, dynamic SAR logic unit SAR Cell3, two-input AND gate 2AND1, two-input AND gate 2AND2, three-input AND gate 3AND1, three-input AND gate 3AND2, two-input OR gate OR1, two-input OR gate OR2, two-input OR gate OR3, and a multi-compare level switch control logic module;

[0014] The clock signal LC_CLK is input to the D terminal of the dynamic SAR logic unit SAR Cell1. The output terminal Q of the dynamic SAR logic unit SAR Cell1 is connected to the D terminal of the dynamic SAR logic unit SAR Cell2. The output terminal Q of the dynamic SAR logic unit SAR Cell2 is connected to the D terminal of the dynamic SAR logic unit SAR Cell3.

[0015] The comparator's output signal COUT includes output signal On, output signal Op, and output signal Valid. The N terminal of each of the dynamic SAR logic units SAR Cell1, SAR Cell2, and SAR Cell3 is connected to output signal On, the P terminal of each of the dynamic SAR logic units SAR Cell1, SAR Cell2, and SAR Cell3 is connected to output signal Op, and the CLK terminal of each of the dynamic SAR logic units SAR Cell1, SAR Cell2, and SAR Cell3 is connected to output signal Valid.

[0016] The dynamic SAR logic unit SAR Cell1 outputs signals P1 and N1, the dynamic SAR logic unit SAR Cell2 outputs signals P2 and N2, and the dynamic SAR logic unit SAR Cell3 outputs signals P3 and N3. Signals P1 and P2 are connected to a two-input AND gate 2AND1 to generate signal INC. Signals N1 and N2 are connected to a two-input AND gate 2AND2 to generate signal DEC. Signals INC and DEC are connected to a two-input OR gate OR1 to generate signal LC_EN. Signals P1, N2, and P3 are connected to a three-input AND gate 3AND1 to generate signal A. Signals N1, P2, and N3 are connected to a three-input AND gate 3AND2 to generate signal B. Signals A and B are connected to a two-input OR gate OR2 to generate signal C. Signal C and signal LC_EN are connected to a two-input OR gate OR3 to obtain signal SAR_EN. Signals N1, P1, N2, P3, N3, and P3 are also connected to the multi-comparison level switch control logic module to generate the level crossover switch control signal.

[0017] Optionally, the two-stage level-crossing ADC circuit also includes a switch SW. 34 ~SW 38 The inverting input of the comparator is connected to the switch SW. 34 ~SW 38 Corresponding to the access level signal V CM V H V L V LF and V HF The level cross switch control signal is used to control switch SW 34 ~SW 38 The on / off state.

[0018] Optionally, the capacitor DAC array further includes a bootstrap switch SW0, one end of which is connected to an analog signal VIN, and the other end of which is connected to the upper plate of the capacitor C0. The control signal FS is used to control the on / off state of the bootstrap switch SW0.

[0019] Optionally, the capacitor DAC array includes switches SW1 to SW2. 33 The lower plate of capacitor C0 is connected to the level signal V via switches SW1 and SW2 respectively. CM and V SS The lower plate of capacitor C1 is connected to the level signal V via switches SW3 to SW6 respectively. CM V SS V H and V L The lower plate of capacitor C2 is controlled by switches SW7 to SW8. 10 Corresponding to the access level signal V CM V SS V H and V L The lower plate of capacitor C3 is connected to switch SW. 11 ~SW 14 Corresponding to the access level signal V CM V SS V H and V L The lower plate of capacitor C4 is connected to switch SW. 15 ~SW 18 Corresponding to the access level signal V CM V SS V H and V L The lower plate of capacitor C5 is connected to switch SW. 19 ~SW 23 Corresponding to the access level signal V DD V CM V SS V H and V L The lower plate of the capacitor C6 is connected to the switch SW. 24 ~SW 28 Corresponding to the access level signal V DD V CM V SS V H and V L The lower plate of capacitor C7 is connected to switch SW. 19 ~SW 23 Corresponding to the access level signal V DD V CM VSS V H and V L The CDAC switch control signal is used to control switches SW1 to SW2. 33 The on / off state.

[0020] Compared with the prior art, the present invention has at least the following characteristics:

[0021] 1. A novel hybrid architecture combining successive approximation and level crossing was designed. By reducing the precision of the LC ADC, higher bandwidth is achieved. Combined with the successive approximation method in the SAR ADC, the precision is improved, enabling more than 11 effective bits to be achieved within a 20kHz bandwidth.

[0022] 2. A combined coarse and fine quantization LC ADC structure was constructed. Coarse quantization was performed using a 3-bit LC ADC to obtain the high 3 bits of the digital signal. Then, a 7-bit SAR logic module performed 7-bit fine quantization on the capacitor array of the original LC ADC to obtain the low 7 bits of the digital signal. Traditional LC ADCs only generate pulse signals; to obtain a digital output, these pulse signals need to be regenerated. However, the coarse and fine quantization combined architecture constructed in this invention only needs to combine the obtained high 3 bits and low 7 bits of the digital signal to obtain a 10-bit digital output, reducing the steps of subsequent digital signal processing.

[0023] 3. It enables two-stage level crossover detection. The first stage of level crossover detection is the coarse quantization process, but due to the reduced accuracy of the LCADC, the detection window for the first stage is too wide. Therefore, a second stage of level crossover detection is added. If level crossover is detected in the second stage, successive approximation fine quantization is initiated. Compared with the traditional architecture, the window for the second stage of level crossover detection can be flexibly adjusted according to the amplitude of the input signal, thereby achieving arbitrary level crossover detection accuracy and solving the problem of effective signal loss caused by the excessively wide window of the first stage of level detection.

[0024] 4. Traditional methods that combine level crossing and successive approximation usually require two or more large capacitor arrays to achieve this. The architecture designed in this invention only needs a 7-bit binary weighted capacitor array to complete the detection of two levels crossing and 7-bit successive approximation fine quantization. Compared with the traditional architecture, the total capacitor size is reduced, which can achieve lower power consumption and area. Attached Figure Description

[0025] Those skilled in the art will understand that the accompanying drawings are provided to better understand the present invention and do not constitute any limitation on the scope of the present invention. Wherein:

[0026] Figure 1A schematic diagram of a two-stage level-crossing ADC circuit for SAR-assisted operation according to an embodiment of this utility model;

[0027] Figure 2 This is a schematic diagram of a level crossing control logic module according to an embodiment of the present invention;

[0028] Figure 3 This is a flowchart illustrating the two-stage level cross-detection process of an embodiment of the present invention.

[0029] Figure 4 The waveform diagram of the seven-bit successive approximation auxiliary operation of the successive approximation control logic module in an embodiment of the present invention is shown.

[0030] Figure 5 The timing diagram of each signal when the two-stage level-crossing ADC circuit for SAR assistance is working according to an embodiment of the present invention;

[0031] Figure 6 This is a simulation result diagram of a 16.601kHz sine wave input to an ADC circuit according to an embodiment of the present invention;

[0032] Figure 7 This is a frequency domain diagram of the output signal of the ADC circuit when a 16.601kHz sine wave is input to the ADC circuit according to an embodiment of the present invention.

[0033] Figure 8 This is a simulation result diagram of an embodiment of the present invention, in which a low-frequency ECG signal is used as an analog signal input to an ADC circuit.

[0034] Figure 9 This is a power consumption distribution diagram of each module when a sine wave signal and an ECG signal are used as analog signal inputs, according to an embodiment of the present invention. Detailed Implementation

[0035] To make the objectives, advantages, and features of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the objectives of the embodiments of this utility model. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may emphasize different aspects and sometimes use different scales.

[0036] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to include the meaning of “and / or”; the term “a number” is generally used to include the meaning of “at least one”; and the term “at least two” is generally used to include the meaning of “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature. “One end” and “the other end,” as well as “proximal end” and “far end,” generally refer to two corresponding parts, including not only endpoints. The terms “installed,” “connected,” and “joined” should be interpreted broadly; for example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two elements or the interaction between two elements. Furthermore, as used in this invention, the phrase "one element is disposed on another element" generally only indicates that there is a connection, coupling, cooperation, or transmission relationship between the two elements. This connection, coupling, cooperation, or transmission can be direct or indirect through an intermediate element, and should not be construed as indicating or implying a spatial positional relationship between the two elements. That is, one element can be located arbitrarily inside, outside, above, below, or to one side of the other element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0037] like Figure 1 As shown, this utility model provides a two-stage level-crossed ADC circuit with SAR-assisted operation, specifically a two-stage level-crossed ADC circuit with seven-bit successive approximation assistance. It consists of a system clock generation module (SysCLK), a capacitor DAC array (7-bit capacitor DAC array), switches SW34-SW38, a comparator (COMP), a level-crossing control logic module (LC LOGIC), a successive approximation control logic module (7-bit SAR LOGIC), a counter (3-bit CNT), and a switch driver circuit (CDAC_Driver). Here, the successive approximation control logic module specifically refers to a 7-bit successive approximation control logic module, and the counter specifically refers to a 3-bit counter.

[0038] The system clock generation module generates control signal FS, clock signal COMP_CLK, and clock signal LC_CLK based on an external clock CP. The capacitor DAC array includes capacitors C0 to C7, with their upper plates connected sequentially. The control signal FS controls the connection between the analog signal VIN and the upper plate of capacitor C0. Note that the analog signal VIN is input to the upper plate of the capacitor DAC array, and the output signal of the upper plate is Fixed OUT. The non-inverting input of the comparator is connected to the upper plate of capacitor C7. The comparator's control terminal receives the clock signal COMP_CLK. It is understood that receiving the clock signal COMP_CLK initiates logic comparison. The level crossing control logic module generates signal SAR_EN, signal LC_EN, a level crossing switch control signal, and signal PW based on the comparator's output signal COUT and the clock signal LC_CLK. The level crossing switch control signal controls the level signal V. CM V H V L V LF The switching between the inverting input of the comparator and the current input is controlled; the successive approximation control logic module generates the lower seven-bit digital signal D[6:0] based on the signal SAR_EN; the counter generates the higher three-bit digital signal D[9:7] based on the signal LC_EN, and the lower seven-bit digital signal D[6:0] and the higher three-bit digital signal D[9:7] are combined to obtain the digital signal D[9:0]; the switch drive circuit generates a CDAC switch control signal based on the signal PW and the digital signal D[9:7], and the CDAC switch control signal is used to control the lower plate of the capacitor C0 and the level signal V. CM V SS The connection and disconnection between capacitors C1 to C4, and the voltage level signal V. CM V SS V H V L The connection and disconnection between capacitors C5 to C7, and the connection between the lower plates of each capacitor and the voltage level signal V. DD V CM V SS V H V L The connection or disconnection between them.

[0039] The inverting input of the comparator is connected to the switch SW. 34 ~SW 38 Corresponding to the access level signal V CM V H V L V LF and V HFThe level cross switch control signal is used to control switch SW 34 ~SW 38 The on / off state of the comparator. Specifically, the inverting input of the comparator is controlled by switch SW. 34 Access level signal V CM The inverting input of the comparator is connected to switch SW. 35 Access level signal V H The inverting input of the comparator is connected to switch SW. 36 Access level signal V L The inverting input of the comparator is connected to switch SW. 37 Access level signal V LF The inverting input of the comparator is connected to switch SW. 38 Access level signal V HF .

[0040] The capacitor-type DAC array further includes a bootstrap switch SW0 and switches SW1 to SW1. 33 One end of the bootstrap switch SW0 is connected to the analog signal VIN, and the other end of the bootstrap switch SW0 is connected to the upper plate of the capacitor C0. The control signal FS is used to control the on / off state of the bootstrap switch SW0. The capacitor-type DAC array includes switches SW1 to SW2. 33 The lower plate of capacitor C0 is connected to the level signal V via switches SW1 and SW2 respectively. CM and V SS The lower plate of capacitor C1 is connected to the level signal V via switches SW3 to SW6 respectively. CM V SS V H and V L The lower plate of capacitor C2 is controlled by switches SW7 to SW8. 10 Corresponding to the access level signal V CM V SS V H and V L The lower plate of capacitor C3 is connected to switch SW. 11 ~SW 14 Corresponding to the access level signal V CM V SS V H and V L The lower plate of capacitor C4 is connected to switch SW. 15 ~SW 18 Corresponding to the access level signal V CM V SS V H and V L The lower plate of capacitor C5 is connected to switch SW. 19 ~SW23 Corresponding to the access level signal V DD V CM V SS V H and V L The lower plate of the capacitor C6 is connected to the switch SW. 24 ~SW 28 Corresponding to the access level signal V DD V CM V SS V H and V L The lower plate of capacitor C7 is connected to switch SW. 19 ~SW 23 Corresponding to the access level signal V DD V CM V SS V H and V L The CDAC switch control signal is used to control switches SW1 to SW2. 33 The on / off state.

[0041] Specifically, the lower plate of capacitor C0 is connected to the level signal V via switch SW1. CM And the level signal V is connected via switch SW2. SS The lower plate of capacitor C1 is connected to a voltage level signal V via switch SW3. CM The voltage level signal V is connected via switch SW4. SS The voltage level signal V is connected via switch SW5. H And the level signal V is connected via switch SW6. L The lower plate of capacitor C2 is connected to a voltage level signal V via switch SW7. CM The voltage level signal V is connected via switch SW8. SS The voltage level signal V is connected via switch SW9. H And via switch SW 10 Access level signal V L The lower plate of capacitor C3 is connected to switch SW. 11 Access level signal V CM , via switch SW 12 Access level signal V SS , via switch SW 13 Access level signal V H And via switch SW 14 Access level signal V L The lower plate of capacitor C4 is connected to switch SW. 15 Access level signal V CM , via switch SW 16 Access level signal VSS , via switch SW 17 Access level signal V H And via switch SW 18 Access level signal V L The lower plate of capacitor C5 is connected to switch SW. 19 Access level signal V DD , via switch SW 20 Access level signal V CM , via switch SW 21 Access level signal V SS , via switch SW 22 Access level signal V H And via switch SW 23 Access level signal V L The lower plate of the capacitor C6 is connected to the switch SW. 24 Input level signal VDD, through switch SW 25 Access level signal V CM , via switch SW 26 Access level signal V SS , via switch SW 27 Access level signal V H And via switch SW 28 Access level signal V L The lower plate of capacitor C7 is connected to switch SW. 29 Access level signal V DD , via switch SW 30 Access level signal V CM , via switch SW 31 Access level signal V SS , via switch SW 32 Access level signal V H And via switch SW 33 Access level signal V L .

[0042] See Figure 2The level crossing control logic module includes dynamic SAR logic units SAR Cell1, SAR Cell2, and SAR Cell3, two-input AND gates 2AND1, 2AND gates 2AND2, three-input AND gates 3AND1 and 3AND2, two-input OR gates OR1, OR2, and OR3, as well as a multi-comparison level switch control logic module. The clock signal LC_CLK is input to the D terminal of dynamic SAR logic unit SAR Cell1. The output Q terminal of dynamic SAR logic unit SAR Cell1 is connected to the D terminal of dynamic SAR logic unit SAR Cell2, and the output Q terminal of dynamic SAR logic unit SAR Cell2 is connected to the D terminal of dynamic SAR logic unit SAR Cell3. The comparator's output signal COUT includes output signal On, output signal Op, and output signal Valid. The N terminal of each of dynamic SAR logic units SAR Cell1, SAR Cell2, and SAR Cell3 is connected to output signal On, and the P terminal of each of dynamic SAR logic units SAR Cell1, SAR Cell2, and SAR Cell3 is connected to output signal Op. Cell1, SAR Cell2, and SAR Cell3 each have their CLK terminals connected to the output signal Valid. SAR Cell1 outputs signals P1 and N1, SAR Cell2 outputs signals P2 and N2, and SAR Cell3 outputs signals P3 and N3. Signals P1 and P2 are connected to a two-input AND gate 2AND1 to generate signal INC. Signals N1 and N2 are connected to a two-input AND gate 2AND2 to generate signal DEC. Signals INC and DEC are connected to a two-input OR gate OR1 to generate signal LC_EN. Signals P1, N2, and P3 are connected to a three-input AND gate 3AND1 to generate signal A. Signals N1, P2, and N3 are connected to a three-input AND gate 3AND2 to generate signal B. Signals A and B are connected to a two-input OR gate OR2 to generate signal C. Signal C and signal LC_EN are connected to a two-input OR gate OR3 to obtain signal SAR_EN. Signals N1, P1, N2, P3, N3, and P3 are also connected to the multi-comparison level switch control logic module to generate the level crossover switch control signal.

[0043] The working principle of the two-stage level-crossing ADC circuit for SAR-assisted operation of this utility model is as follows:

[0044] First, during the sampling phase, the external analog signal VIN is input to the upper plate of the 7-bit capacitor DAC array via the bootstrap switch SW0, and its sampling control signal FS is generated by the system clock generation module (SysCLK). The upper plate of the 7-bit capacitor DAC array outputs the signal Fixed OUT. During the sampling phase, some switches on the lower plate of the 7-bit capacitor DAC array will be selected and connected to VIN based on the result of the previous conversion. DD or V SS After the sampling process is complete, all switches will be connected to V. CM At this point, the Fixed OUT signal from the upper plate of the 7-bit capacitor DAC array is fed into the non-inverting input of the comparator. Subsequently, the first level crossover detection result will be obtained through two comparison cycles.

[0045] If a level crossover is detected during the first level crossover detection, the 3-bit counter (3-bit CNT) will perform ±1 operations to obtain the high 3 bits of the digital signal. Simultaneously, the 7-bit successive approximation control logic module (7-bit SAR LOGIC) will be activated to perform a successive approximation process for 7 cycles to obtain the low 7 bits of the digital signal. The two are combined to obtain a 10-bit digital signal output. Thus, the 3-bit LC ADC obtains the coarse quantization result, and the 7-bit SAR logic module obtains the fine quantization result, completing one quantization process.

[0046] If no level crossing is detected during the first level crossing detection (window voltage is V) H V L If the second level cross-detection is performed (window voltage is V), then the second level cross-detection will continue. HF V LF If a level crossing is detected a second time, the 7-bit successive approximation control logic module (7-bit SAR LOGIC) is activated to perform a 7-cycle successive approximation process to obtain the lower seven bits of the digital signal. Under this condition, the output of the 3-bit counter (3-bit CNT) remains unchanged. Thus, only the fine quantization result is obtained, while the coarse quantization result remains unchanged.

[0047] If the second level cross-detection still fails to detect a result, it means that the change in signal amplitude is less than two window voltages, indicating inactivity. The system will then directly enter sleep mode to save power.

[0048] To reduce power consumption and area, the coarse and fine quantization processes, as well as the two-segment level crossover detection processes, are all performed on a 7-bit capacitor DAC array. Therefore, during the sampling and conversion stages, the voltage connected to the lower plates of all capacitors in the 7-bit capacitor DAC array is not the same. Specifically, during the sampling stage, the lower plates of the lower segments C0 to C4 are connected to V via a switch. SSThe higher-level C5-C7 segments need to be connected to V based on the output of the current 3-bit counter (3-bit CNT). DD or V SS At this point, the upper plate output signal of the 7-bit capacitor DAC array is Fixed OUT = VIN. At the end of the sampling phase and the beginning of the conversion phase, the system clock generation module (SysCLK) outputs signal FS = 0 to disable the bootstrap switch SW0. The lower plates of the low-segment C0 to C4 will then be connected to VIN via a switch. CM High-level C5-C7 will also receive V. CM At this point, the output Fixed OUT of the upper plate of the 7-bit capacitor DAC array can be approximated as:

[0049] Fixed OUT = VIN(t) - VIN(t-1) + V CM

[0050] T represents time. Based on the above formula, the change in the external input signal VIN between the two time points is obtained. Then, Fixed OUT is connected to the non-inverting input of the comparator, and the inverting input of the comparator is connected to VIN at the beginning of the conversion phase. CM Perform the first comparison. This operation determines the direction of change in the amplitude of the current input signal. If the signal amplitude increases, Fixed OUT will be greater than V. CM Conversely, it is less than V. CM After determining the direction of the signal change, the inverting input of the comparator in the next cycle will select the input to V based on the result of the previous comparison. H or V L That is, when the signal amplitude increases, it is connected to V. H Conversely, it will receive V. L Note that the window voltage at this time is V. H and V L This is the first level crossover detection. Upon detection, the comparator output signal COUT is sent to the level crossover control logic module (LC LOGIC). LC LOGIC will set LC_EN = 1, at which point a 3-bit counter will be started performing ±1 operations. Simultaneously, SAR_EN will also be set to 1 to initiate successive approximation. At the start of successive approximation, the lower plate of C0 in the 7-bit capacitor DAC array remains connected to V. CM C1 to C7 are connected to V based on the results of successive approximations. H or V L This makes the 7-bit successive approximation reference level VREF / 8. This is because the minimum unit voltage of a 3-bit LC ADC is LSB (LSB = VREF / 2). 3When the reference level for successive approximations is LSB, the weights in the final ADC output digital code can be distributed in a binary manner. That is, the least significant bit weight of the LC ADC is exactly twice the most significant bit weight of the 7-bit SAR LOGIC. The resulting high 3 bits can then be directly merged with the low 7 bits, eliminating the need for additional code transformation steps and further reducing system complexity and power consumption. After seven successive approximations, a coarse 3-bit digital signal and a fine 7-bit digital signal are obtained, which are then used as the ADC output, completing one quantization process.

[0051] The above describes the quantization process where a level crossover is detected during the first level crossover detection. If the first level crossover detection fails to detect a level crossover, a second level crossover detection will be initiated. Since the LC ADC has a precision of 3 bits, V... H and V L The voltage is V CM ±VREF / 8. Because this is a large window voltage, it may cause some valid signals with insignificant amplitude changes to be missed.

[0052] Therefore, a two-stage level crossover detection method is proposed, that is, during the first level crossover detection, a level crossover (greater than V) is detected. H or V L The inverting input of the comparator (COMP) will be connected to V. HF or V LF These two voltages form a smaller window for a second level crossover detection. (With V) H and V L The LSB (V) must be designed as an LC ADC CM ±VREF / 2 N ) different, V HF and V LF In V H and V L The internal settings are arbitrary. The gain of the low-noise amplifier in the analog front-end is often susceptible to changes due to temperature fluctuations or power supply voltage fluctuations; therefore, V can be adjusted according to the actual situation. HF and V LF The value is used to dynamically adjust the window size of the second-level level crossover detection, thereby achieving more accurate event-driven operation. After the second level detects a level crossover, coarse quantization is not performed; only the SAR logic module is activated for fine quantization. After obtaining the lower 7 bits of the digital signal, it is combined with the current higher 3 bits of the digital signal to obtain the system's 10-bit output.

[0053] See Figure 2Continuing the explanation, signals On, Op, and Valid are all outputs of comparator COMP, specifically COUT. During the sampling phase, LC_CLK = 0, clearing N1, P1, N2, P2, N3, and P3 to zero. When LC_CLK = 1, the conversion phase begins, activating the first SAR logic unit, SAR Cell1. At this point, Fixed OUT first compares with V... CM The comparison will be performed, and the result will be stored in N1 and P1. When Fixed OUT is greater than V... CM At that time, P1 = 1, N1 = 0. Then, in the second comparator cycle, Fixed OUT and V... H When compared, when greater than V H When we get P2 = 1 and N2 = 0, such as Figure 2 This results in signal INC = 1. Simultaneously, passing through two-input OR gates OR1 and OR3 will also cause LC_EN = 1 and SAR_EN = 1. These two signals will cause the 3-bit counter (3-bit CNT) to increment by 1 and activate the 7-bit successive approximation logic module (7-bit SAR LOGIC) for fine quantization. When Fixed OUT and V are in the second comparator cycle... H Compared to V H At this point, the results P2 = 0 and N2 = 1, indicating that INC and DEC will both be 0. Subsequently, in the third comparator cycle, Fixed OUT and V... HF Compare, if greater than V HF Then the result is P3 = 1, N3 = 0. For example... Figure 2 At this point, the three-input AND gate 3AND1 will produce signal A as 1, which will make SAR_EN 1, thus activating the 7-bit successive approximation logic module (7-bit SAR LOGIC) to obtain the fine quantization result. If the result of the second level cross-detection is less than V... HF This will result in P3 = 0 and N3 = 1. From Figure 2 As can be seen, LC_EN and SAR_EN will both be 0, and the system will enter a sleep state until the next working cycle arrives.

[0054] To more intuitively demonstrate the system's operation and the two-stage level cross-detection, please refer to... Figure 3 and Figure 4 ,like Figure 3 As shown, during the sampling phase, the system clock generation module outputs a signal LC_CLK = 0 (sampling phase), and LC_CLK = 1 indicates entry into the conversion phase. The output Fixed OUT of the upper plate of the 7-bit capacitor DAC array is compared with V by a comparator. CM Compare the values ​​and move to the left or right side based on the comparison result. (If the value is greater than V) CM For example, if the judgment result is YES, then it is compared with V. HThe comparison is performed; this is the first level crossover detection process. If it is YES, the level crossover control logic module (LC LOGIC) outputs signals LC_EN = 1 and SAR_EN = 1. The high 3 bits of the digital signal D[9:7] are also obtained. Then, a 7-bit successive approximation process is initiated, such as... Figure 4 The diagram in section a shows the process. The lower 7 bits of the digital signal D[6:0] are obtained, and the sampling process ends before entering the next cycle. If the result is NO during the first-level level cross-detection, then Fixed OUT continues with V. HF The comparison is performed; this is the second level of level cross-detection. If the result is YES, then SAR_EN is 1, and the 7-bit successive approximation process begins, as follows: Figure 4 The diagram in section c shows the process. The lower 7 bits of the digital signal are obtained, and then the next sampling cycle begins. Figure 4 Parts b and d in the diagram illustrate the successive approximation process as the level changes downwards. If the result of the second-level level cross-detection is still NO, the sampling process directly proceeds to the next cycle.

[0055] See Figure 2 LC_EN = 1 indicates that a level crossing is detected during LC ADC operation, and an increment or decrement signal is sent to the 3-bit counter (3-bit CNT); SAR_EN = 1 indicates that a start signal is sent to the 7-bit successive approximation logic module (7-bit SAR LOGIC) when 7-bit successive approximation is required. At the beginning of the first working cycle, the sampling signal FS is first set to 1, and after sampling for one CP cycle, it is set to zero to indicate that one sampling is completed. Then the comparator clock COMP_CLK arrives, and the inverting input of the comparator is first connected to V. CM At this point, the upper plate output Fixed OUT of the 7-bit capacitor DAC array will first be V. CM Compare, if greater than V CM , will be with V H Comparison, that is, the inverting input of the comparator is connected to V. H The comparison result is greater than V. H At this time, LC_EN is set to 1, controlling the 3-bit CNT to increment by 1. For example... Figure 5 This indicates that the high 3 bits of D[9:7] have undergone an increment operation, and SAR_EN is also set to 1, which will begin 7 successive approximations when the next comparator cycle arrives. Before the end of the first working cycle, the low 7 bits of D[6:0] have updated the data, which is the result of 7 successive approximations by the 7-bit SAR LOGIC. In the second working cycle, COMP_CLK arrives after sampling is completed, and according to the results, Fixed OUT is greater than V at this time. CM But less than V HTherefore, the high 3 bits of the counter output will remain unchanged. According to the two-stage level cross-detection proposed in this invention, it will then be compared with a more precise level V. HF Comparison, that is, the inverting input of the comparator is connected to V. HF The result indicates that the value is greater than V in the third comparison period. HF Therefore, SAR_EN is set to 1 to start the 7-bit SAR LOGIC operation. At the end of the second working cycle, D[6:0] is updated with the results of 7 successive approximations. In the third working cycle, it can be seen that with the arrival of COMP_CLK, the voltage on the upper plate of CDAC is greater than V. CM But less than V H It is also less than V HF Therefore, neither the 3-bit counter nor the 7-bit successive approximation logic module will be activated; D[9:7] and D[6:0] will remain unchanged until the next working cycle. If Fixed OUT is less than V... CM Then, the voltage compared with the subsequent voltage will become V. L and V LF The working principle is greater than V CM The time is the same.

[0056] Figure 6 The transient simulation results are shown for an input VIN of 16.601kHz sine wave, where VIN is the input signal, VOUT is the analog signal obtained after the 10-bit digital signal output is restored by a 10-bit ideal DAC, and LC_EN indicates that the counter performs ±1 operation. Since the bandwidth designed in this invention is 20kHz, 16.601kHz is already a relatively high input signal frequency. Figure 6 As can be seen from the graph, LC_EN = 1 indicates that a coarse quantization result has been obtained. In the graph, pulses are present at all times except for the peaks and troughs of the VIN sine wave. This means that the first level crossover detection yielded a result. The coarse quantization result is obtained from the 3-bit counter, and then the fine quantization result is obtained from the 7-bit successive approximation logic module. A closer look reveals… Figure 6 The VOUT signal reveals cutoff and saturation at certain peaks and troughs, resulting in no data. This is because the amplitude change of VIN is extremely small during these moments, less than the window of the second-level level cross-detection. Therefore, the system enters a sleep state and remains inactive to reduce power consumption. To obtain the spectral characteristics of VOUT, interpolation reconstruction of VOUT is required. After reconstructing VOUT using mathematical tools and performing FFT analysis, the resulting spectrum is as follows... Figure 7 As shown in the figure, the effective bit depth is 11.34 bits, the spurious-free dynamic range is 76.37 dB, the signal-to-noise ratio is 70.04 dB, and the power consumption is only 4.74 μW.

[0057] To further demonstrate the excellent energy efficiency of this invention in the field of low-frequency biomedical signal measurement, an electrocardiogram (ECG) signal is used as an example. Figure 8 The transient response output of the system is given when the ECG signal is used as the input signal. For example... Figure 8 VIN is the ECG input signal, VOUT is the analog signal obtained after the 10-bit digital signal is restored by a 10-bit ideal DAC, and LC_EN indicates that the counter performs ±1 operation. In the time interval of 120ms to 380ms, the number of signal sampling points is relatively small; in the time interval of 400ms to 460ms, the number of sampling points increases, resulting in good overall fidelity. In the entire signal, the LC_EN signal at the bottom represents the signal relative to V... H and V L At the level crossing point, it can be seen that the 3-bit counter changes only at a few points in time. This means that most of the time, the high 3 bits of the output 10-bit digital signal remain unchanged, which reduces power consumption. Under this ECG signal input, the measured ADC power consumption is only 0.78uW. Simulation results show that, compared with traditional ADCs using uniform sampling, the designed two-stage level-crossed ADC with seven-bit successive approximation assistance has higher energy efficiency when dealing with signals with high time-domain discreteness. Figure 9 Fin represents the energy consumption percentage of each module in the system when a 16.601kHz sine wave and an ECG signal are used as inputs, respectively. Fin is also known as the analog signal VIN. Figure 9 The left side of the diagram shows the power consumption percentage of each module when a sine wave is input. At this time, the power consumption is mainly dynamic. The capacitor DAC array consumes the vast majority of the power, reaching 60.26%. The comparator accounts for 22.74% of the power consumption, and the remaining digital circuitry consumes a total of 17% of the power consumption. Figure 9 The right-hand side of the graph shows the power consumption percentage under the ECG input signal. It can be seen that the sampling rate is reduced and the dynamic power consumption is decreased. Although the capacitor DAC and comparator still account for most of the power consumption, it is reduced compared to the left graph. It can be seen that by controlling the system operation and sampling through event-driven control, the overall energy efficiency has been improved.

[0058] This invention is applicable to the conversion of low-frequency signals such as electrocardiogram signals. The lower the frequency of the signal, the lower the power consumption of the system. Conversion can only be triggered when the signal change amplitude exceeds a certain range. At the same time, continuous detection can be performed when the signal amplitude changes rapidly. It is very suitable for the conversion of analog signals that are sparse in the time domain.

[0059] This invention, based on a traditional LC ADC, combines the successive approximation technique from SAR ADCs, integrating the advantages of both structures to achieve good accuracy and bandwidth with lower power consumption. Since traditional LC ADCs face significant challenges in balancing accuracy, power consumption, and bandwidth, the reason this invention's LC ADC doesn't require high precision to achieve a 20kHz bandwidth is due to its structure of level-crossing coarse quantization followed by successive approximation fine quantization. Specifically, coarse quantization is performed by a 3-bit LC ADC, followed by fine quantization by a 7-bit successive approximation logic module, achieving an accuracy of over 10 bits.

[0060] Meanwhile, noting that reducing the accuracy of the LC ADC might result in an excessively wide level crossing window, missing some useful signals, this invention proposes a two-stage level crossing detection structure. If a level crossing is not detected in the first level crossing detection, a second level crossing detection is performed with a smaller window voltage. In this case, only a 7-bit successive approximation logic module is activated for fine quantization. Furthermore, the window voltage for the second level crossing detection can be arbitrarily set according to the input signal. Compared to traditional LC ADCs, this invention achieves more flexible level crossing detection. All of the above functions are implemented on a 7-bit capacitive DAC array by switching the lower plate switch. Compared to the traditional method combining LC ADC and SAR ADC, this invention requires a smaller total capacitance, thus achieving lower area and power consumption.

[0061] Although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A two-stage level-crossing ADC circuit for SAR-assisted operation, characterized in that, include: The system clock generation module is used to generate control signal FS, clock signal COMP_CLK, and clock signal LC_CLK based on the external clock CP; A capacitor-type DAC array includes capacitors C0 to C7, the upper plates of each of the capacitors C0 to C7 are connected together in sequence, and the control signal FS is used to control the on / off connection between the analog signal VIN and the upper plate of the capacitor C0. The comparator has its non-inverting input connected to the upper plate of the capacitor C7, and its control terminal receives the clock signal COMP_CLK. The level crossing control logic module generates signals SAR_EN, LC_EN, a level crossing switch control signal, and PW based on the comparator's output signal COUT and the clock signal LC_CLK. The level crossing switch control signal is used to control the level signal V. CM V H V L V LF On / off connection with the inverting input of the comparator; The successive approximation control logic module generates the lower seven-bit digital signal D[6:0] based on the signal SAR_EN; The counter generates the high three digital signals D[9:7] based on the signal LC_EN, and the low seven digital signals D[6:0] are combined with the high three digital signals D[9:7] to obtain the digital signal D[9:0]. The switch driving circuit generates a CDAC switch control signal based on the signal PW and the digital signal D[9:7]. The CDAC switch control signal is used to control the lower plate of the capacitor C0 and the level signal V. CM V SS The connection and disconnection between capacitors C1 to C4, and the voltage level signal V. CM V SS V H V L The connection and disconnection between capacitors C5 to C7, and the lower plate of each capacitor C5 to C7 and the voltage level signal V. DD V CM V SS V H V L The connection or disconnection between them.

2. The two-stage level-crossing ADC circuit for SAR-assisted operation according to claim 1, characterized in that, The level crossover control logic module includes dynamic SAR logic unit SAR Cell1, dynamic SAR logic unit SAR Cell2, dynamic SAR logic unit SAR Cell3, two-input AND gate 2AND1, two-input AND gate 2AND2, three-input AND gate 3AND1, three-input AND gate 3AND2, two-input OR gate OR1, two-input OR gate OR2, two-input OR gate OR3, and a multi-compare level switch control logic module. The clock signal LC_CLK is input to the D terminal of the dynamic SAR logic unit SAR Cell1. The output terminal Q of the dynamic SAR logic unit SAR Cell1 is connected to the D terminal of the dynamic SAR logic unit SAR Cell2. The output terminal Q of the dynamic SAR logic unit SAR Cell2 is connected to the D terminal of the dynamic SAR logic unit SAR Cell3. The comparator's output signal COUT includes output signal On, output signal Op, and output signal Valid. The N terminal of each of the dynamic SAR logic units SAR Cell1, SAR Cell2, and SAR Cell3 is connected to output signal On, the P terminal of each of the dynamic SAR logic units SAR Cell1, SAR Cell2, and SAR Cell3 is connected to output signal Op, and the CLK terminal of each of the dynamic SAR logic units SAR Cell1, SAR Cell2, and SAR Cell3 is connected to output signal Valid. The dynamic SAR logic unit SAR Cell1 outputs signals P1 and N1, the dynamic SAR logic unit SAR Cell2 outputs signals P2 and N2, and the dynamic SAR logic unit SAR Cell3 outputs signals P3 and N3. Signals P1 and P2 are connected to a two-input AND gate 2AND1 to generate signal INC. Signals N1 and N2 are connected to a two-input AND gate 2AND2 to generate signal DEC. Signals INC and DEC are connected to a two-input OR gate OR1 to generate signal LC_EN. Signals P1, N2, and P3 are connected to a three-input AND gate 3AND1 to generate signal A. Signals N1, P2, and N3 are connected to a three-input AND gate 3AND2 to generate signal B. Signals A and B are connected to a two-input OR gate OR2 to generate signal C. Signal C and signal LC_EN are connected to a two-input OR gate OR3 to obtain signal SAR_EN. Signals N1, P1, N2, P3, N3, and P3 are also connected to the multi-comparison level switch control logic module to generate the level crossover switch control signal.

3. The SAR-assisted two-stage flash ADC circuit of claim 1, wherein, The two-stage level-crossing ADC circuit also includes a switch SW. 34 ~SW 38 The inverting input of the comparator is connected to the switch SW. 34 ~SW 38 Corresponding to the access level signal V CM V H V L V LF and V HF The level cross switch control signal is used to control switch SW 34 ~SW 38 The on / off state.

4. The two-stage level-crossing ADC circuit for SAR-assisted operation according to claim 1, characterized in that, The capacitor DAC array also includes a bootstrap switch SW0, one end of which is connected to an analog signal VIN, and the other end of which is connected to the upper plate of the capacitor C0. The control signal FS is used to control the on / off state of the bootstrap switch SW0.

5. The two-stage level-crossing ADC circuit for SAR-assisted operation according to claim 1, characterized in that, The capacitor DAC array includes switches SW1 to SW2. 33 The lower plate of capacitor C0 is connected to the level signal V via switches SW1 and SW2 respectively. CM and V SS The lower plate of capacitor C1 is connected to the level signal V via switches SW3 to SW6 respectively. CM V SS V H and V L The lower plate of capacitor C2 is controlled by switches SW7 to SW8. 10 Corresponding to the access level signal V CM V SS V H and V L The lower plate of capacitor C3 is connected to switch SW. 11 ~SW 14 Corresponding to the access level signal V CM V SS V H and V L The lower plate of capacitor C4 is connected to switch SW. 15 ~SW 18 Corresponding to the access level signal V CM V SS V H and V L The lower plate of capacitor C5 is connected to switch SW. 19 ~SW 23 Corresponding to the access level signal V DD V CM V SS V H and V L The lower plate of the capacitor C6 is connected to the switch SW. 24 ~SW 28 Corresponding to the access level signal V DD V CM V SS V H and V L The lower plate of capacitor C7 is connected to switch SW. 19 ~SW 23 Corresponding to the access level signal V DD V CM V SS V H and V L The CDAC switch control signal is used to control switches SW1 to SW2. 33 The on / off state.

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