An anti-jamming communication circuit

Abstract

The utility model discloses an anti -interference communication circuit for controlling the external communication of chip, including sending signal path and receiving signal path, sending signal path includes a NMOS pipe, and its chip side sending signal end is connected through the first resistance and the source of NMOS pipe, and the source and the grid of NMOS pipe are connected through the second resistance, and its grid and power connection, and its drain and equipment side sending signal end connection, receiving signal path includes a NMOS pipe, and its chip side receiving signal end is connected through the third resistance and the source of NMOS pipe, and is connected through the fifth resistance and power, and the source and the grid of NMOS pipe are connected through the fourth resistance, and its grid and power connection, and its drain is directly connected with chip side receiving signal end. The circuit has realized the inter -board communication direct connection and communication isolation function through adopting MOS pipe, has effectively blocked the invasion of external high voltage interference signal to the communication interface of control chip, and is a simple, reliable and low -cost solution.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuit technology, and in particular to an anti-interference communication circuit. Background Technology

[0002] Portable power supplies mainly consist of three parts: an inverter, a front control board, and a BMS (Battery Management System). These parts need to communicate with each other to transmit data. There are many ways to achieve communication between these parts, such as optocoupler isolation and dedicated RS485 chip communication, but each has its advantages and disadvantages.

[0003] Figure 1 While optocoupler-isolated communication methods offer simple circuitry, they also have significant drawbacks: First, the LEDs and photosensitive elements inside the optocoupler are greatly affected by ambient temperature; both increases and decreases in temperature will affect the optocoupler's transmission ratio. Therefore, the impact of ambient temperature must be considered during use, and appropriate temperature control or compensation measures must be taken. Second, the large transmission time delay of the optocoupler leads to a higher data packet loss rate.

[0004] Figure 2 The communication method using a dedicated RS485 chip has strong anti-interference ability, good communication quality, and is less affected by ambient temperature. However, dedicated RS485 chips are generally more expensive. Utility Model Content

[0005] This utility model aims to provide a simple, reliable, and low-cost anti-interference communication circuit to achieve short-distance direct communication between boards. The technical solution is as follows: An anti-interference communication circuit is used to control the external communication of a chip, including a signal transmission path and a signal reception path; The signal transmission path includes a first resistor, a second resistor, and a first MOSFET; the chip-side signal transmission terminal of the signal transmission path is connected to the source of the first MOSFET through the first resistor; the source and gate of the first MOSFET are connected through the second resistor, the gate is connected to the power supply, and the drain is connected to the device-side signal transmission terminal. The signal receiving path includes a third resistor, a fourth resistor, a fifth resistor, and a second MOS transistor. The chip-side signal receiving terminal of the signal receiving path is connected to the source of the second MOS transistor through the third resistor and to the power supply through the fifth resistor. The source and gate of the second MOS transistor are connected through the fourth resistor, the gate is connected to the power supply, and the drain is directly connected to the device-side signal receiving terminal. The first MOS transistor and the second MOS transistor are NMOS transistors; The chip-side transmitting signal terminal and the chip-side receiving signal terminal are used to connect with the control chip; The device-side transmitting signal terminal and the device-side receiving signal terminal are used for external connections.

[0006] Furthermore, the power supply is the operating power supply for the control chip.

[0007] Furthermore, the voltage of the power supply is +3.3V.

[0008] Furthermore, the drain-source rated voltage of the PMOS and NMOS transistors is not less than 50V.

[0009] Furthermore, the resistance values ​​of the first resistor and the third resistor are both 100Ω.

[0010] Furthermore, the anti-interference communication circuit is used for two-wire UART communication, including a transmit signal path and a receive signal path.

[0011] Furthermore, the anti-interference communication circuit is used for four-wire SPI communication, and according to the master-slave configuration of SPI communication, it includes one transmit signal path and three receive signal paths, or three transmit signal paths and one receive signal path.

[0012] Technical effects: This utility model's anti-interference communication circuit uses MOS transistors instead of optocouplers or dedicated communication chips to achieve direct inter-board communication and communication isolation, effectively blocking external high-voltage interference signals from invading the MCU communication interface, thus strongly protecting the security of the MCU communication interface and providing a simple, reliable, and low-cost solution. Attached Figure Description

[0013] Figure 1 It is a communication circuit that uses optical isolation; Figure 2 It is a communication circuit using a dedicated RS485 chip; Figure 3 This is an anti-interference communication circuit of the present invention. Detailed Implementation

[0014] To further illustrate the various embodiments, the present invention provides accompanying drawings. These drawings are part of the disclosure of the present invention and are mainly used to illustrate the embodiments, and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these drawings, those skilled in the art should be able to understand other possible implementations and the advantages of the present invention. Components in the drawings are not drawn to scale, and similar component symbols are generally used to represent similar components.

[0015] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments.

[0016] like Figure 3As shown, this utility model proposes a simple anti-interference communication circuit for controlling the UART interface (Universal Asynchronous Receiver / Transmitter) of the MCU chip for external communication, including a transmit signal path and a receive signal path.

[0017] The signal transmission path includes resistors R1 and R2 and MOSFET Q1; where MOSFET Q1 is an NMOS transistor. The chip-side transmit signal terminal TX is connected to the source of MOSFET Q1 through resistor R1. The source of MOSFET Q1 is connected to the +3.3V power supply through resistor R2, its gate is directly connected to the +3.3V power supply, and its drain is connected to the device-side transmit signal terminal TX_out.

[0018] The signal receiving path includes resistors R3, R4, and R5, and MOSFET Q2; MOSFET Q2 is an NMOS transistor. The chip-side receive signal terminal RX is connected to the source of MOSFET Q2 via resistor R3, and to the +3.3V power supply via resistor R5. The source of MOSFET Q2 is connected to the +3.3V power supply via resistor R4, its gate is directly connected to the +3.3V power supply, and its drain is directly connected to the device-side receive signal terminal RX_out.

[0019] Among them, the chip-side transmit signal terminal TX and the chip-side receive signal terminal RX are used to connect with the MCU, while the device-side transmit signal terminal TX_out and the device-side receive signal terminal RX_out are used for external connections.

[0020] The main difference between the circuit structures of the receiving signal path and the transmitting signal path is: In the signal receiving path, the chip-side signal receiving terminal RX is connected to the +3.3V power supply through resistor R5.

[0021] The +3.3V power supply is the operating power supply for the MCU and is directly connected to the MCU's operating power supply to ensure that the chip-side voltage of the anti-interference communication circuit is consistent with the MCU's operating voltage. +3.3V is a typical value for the MCU's power supply voltage; it can also be +5V, +1.8V, etc. In this case, the amplitude range of the high-level and low-level signals needs to be adaptively adjusted according to the MCU's power supply voltage.

[0022] The circuit works as follows: Transmission signal path: (1) When a high-level signal (2.7V~3.3V) is input to the TX terminal of the chip side, the GS voltage of Q1 is insufficient to turn on Q1, and Q1 is turned off. At this time, the high-level signal input to the TX terminal of the chip side is transmitted to the TX_out terminal of the device side through R1 and the body diode of Q1 to realize signal output.

[0023] (2) When a low-level signal (<0.7V) is input to the TX terminal of the chip side, the GS voltage of Q1 (the voltage drop across R2) is sufficient to turn on Q1, and Q1 is turned on. At this time, the voltage of the TX_out terminal of the device side is pulled down to a voltage that is almost the same as the voltage of the TX terminal of the chip side, thus realizing signal output.

[0024] The TX terminal of the chip is connected to the MCU, and the level of its transmitted signal is stable and will not cause external interference.

[0025] Receive signal path: (1) When a high-level signal (2.7V~5V) is input to the device-side receiving signal terminal RX_out, the GS voltage of Q2 (the voltage drop across R4) is insufficient to turn on Q2, and Q2 is turned off. The signal on the device-side receiving signal terminal RX_out cannot be transmitted to RX through resistor R3 and the body diode of Q2. At this time, the chip-side receiving signal terminal RX is pulled up by resistor R5 to set the chip-side receiving signal terminal RX to a high level, thereby realizing signal output.

[0026] (2) When the external RX signal is low (<0.7V), the GS voltage of Q2 is sufficient to turn on Q2, and Q2 turns on; the chip side receiving signal terminal RX is pulled down to a voltage almost the same as the device side receiving signal terminal RX_out, thus realizing signal output.

[0027] The anti-interference principle of this circuit is as follows: (1) Isolation function: During the signal transmission process of the receiving signal terminal RX_out or the transmitting signal terminal TX_out on the device side, the unidirectional conductivity of the diodes in Q1 and Q2 is utilized. If there is a high-level interference signal, it cannot be directly transmitted to the MCU through the diodes in Q1 and Q2, thereby reducing the impact of interference signals on communication signals and protecting the MCU.

[0028] Preferably, to achieve good anti-interference performance, the drain-source rated voltage (VDSS) of the NMOS transistor is not less than 50V.

[0029] (2) Impedance matching: The 100Ω resistors R1 and R3 serve as impedance matching. Proper impedance matching can reduce signal reflection and prevent the reflected signal from superimposing on the original signal and causing interference. For example, in TX signal transmission, R1 can match the impedance between the TX signal source and the transmission line, reducing interference caused by signal reflection.

[0030] Example 2 This anti-interference communication circuit can be configured with several transmit signal paths and several receive signal paths as needed. For example, when used with a four-wire SPI communication interface (serial peripheral interface), the number of transmit and receive signal paths varies depending on the master-slave configuration: when acting as a master device, it is configured as three transmit and one receive; when acting as a slave device, it is configured as three receive and one transmit.

[0031] In summary, the anti-interference communication circuit of this utility model achieves direct inter-board communication and communication isolation by using MOS transistors instead of optocouplers or dedicated communication chips. This effectively blocks external high-voltage interference signals from attacking the MCU communication interface, thus strongly protecting the security of the MCU communication interface and providing a simple, reliable, and low-cost solution.

[0032] Although the present invention has been specifically shown and described in conjunction with preferred embodiments, those skilled in the art should understand that various changes in form and detail may be made to the present invention without departing from the spirit and scope of the present invention as defined in the appended claims, and all such changes shall be within the scope of protection of the present invention.

Claims

1. An anti-interference communication circuit for controlling the external communication of a chip, characterized in that: This includes the signal transmission path and the signal reception path; The signal transmission path includes a first resistor, a second resistor, and a first MOSFET; the chip-side signal transmission terminal of the signal transmission path is connected to the source of the first MOSFET through the first resistor; the source and gate of the first MOSFET are connected through the second resistor, the gate is connected to the power supply, and the drain is connected to the device-side signal transmission terminal. The signal receiving path includes a third resistor, a fourth resistor, a fifth resistor, and a second MOS transistor. The chip-side signal receiving terminal of the signal receiving path is connected to the source of the second MOS transistor through the third resistor and to the power supply through the fifth resistor. The source and gate of the second MOS transistor are connected through the fourth resistor, the gate is connected to the power supply, and the drain is directly connected to the device-side signal receiving terminal. The first MOS transistor and the second MOS transistor are NMOS transistors; The chip-side transmitting signal terminal and the chip-side receiving signal terminal are used to connect with the control chip; The device-side transmitting signal terminal and the device-side receiving signal terminal are used for external connections.

2. The anti-interference communication circuit according to claim 1, characterized in that: The power supply is the operating power supply for the control chip.

3. The anti-interference communication circuit according to claim 1, characterized in that: The voltage of the power supply is +3.3V.

4. The anti-interference communication circuit according to claim 1, characterized in that: The drain-source rated voltage of the NMOS transistor is not less than 50V.

5. The anti-interference communication circuit according to claim 1, characterized in that: The resistance values ​​of the first resistor and the third resistor are 100Ω.

6. The anti-interference communication circuit according to claim 1, characterized in that: The anti-interference communication circuit is used for two-wire UART communication, including a transmit signal path and a receive signal path.

7. The anti-interference communication circuit according to claim 1, characterized in that: The anti-interference communication circuit is used for four-wire SPI communication. Depending on the master-slave configuration of the SPI communication, it includes one transmit signal path and three receive signal paths, or three transmit signal paths and one receive signal path.

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