Semiconductor device

Abstract

A semiconductor device including a high voltage transistor is provided. The high voltage transistor includes a main field plate layer between a gate structure and a drain region of the high voltage transistor, a barrier layer between the main field plate layer and a substrate layer of the high voltage transistor, and a patterned field plate structure laterally between the barrier layer and the drain region. The patterned field plate structure can be formed from the same layer as the gate structure and an associated gate dielectric layer, which minimizes cost, complexity, and manufacturing resources for forming the patterned field plate structure. The patterned field plate structure functions as a self-aligned mask for forming the barrier layer, the drain region, and / or a metal silicide layer on the drain region. This enables closer positioning of the barrier layer and a drain contact on the drain region, and reduces a lateral size of the drain region.

Description

Technical Field

[0001] This utility model relates to a semiconductor device. Background Technology

[0002] A high-voltage transistor is a metal-oxide-semiconductor (MOS) transistor that can be configured to operate at a higher drain voltage than a low-voltage transistor. Low-voltage transistors can be used in applications such as logic circuits (e.g., processors), memory (e.g., static random-access memory (SRAM)), and / or input / output (I / O) circuits. High-voltage transistors can be used in integrated circuit (IC) drivers, power ICs, image sensors, power management, display driver ICs (DDICs), bipolar-CMOS-DMOS ICs (BCDICs), and / or image signal processing (ISP) ICs. Utility Model Content

[0003] This utility model provides a semiconductor device, including: a first source / drain region in a substrate layer; a second source / drain region in the substrate layer; a gate structure above the substrate layer and between the first source / drain region and the second source / drain region; a barrier layer on a first portion of the substrate layer, wherein the barrier layer is located between the gate structure and the second source / drain region; a main field plate layer on the barrier layer; and a patterned field plate structure on a second portion of the substrate layer, wherein the patterned field plate structure is laterally located between the barrier layer and the second source / drain region.

[0004] This utility model provides a semiconductor device, comprising: a first source / drain region in a substrate layer; a second source / drain region in the substrate layer; a gate structure above the substrate layer and between the first source / drain region and the second source / drain region; a gate dielectric layer between the gate structure and the substrate layer; sidewall spacers on the sidewalls of the gate structure; a barrier layer on a first portion of the substrate layer, wherein the barrier layer is located between the sidewall spacers and the second source / drain region, and wherein a first end of the barrier layer is located above the gate structure; a main field plate layer on the barrier layer; and a patterned field plate structure on a second portion of the substrate layer, wherein the patterned field plate structure is laterally located between the barrier layer and the second source / drain region, and wherein a second end of the barrier layer opposite to the first end is substantially in contact with the patterned field plate structure. Attached Figure Description

[0005] The present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the sizes of the various features may be arbitrarily increased or decreased.

[0006] Figure 1 This is a diagram of an exemplary semiconductor device described in this utility model.

[0007] Figure 2A and Figure 2B This is a diagram of an embodiment of the integrated circuit device described in this utility model.

[0008] Figures 3A-3R This is a diagram illustrating an embodiment of the integrated circuit device described in this utility model.

[0009] Figure 4 This is a diagram of an embodiment of the integrated circuit device described in this utility model.

[0010] Figure 5 This is a diagram of an embodiment of the integrated circuit device described in this utility model.

[0011] Figure 6 This is a diagram of an embodiment of the integrated circuit device described in this utility model.

[0012] Figure 7 This is a flowchart of an exemplary process related to forming the semiconductor device described in this utility model. Detailed Implementation

[0013] The following utility model description provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify the utility model description. Of course, these specific examples are merely illustrative and not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the utility model description. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and the like may be used to describe the relationship between one component or feature and another, as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are also intended to cover different orientations of components during use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this invention may be interpreted accordingly.

[0015] To operate at higher drain voltages, high-voltage transistors can be fabricated to withstand higher breakdown voltages. Breakdown voltage is the voltage at which a transistor will stop operating according to its intended operating principle when reached or near a certain voltage. In high-voltage transistors, because they experience high drain voltages, the gate-to-drain voltage may sometimes meet or exceed the high-voltage transistor's breakdown voltage.

[0016] In some cases, it is possible to fabricate high-voltage transistors with minimal distance between the gate structure and drain region, enabling them to achieve a specific breakdown voltage (BV). Increasing the distance between the gate structure and drain region allows for a larger electric field distribution between them, which reduces the peak amplitude of the electric field (and thus increases the breakdown voltage). Furthermore, a field plate layer can be included in the region between the gate structure and drain region to help control the peak electric field between them.

[0017] The region between the gate structure and the drain region is a keep-out area for metal silicide formation. Therefore, a barrier layer is formed on the substrate of the high-voltage transistor in this region to prevent metal silicide formation when a metal silicide layer is formed on the drain region. A field plate layer can be formed on the barrier layer, and the barrier layer provides additional buffering for the field plate layer to further distribute the electric field between the gate structure and the drain region. However, the barrier layer may be subject to manufacturing rules, such as the minimum spacing between the barrier layer and the drain contact of the drain region, and / or the minimum overlap between the barrier layer and the drain region (e.g., to ensure that silicide formation is prevented on the substrate). These manufacturing rules may lead to an increase in the lateral occupancy area of ​​the high-voltage transistor. Due to the specific on-resistance (R0) of the high-voltage transistor… onThe specific on-resistance (SIR) is a function of the resistance of a high-voltage transistor and the device spacing of the high-voltage transistor. Therefore, the increased lateral occupancy due to barrier layer manufacturing rules can result in a higher specific on-resistance for the high-voltage transistor. A higher specific on-resistance increases power consumption, thereby reducing the operating efficiency of the high-voltage transistor. Furthermore, the increased lateral occupancy reduces the density of high-voltage transistors that can be integrated onto a semiconductor device without increasing the lateral occupancy of the semiconductor device itself.

[0018] In some embodiments described in this invention, the high-voltage transistor includes a main field plate layer between the gate structure and the drain region of the high-voltage transistor, a barrier layer between the main field plate layer and the substrate layer of the high-voltage transistor, and a patterned field plate structure laterally positioned between the barrier layer and the drain region. The patterned field plate structure can be formed from the same layers as the gate structure and the associated gate dielectric layer, which minimizes the cost, complexity, and manufacturing resources required to form the patterned field plate structure.

[0019] The patterned field plate structure acts as a self-aligned mask for forming the barrier layer, allowing for precise control over the lateral coverage of the barrier layer on the substrate. Using a patterned field plate structure reduces the spacing between the barrier layer and the drain contact on the drain region of the high-voltage transistor structure, thereby reducing the lateral footprint of the high-voltage transistor structure. Additionally and / or alternatively, the patterned field plate structure serves as a self-aligned mask for forming the drain region and the associated metal silicide layer on the drain region. The use of the patterned field plate structure eliminates the need for partial overlap between the barrier layer and the drain region, which reduces the lateral width of the drain region. The reduced lateral width of the drain region further reduces the lateral footprint of the high-voltage transistor structure.

[0020] This reduction in the lateral occupied area of ​​the high-voltage transistor structure enables the high-voltage transistor to achieve a lower specific on-resistance. Lower specific on-resistance reduces power consumption, thereby improving the operating efficiency of the high-voltage transistor. Furthermore, the reduced lateral occupied area allows for increased density of high-voltage transistors integrated onto semiconductor devices without increasing (or minimizing) the peak electric field between the gate and drain regions of the high-voltage transistor.

[0021] Figure 1 This is a diagram of an exemplary semiconductor device 100 described in this utility model. The semiconductor device 100 may include a system-on-a-chip (SoC) device, a logic device (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)), a memory device (e.g., a high-bandwidth memory (HBM) device), a panel driver device, an integrated circuit (IC) driver, a radio frequency (RF) power amplifier, a display driver IC (DDIC), and / or other types of semiconductor devices.

[0022] like Figure 1 As shown, the semiconductor device 100 may include a device layer 102 and an interconnect layer 104 located above the device layer 102 in the z-direction. The device layer 102 may also be referred to as the front-end region or front-end process (FEOL) region of the semiconductor device 100. The interconnect layer 104 may also be referred to as the back-end region or back-end process (BEOL) region of the semiconductor device 100.

[0023] Device layer 102 includes substrate layer 106. Substrate layer 106 may correspond to a portion of a semiconductor wafer on which semiconductor device 100 is formed. Substrate layer 106 may include a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, or another type of semiconductor substrate. Substrate layer 106 may extend in semiconductor device 100 along the x-direction and / or y-direction.

[0024] Integrated circuit device 108 may be included in and / or on substrate 106 of device layer 102 of semiconductor device 100. Integrated circuit device 108 includes front-end transistor structures (e.g., front-end planar transistor structures, front-end fin field-effect transistor (Fin FET) structures, front-end gate-all-around (GAA) transistor structures), pixel sensors, capacitors, resistors, sensors, photosensors, transceivers, transmitters, receivers, optical circuits, and / or other types of front-end semiconductor devices. A front-end semiconductor device refers to a semiconductor device formed in (e.g., in and / or on) substrate 106 of semiconductor device 100.

[0025] In some embodiments, one or more of the integrated circuit device 108 include a high-voltage transistor (or a medium-voltage transistor). A "high-voltage transistor" refers to a transistor configured to operate at a higher operating voltage (e.g., a higher gate voltage, a higher source / drain voltage) than a low-voltage transistor. As an example, a high-voltage transistor may be configured to operate in a drain voltage range of about 9 volts to about 36 volts, while a low-voltage transistor may be configured to operate in a drain voltage range of about 0 volts to about 1.8 volts. However, other values ​​within these ranges are also within the scope of this invention.

[0026] High-voltage transistors (or medium-voltage transistors) may include laterally diffused (or laterally double-diffused) metal-oxide-semiconductor (LDMOS) transistors with drift regions, wherein charge carriers diffuse laterally to facilitate the distribution of an electric field between the gate structure and the source / drain regions of the high-voltage transistor. The lateral diffusion of charge carriers in the drift regions enables the high-voltage transistor to withstand higher gate and source / drain voltages than a low-voltage transistor (e.g., increasing the breakdown voltage of the high-voltage transistor).

[0027] A dielectric layer 110 is contained above a substrate layer 106. The dielectric layer 110 includes an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and / or another type of dielectric layer. The dielectric layer 110 includes a dielectric material that allows portions of the substrate layer 106 and / or the integrated circuit device 108 to be selectively etched or protected from etching, and / or the integrated circuit device 108 in the electrically isolated device layer 102. The dielectric layer 110 includes silicon nitride (Si). x N y ), oxides (e.g., silicon dioxide (SiO2) x (and / or another oxide material), and / or another type of dielectric material. The dielectric layer 110 may extend in the x and / or y directions in the semiconductor device 100.

[0028] Interconnect layer 104 in semiconductor device 100 is located above substrate layer 106 in the z-direction and above integrated circuit device 108 in semiconductor device 100. Integrated circuit device 108 can be electrically coupled to interconnect layer 104 via contact structure 112. In some embodiments, integrated circuit device 108 can be electrically coupled to gate contacts and source / drain contacts. Contact structure 112 can include contact plugs, vias, pillars, contact pads, and / or other types of conductive contacts. Contact structure 112 can include one or more electrically conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), alloys thereof, metal nitrides containing one or more metals, and / or another electrically conductive material. In some embodiments, a pad is included between contact structure 112 and dielectric layer 110. The pad can include adhesive pads, barrier pads, and / or another type of pad, and can include pad materials such as tantalum (Ta), tantalum nitride (TaN), and / or titanium nitride (TiN).

[0029] Interconnect layer 104 includes multiple dielectric layers (e.g., back-end dielectric layers) arranged in a direction generally perpendicular to substrate layer 106 (e.g., the z-direction). The dielectric layers may include ILD layers 114 and etch stop layers (ESL) 116 arranged alternately in the z-direction. ILD layers 114 and ESL 116 may extend in the x-direction and / or y-direction of semiconductor device 100.

[0030] ILD layers 114 may each comprise oxides (e.g., silicon oxide (SiO2)). xThe dielectric material can be an undoped silicate glass (USG), a boron-containing silicate glass (BSG), a fluorinated silicate glass (FSG), tetraethyl orthosilicate (TEOS), hydrosilsesquioxane (HSQ), and / or other suitable dielectric materials. In some embodiments, the ILD layer 114 comprises an extremely low dielectric constant (ELK) dielectric material having a dielectric constant of less than about 2.5. Examples of ELK dielectric materials include carbon-doped silicon oxide (C-SiO2). x ), amorphous fluorinated carbon (aC) x F y ), parylene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon oxycarbonate (SiOC) polymers, porous hydrosilsesquioxane (HSQ), porous methylsilsesquioxane (MSQ), porous polyarylene ether (PAE) and / or porous silica (SiO2) x )wait.

[0031] ESL 116 can each include silicon nitride (Si). x N y Silicon carbide (SiC), silicon oxynitride (SiON), and / or another suitable dielectric material. In some embodiments, ILD layers 114 and ESL 116 comprise different dielectric materials to provide etching selectivity, thereby enabling the formation of various structures in interconnect layer 104.

[0032] Interconnect layer 104 includes multiple conductive structures. One or more of the conductive structures are electrically coupled and / or substantially coupled to one or more of the integrated circuit devices 108 in device layer 102 (e.g., to contact structures 112 of integrated circuit devices 108). The conductive structures provide electrical wiring to enable signals and / or power to be supplied to and / or from integrated circuit devices 108. The conductive structures may include combinations of metallization structures 118 and interconnect structures 120. Metallization structure 118 may include trenches, metallization layers, conductive traces, and / or other types of metallization structures. Interconnect structure 120 may include vias, plugs, interconnects, and / or other types of interconnect structures. Metallization structure 118 and interconnect structure 120 may be one or more electrically conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of electrically conductive materials. In some embodiments, metallization structure 118 and interconnect structure 120 include one or more pad layers. One or more pad layers may include barrier pads, adhesive pads, and / or another type of pad. Examples of materials for one or more pads include tantalum nitride (TaN) and / or titanium nitride (TiN).

[0033] In some embodiments, the metallization structures 118 and interconnect structures 120 of interconnect layer 104 may be arranged in a vertical manner (e.g., in the z-direction). In other words, a plurality of stacked metallization structures 118 and interconnect structures 120 extend between the top of device layer 102 and interconnect layer 104 to facilitate the routing of electrical signals and / or power between device layer 102 and interconnect structures (not shown) of semiconductor device 100. The plurality of stacked metallization structures 118 may be arranged in a layer, referred to as an M-layer. For example, a metal-O (MO) layer may be located at the bottom of interconnect layer 104 and may be directly coupled to device layer 102 (e.g., coupled to contact structures 112 of integrated circuit device 108 in device layer 102). A via-1 (V1) layer including one or more interconnect structures 120 may be included above the MO layer. The metal-1 layer (M1) can be located above the V1 layer in the interconnect layer 104, the via-2 layer (V2) can be located above the M1 layer, and the metal-2 layer (M2) can be located above the M1 layer. In addition, via layers can be included between the vertically arranged M-layers.

[0034] As mentioned above, providing Figure 1 As an example. Other examples may be similar. Figure 1 The descriptions differ from those in the text.

[0035] Figure 2A and Figure 2B This is a diagram of an embodiment 200 of the integrated circuit device 108 described in this utility model. In embodiment 200, the integrated circuit device 108 includes a high-voltage transistor, such as an LDMOS transistor.

[0036] like Figure 2A and Figure 2B As shown, the integrated circuit device 108 may include a semiconductor device 100 substrate 106 or (or may include on the substrate 106). The integrated circuit device 108 may include an active region 202 in the substrate 106, a bulk region 204 in the substrate 106, a source / drain region 206a in the bulk region 204, a source / drain region 206b in the active region 202, and a gate structure 208 on the active region 202.

[0037] Active region 202 may include a region of substrate 106 in which integrated circuit device 108 operates. Active region 202 may include a doped region of substrate 106, i.e., doped with one or more types of dopants, such as p-type dopants and / or n-type dopants. Active region 202 includes one or more semiconductor materials such that the conductivity of active region 202 can be selectively controlled using an electric field. Thus, based on the conductivity of active region 202, current can selectively flow between source / drain regions 206a and source / drain regions 206b. Voltage can be selectively applied to gate structure 208 to selectively control the conductivity of active region 202 in substrate 106.

[0038] Source / drain region 206a may be located on a first side of gate structure 208 (e.g., laterally adjacent to the first side), and source / drain region 206b may be located on a second side of gate structure 208 opposite to the first side (e.g., laterally adjacent to the second side). Depending on the context, source / drain region may refer to a source region, a drain region, or a combination of source and drain regions. In some embodiments, source / drain region 206a is the source region of integrated circuit device 108, and source / drain region 206b is the drain region of integrated circuit device 108, configured to operate at relatively high voltages (e.g., up to about 36 volts).

[0039] Source / drain regions 206a and 206b may each comprise one or more doped regions of substrate 106. In some embodiments, source / drain regions 206a and 206b may comprise the same dopant type. For example, source / drain regions 206a and 206b may each comprise silicon doped with one or more p-type dopants, such as boron (B) and / or gallium (Ga). Another example is that source / drain regions 206a and 206b may each comprise silicon doped with one or more n-type dopants, such as arsenic (As) and / or phosphorus (P). In some embodiments, source / drain regions 206a and 206b comprise different dopant types. For example, source / drain region 206a may comprise silicon doped with one or more p-type dopants, and source / drain region 206b may comprise silicon doped with one or more n-type dopants.

[0040] The gate structure 208 may be laterally located on the substrate layer 106 between the source / drain regions 206a and 206b. In some embodiments, the gate structure 208 comprises a polysilicon gate. In some embodiments, the gate structure 208 comprises a metal gate and comprises one or more metal materials, such as tungsten (W), titanium (Ti), titanium aluminum (TiAl), and / or other suitable metal materials.

[0041] A gate dielectric layer 210 may be contained on the substrate 106 between the substrate layer 106 and the gate structure 208. In some embodiments, a portion of the gate dielectric layer 210 is located on the bulk region 204, and another portion is contained on the active region 202. The gate dielectric layer 210 can provide electrical isolation between the gate structure 208 and the substrate 106, allowing a voltage applied to the gate structure 208 to cause an electric field to be generated in the substrate 106. In some embodiments, the gate dielectric layer 210 may comprise a low dielectric constant (low k) dielectric material, such as silicon oxide (SiO2). x For example, SiO2). Additionally and / or alternatively, the gate dielectric layer 210 may include a high dielectric constant (high k) dielectric material (e.g., a dielectric material having a dielectric constant greater than about 3.9), such as silicon nitride (SiO2). x N y For example, Si3N4), hafnium oxide (HfO) x For example, HfO2) and / or aluminum oxide (Al) x O y (e.g., Al2O3).

[0042] One or more sidewall spacers 212 may be included on and / or above the sidewalls of the gate structure 208. The sidewall spacers 212 may include silicon oxycarbide (SiOC), nitrogen-free SiOC, or another suitable dielectric material. Due to the directional (e.g., vertical) etching technique used to form the sidewall spacers 212, the sidewall spacers 212 may have curved or rounded outer surfaces.

[0043] The body implantation region 214 may be contained within a bulk region 204 of the substrate layer 106 adjacent to the source / drain region 206a. The body implantation region 214 may be doped with an opposite type of dopant to the source / drain region 206a (e.g., the source / drain region 206a may be doped with an n-type dopant and the body implantation region 214 may be doped with a p-type dopant). An electrical bias is applied to the body implantation region 214 to establish a body bias in the substrate layer 106 to compensate for the threshold voltage (V0) of the integrated circuit device 108. t The offset or change of ).

[0044] like Figure 2A and Figure 2BAs shown, drift region 216 may correspond to a portion of the active region 202 between gate structure 208 and source / drain region 206b. During operation of integrated circuit device 108, depletion region may be formed in drift region 216. In depletion region, the magnitude (or intensity) of the electric field formed in active region 202 is non-uniform between gate structure 208 and source / drain region 206b. The amplitude of the electric field in depletion region may be highest near gate structure 208 and may decrease from gate structure 208 to source / drain region 206b. If the amplitude of the electric field near gate structure 208 reaches the critical breakdown electric field of integrated circuit device 108 (e.g., the maximum electric field at breakdown), it may exceed the breakdown voltage of integrated circuit device 108.

[0045] To suppress the peak electric field in drift region 216 and thus achieve a higher breakdown voltage for integrated circuit device 108, a main field substrate layer may be included over drift region 216 between gate structure 208 and source / drain region 206b. The main field substrate layer 218 may extend along substrate layer 106 between gate structure 208 and source / drain region 206b, and in some embodiments may extend on the sidewalls of gate structure 208, extending beyond portions of gate structure 208 and sidewall spacers 212.

[0046] The main substrate layer 218 can be electrically biased to uniformly distribute the electric field amplitude across the drift region 216, which reduces the peak amplitude of the electric field in the integrated circuit device 108. The main substrate layer 218 may include metals such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), tantalum (Ta), ruthenium (Ru), cobalt (Co), and tungsten (Co). Alternatively and / or, the main substrate layer 218 may include metal nitride materials (e.g., titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), metal oxides (e.g., titanium oxide (TiO2)), and / or another type of metal-containing material.

[0047] A barrier layer 220 may be included between the substrate layer 106 (e.g., drift region 216 in the substrate layer 106) and the main field plate layer 218. The barrier layer 220 may include a resist protective oxide (RPO) layer, which is included to prevent the formation of metal silicides on the substrate layer 106, the gate structure 208, and / or the surface of the integrated circuit device 108, except on the source / drain regions 206a and / or 206b. The barrier layer 220 may also provide a vertical buffer for the main field plate layer 218, allowing the electric field to be further distributed over a larger area for electric field distribution tuning. The barrier layer 220 may include one or more dielectric materials, such as oxides (e.g., SiO2). x (e.g., SiO2), nitrides (e.g., Si)x N y (e.g., Si3N4), carbides, nitrides, carbon oxides, and nitride carbides, polymers, and / or other suitable dielectric materials.

[0048] like Figure 2A and Figure 2B As further shown, the patterned field plate structure 222 may be laterally included on the substrate layer 106 between the barrier layer 220 and the source / drain region 206b. The patterned field plate structure 222 may be included as a self-aligned mask for forming the barrier layer 220 and / or for forming a metal silicide layer on the source / drain region 206b. Specifically, the patterned field plate structure 222 may define the lateral position of the end of the barrier layer 220 facing the source / drain region 206b, and / or may define the lateral position of the end of the metal silicide layer on the source / drain region 206b facing the barrier layer 220. Therefore, a first side of the patterned field plate structure 222 may be adjacent to and in direct substantial contact with the end of the barrier layer 220 facing the source / drain region 206b, and a second side of the patterned field plate structure 222 may be adjacent to the source / drain region 206b. In some embodiments, a first side of the patterned field plate structure 222 is spaced apart from the end of the main field plate layer 218 facing the source / drain region 206b. In some embodiments, the first side of the patterned field plate structure 222 is in direct and substantial contact with the end of the main field plate layer 218 facing the source / drain region 206b.

[0049] The patterned field plate structure 222 provides a clear barrier between the barrier layer 220 and the source / drain region 206b, thus allowing for highly controllable parameters such as the distance between the end of the barrier layer and the contact structure of the source / drain region 206b and / or the formation of the metal silicide layer on the source / drain region 206b.

[0050] In some embodiments, the patterned field structure 222 is formed from the same layers as the gate structure 208 and the gate dielectric layer 210 to minimize the impact on cost, time, and / or complexity of forming the integrated circuit device 108. Therefore, the patterned field structure 222 may include a dielectric layer 224 on the substrate layer 106 and a metal layer 226 (or a polysilicon layer) on the dielectric layer 224. The gate dielectric layer 210 and the dielectric layer 224 may be formed from the same dielectric layer, and the gate structure 208 and the metal layer 226 may be formed from the same metal layer (or the same polysilicon layer). Alternatively, the patterned field structure 222 may include another material composition, such as a monolithic dielectric structure or a monolithic metal (or polysilicon) structure, etc.

[0051] like Figure 2A and Figure 2BAs further shown, dielectric layer 110 may be included above integrated circuit device 108. Field plate contact 228 may extend through dielectric layer 110 and may be included on main field plate layer 218. Bias voltage may be applied to main field plate layer 218 through field plate contact 228 to reduce peak electric field in drift region 216. Bias voltage increases carrier depletion in drift region 216, thereby reducing peak electric field strength in drift region 216. By manipulating the electric field, integrated circuit device 108 can achieve higher breakdown voltage.

[0052] Contact structure 112a (e.g., gate contact) may be included in one or more dielectric layers and may be electrically and / or substantially connected to gate structure 208. Figure 2A As shown, contact structures 112b and 112c (e.g., source / drain contacts) can be included in dielectric layer 110 and can be electrically and / or substantially connected to source / drain regions 206a and 206b, respectively. Alternatively, as... Figure 2B As shown, contact structure 112b can be substantially connected to the body injection region 214. In this embodiment, the source / drain region 206a and the body injection region 214 are electrically connected together, and the source-body voltage (V) SB The contact structure 112b is applied to both the source / drain region 206a and the body injection region 214.

[0053] like Figure 2A and Figure 2B As further shown, metal silicide layers 230a and 230b may be included on the source / drain regions 206a and 206b of the integrated circuit device 108, respectively. Metal silicide layers 230a and 230b may each comprise titanium silicide (TiSi), ruthenium silicide (RuSi), and / or another type of metal silicide material. Metal silicide layers 230a and 230b provide a transition between the semiconductor material of the source / drain region 206a and the metal material of the contact structures 112b and 112c formed on the source / drain regions 206a and 206b, respectively. Metal silicide layers 230a and 230b enable low contact resistance between the contact structures 112b, 112c and the source / drain regions 206a, 206b.

[0054] like Figure 2A and Figure 2BAs further shown, the integrated circuit device 108 may have one or more dimensions. An exemplary dimension D1 may correspond to the lateral distance between the edge of the patterned field plate structure 222 facing the gate structure 208 and the sidewall spacers 212 on the sidewalls of the gate structure 208 facing the source / drain region 206b. Dimension D1 may also correspond to the lateral length of a portion of the barrier layer 220 on the substrate layer 106 between the gate structure 208 and the source / drain region 206b. In some embodiments, dimension D1 is contained in the range of about 200 nanometers to about 500 nanometers. If dimension D1 is less than about 200 nanometers, the integrated circuit device may not achieve a sufficiently high breakdown voltage, while if dimension D1 is greater than about 500 nanometers, the integrated circuit device may not achieve a sufficiently low specific on-resistance. However, other values ​​and ranges besides about 200 nanometers to about 500 nanometers for dimension D1 are also within the scope of this invention. In some embodiments, the lateral distance between the patterned field plate structure 222 and the sidewall spacers 212 is less than the distance between the source / drain region 206b and the gate structure 208 (in...). Figure 2A and Figure 2B (represented as dimension D2).

[0055] Another example is that dimension D3 can correspond to the lateral length (or width) of the source / drain region 206b. In some embodiments, dimension D3 is contained in the range of about 100 nanometers to about 200 nanometers. If dimension D3 is less than about 100 nanometers, the source / drain region 206b may be susceptible to high process variation, while if dimension D3 is greater than about 200 nanometers, the integrated circuit device may not be able to achieve a sufficiently low specific on-resistance. However, other values ​​and ranges of dimension D3 other than about 100 nanometers to about 200 nanometers are also within the scope of this invention.

[0056] Another example of dimension D4 can correspond to the lateral length (or width) of the patterned field plate structure 222. In some embodiments, dimension D4 is contained in the range of about 50 nanometers to about 200 nanometers. If dimension D4 is less than about 50 nanometers, the likelihood of the barrier layer 220 encroaching on the source / drain region 206b may increase, while if dimension D4 is greater than about 200 nanometers, the integrated circuit device may not be able to achieve a sufficiently low specific on-resistance. However, other values ​​and ranges besides about 100 nanometers to about 200 nanometers for dimension D4 are also within the scope of this invention. In some embodiments, the lateral length (dimension D4) of the patterned field plate structure 222 is less than the length of the gate structure 208.

[0057] Another example is that dimension D5 can correspond to the vertical thickness (or height) of the patterned field plate structure 222. Since the patterned field plate structure 222 can be formed from the same layers as the gate structure 208 and the gate dielectric layer 210, dimension D5 can correspond to the total vertical thickness (or height) of the gate structure 208 and the gate dielectric layer 210. However, other values ​​and ranges of dimension D5 are also within the scope of this invention.

[0058] Another exemplary dimension D6 may correspond to the lateral distance between the edge of the patterned field plate structure 222 facing the source / drain region 206b and the contact structure 112c on the source / drain region 206b. In some embodiments, dimension D6 is contained in the range of about 20 nanometers to about 100 nanometers. If dimension D6 is less than about 20 nanometers, the lateral width (or length) of the source / drain region 206b may not be large enough to handle the high drain voltage of the integrated circuit device 108, while if dimension D6 is greater than about 100 nanometers, the integrated circuit device may not be able to achieve a sufficiently low specific on-resistance. However, other values ​​and ranges besides about 20 nanometers to about 100 nanometers for dimension D6 are also within the scope of this invention.

[0059] Another exemplary dimension D7 may correspond to the lateral distance between the edge of the patterned field plate structure 222 facing the gate structure 208 and the edge of the main field plate layer 218 facing the source / drain region 206b. In some embodiments, dimension D7 is contained in the range of about 0 nanometers to about 100 nanometers. If dimension D7 is greater than about 100 nanometers, the integrated circuit device may not be able to achieve a sufficiently high breakdown voltage. However, other values ​​and ranges besides about 0 nanometers to about 100 nanometers for dimension D7 are also within the scope of this invention. In some embodiments, the distance between the patterned field plate structure 222 and the main field plate layer 218 (dimension D7) is smaller than the distance between the patterned field plate structure 222 and the contact structure 112c (dimension D6).

[0060] Thus, the integrated circuit device 108 includes a barrier layer 220 on a substrate layer 106 between the gate structure 208 and the source / drain region 206b, a main field plate layer 218 on the barrier layer 220, and a patterned field plate structure 222 on the substrate layer 106 laterally between the barrier layer 220 and the source / drain region 206b. A first end of the barrier layer 220 may be located above the gate structure 208, and a second end of the barrier layer 220 opposite to the first end may be in substantial contact with the patterned field plate structure 222. The patterned field plate structure 222 can be used as a self-aligned pattern to form the barrier layer 220, thereby enabling precise control of the distance between the barrier layer 220 and the contact structure 112c of the source / drain region 206b. Furthermore, the patterned field plate structure 222 can be used for self-aligned patterning to form a metal silicide layer 230b on the source / drain regions 206b, thereby enabling precise control over the formation of the metal silicide layer 230b only on the source / drain regions 206b. In this way, the patterned field plate structure 222 can compensate for process variations that may occur during the formation of the barrier layer 220 and / or the metal silicide layer 230b, which allows for a reduction in the lateral occupied area of ​​the integrated circuit device 108. This reduction in the lateral occupied area of ​​the integrated circuit device 108 enables the integrated circuit device 108 to achieve a lower specific on-resistance (which improves the operating efficiency of the integrated circuit device 108) and / or to include a higher density of integrated circuit devices 108 within the semiconductor device 100.

[0061] As mentioned above, providing Figure 2A and Figure 2B As an example, other examples may be related to... Figure 2A and Figure 2B The descriptions are different.

[0062] Figures 3A-3R This is a diagram of an embodiment 300 of an integrated circuit device 108 comprising a main field substrate layer 218 and a patterned field substrate structure 222 as described in this invention. In some embodiments, one or more of the operations may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, ion implantation tools, planarization tools, and / or other suitable semiconductor processing tools.

[0063] like Figure 3A As shown, one or more of the operations in Embodiment 300 can be performed in conjunction with the substrate 106 of the semiconductor device 100. The substrate 106 may be provided in the form of a semiconductor wafer or other type of substrate.

[0064] like Figure 3BAs shown, one or more regions in the substrate 106 can be doped to form an active region 202 and / or a bulk region 204. An ion implantation tool can be used to implant dopants (e.g., p-type ions, n-type ions) into the substrate 106 to form the active region 202 and / or the bulk region 204.

[0065] like Figure 3C As shown, a dielectric layer 302 can be formed on the substrate layer 106, and a gate electrode layer 304 can be formed on the dielectric layer 302. The deposition tool can use physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and / or another suitable deposition technique to deposit the dielectric layer 302. In some embodiments, the dielectric layer 302 is formed as portions with different vertical thicknesses. For example, a first portion of the dielectric layer 302 can be formed with a first vertical thickness (in... Figure 3C (represented as dimension D8), and the second portion of dielectric layer 302 can be formed with a second vertical thickness (in... Figure 3C The dimension 302 (denoted as D9) is greater than the first vertical thickness. In some embodiments, a dielectric layer 302 may be deposited and then etched to form portions with different vertical thicknesses. In some embodiments, portions of the dielectric layer 302 with different vertical thicknesses may be deposited in different deposition operations.

[0066] A gate electrode layer 304 may be formed on and / or over the dielectric layer 302. Deposition tools may be used to deposit the gate structure 208 using PVD, CVD, ALD, electroplating, and / or another suitable deposition technique. In some embodiments, a planarization tool is used to planarize the dielectric layer 302 and / or the gate electrode layer 304. Chemical mechanical planarization (CMP) and / or another suitable planarization technique may be used to planarize the dielectric layer 302 and / or the gate electrode layer 304.

[0067] like Figure 3D As shown, a mask layer 306 can be formed on the gate electrode layer 304, and a pattern can be formed in the mask layer 306. In some embodiments, the mask layer 306 is a photoresist layer, and a deposition tool can be used to form the mask layer 306 using spin coating and / or another suitable deposition technique. The pattern can be formed in the mask layer 306 by photolithography, wherein the mask layer 306 can be exposed to a radiation source using an exposure tool to pattern the mask layer 306. A development tool can be used to develop and remove portions of the mask layer 306 to expose the pattern. In some embodiments, the mask layer 306 is a hard mask layer, and an etching tool can be used to etch the mask layer 306 based on the patterned photoresist layer to form the pattern in the mask layer 306.

[0068] like Figure 3E As shown, an etching tool can etch the gate electrode layer 304 based on a pattern in the mask layer 306 to define the metal layer 226 of the gate structure 208 and the patterned field plate structure 222. In some embodiments, a dry etching operation is performed to define the metal layer 226 of the gate structure 208 and the patterned field plate structure 222 such that the sidewalls of the metal layer 226 of the gate structure 208 and the patterned field plate structure 222 are substantially perpendicular. The dry etching operation may include a gas-based etching operation, a plasma-based etching operation, and / or another suitable dry etching operation. Additionally and / or alternatively, a wet etching operation may be performed to define the metal layer 226 of the gate structure 208 and the patterned field plate structure 222.

[0069] like Figure 3F As shown, the etching tool can etch the dielectric layer 302 based on the pattern in the mask layer 306 and / or based on the gate structure 208 and the metal layer 226 to define the gate dielectric layer 210 and the dielectric layer 224 of the patterned field structure 222. As described above, the dielectric layer 302 may include portions with different vertical thicknesses. The dielectric layer 302 can be etched such that the gate dielectric layer 210 includes a portion having a first thickness (size D8) and another portion having a second thickness (size D9) (a larger thickness). Furthermore, the dielectric layer 302 can be etched such that the dielectric layer 224 of the patterned field structure 222 has a second thickness (size D9) (a larger thickness).

[0070] like Figure 3G As shown, sidewall spacers 212 can be deposited on the sidewalls of gate structure 208 using CVD, ALD, PVD, and / or another type of deposition technique (e.g., using deposition tools). In some embodiments, the spacer layer is blanket-deposited on semiconductor device 100 and then etched back to define sidewall spacers 212.

[0071] like Figure 3H As shown, another dielectric layer 308 may be formed on and / or over a portion of the substrate layer 106 between the gate structure 208 and the subsequently formed source / drain regions 206b. The dielectric layer 308 may also be deposited over the gate structure 208, other portions of the substrate layer 106, and / or over the patterned field plate structure 222. The dielectric layer 308 may be deposited using CVD, ALD, PVD, and / or another type of deposition technique.

[0072] like Figure 3IAs shown, an etching tool can be used to subsequently remove portions of the dielectric layer 308 to define a barrier layer 220 between the gate structure 208 and the patterned field structure 222. In some embodiments, a dry etching operation is performed to etch the dielectric layer 308 to define the barrier layer 220. The dry etching operation may include a gas-based etching operation, a plasma-based etching operation, and / or another suitable dry etching operation. Removing portions of the barrier layer 220 on the patterned field structure 222 and portions of the barrier layer 220 on the substrate layer 106 adjacent to the side of the patterned field structure 222 facing away from the gate structure 208, such that the patterned field structure 222 defines an end of the barrier layer 220 facing away from the gate structure 208.

[0073] like Figure 3J As shown, source / drain regions 206a and 206b can be formed in the substrate 106. Furthermore, a body implantation region 214 can be formed in the substrate 106 adjacent to the source / drain region 206a. The source / drain region 206a can be formed on a first side of the gate structure 208, and the source / drain region 206b can be formed on a second side of the gate structure 208 opposite to the first side. Therefore, the gate structure 208 is laterally located between the source / drain regions 206a and 206b. This allows the gate structure 208 to selectively control the conductivity of the active region 202 in the substrate 106 between the source / drain regions 206a and 206b.

[0074] Furthermore, the source / drain region 206b can be formed such that the patterned field plate structure 222 is laterally located between the source / drain region 206b and the barrier layer 220. The patterned field plate structure 222 provides a clear boundary between the edge of the source / drain region 206b and a portion of the substrate layer 106 below the patterned field plate structure 222, which allows the metal silicide layer 230b to be precisely formed on the source / drain region 206b without forming the metal silicide layer 230b on other portions of the substrate layer 106 located between the gate structure 208 and the source / drain region 206b.

[0075] In some embodiments, source / drain regions 206a and 206b can be formed by doping portions of substrate 106. For example, a first portion of substrate 106 may be doped with one or more dopants (e.g., n-type dopants, p-type dopants) to form source / drain region 206a, and a second portion of substrate 106 may be doped with one or more dopants (e.g., n-type dopants, p-type dopants). Ion implantation tools can be used to implant dopant ions into the first and / or second portions of substrate 106 to form source / drain regions 206a and / or source / drain regions 206b. Alternatively and / or alternatively, another doping technique (e.g., diffusion) can be used to form source / drain regions 206a and 206b.

[0076] In some embodiments, source / drain regions 206a and 206b are formed by epitaxial growth of source / drain regions 206a and 206b in a recess in substrate 106. An etching tool can be used to etch substrate 106 to form the recess in substrate 106. The etching operation can be referred to as a strained source / drain (SSD) etching operation, and the recess can be referred to as a strained source / drain recess. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching techniques.

[0077] The deposition tool can be used to form source / drain regions 206a and 206b in the recess. The deposition tool can be used to form source / drain regions 206a and 206b by epitaxial growth, wherein a layer of epitaxial material is deposited in the recess, such that a layer of semiconductor material is formed by epitaxial growth with a specific crystal orientation.

[0078] The materials used to form the source / drain regions 206a and 206b (e.g., silicon (Si), gallium (gas), or another type of semiconductor material) can be doped with p-type dopants (e.g., dopants that include electron acceptor atoms that generate holes in the material), n-type dopants (e.g., dopants that include electron donor atoms that generate mobile electrons in the material), and / or other types of dopants. The material can be doped by adding impurities (e.g., p-type dopants, n-type dopants) to the source gas used during epitaxial operations. Examples of p-type dopants that can be used in epitaxial operations include boron (B) or germanium (Ge). Examples of n-type dopants that can be used in epitaxial operations include phosphorus (P) or arsenic (As).

[0079] Further as Figure 3KAs shown, metal silicide layers 230a and 230b can be formed on source / drain regions 206a and 206b, respectively. A self-aligned silicide process can be performed to form metal silicide layers 230a and 230b. The self-aligned silicide process may include depositing a layer of metal material (e.g., titanium (Ti), cobalt (Co), ruthenium (Ru)) on source / drain regions 206a and 206b using a deposition tool, and then performing an annealing operation to allow the metal material to diffuse into the top surfaces of source / drain regions 206a and 206b to form metal silicide layers 230a and 230b. Patterned field plate structure 222 and barrier layer 220 prevent the formation of a layer of metal material on the substrate layer 106 between gate structure 208 and source / drain region 206b (thereby preventing the formation of metal silicide layer 230b). In some embodiments, another technique is used to form metal silicide layers 230a and 230b.

[0080] like Figure 3L As shown, a metal-containing layer 310 can be formed above the integrated circuit device 108. The deposition tool can use CVD technology, ALD technology, PVD technology, electroplating technology and / or another type of deposition technology to deposit the metal-containing layer 310.

[0081] like Figure 3M As shown, a photoresist layer 312 can be formed on and / or over the metal-containing layer 310. A deposition tool uses spin coating and / or other suitable deposition techniques to deposit the photoresist layer 312. The photoresist layer 312 can be patterned such that it remains over a portion of the metal-containing layer 310 on the barrier layer 220. An exposure tool can be used to expose the photoresist layer 312 to a radiation source to pattern the photoresist layer 312. A development tool can be used to develop and remove portions of the photoresist layer 312 to expose the pattern.

[0082] like Figure 3N As shown, etching operations can be performed based on the pattern in the photoresist layer 312 to etch the metal-containing layer 310, thereby defining the host substrate layer 218. In some embodiments, the etching operation may include a wet etching operation, a dry etching operation (e.g., a gas-based etching operation, a plasma-based etching operation), and / or another suitable etching operation.

[0083] like Figure 3O As shown, the remaining portion of the photoresist layer 312 can be removed after the main substrate layer 218 is formed. In some embodiments, the photoresist removal tool uses chemical stripping, plasma ashing, and / or other techniques to remove the remaining portion of the photoresist layer 312.

[0084] like Figure 3PAs shown, after forming the main substrate layer 218, a dielectric layer 110 can be formed on and / or over the integrated circuit device 108. Deposition tools can be used to deposit the dielectric layer 110 using PVD, CVD, ALD, oxidation, and / or another suitable deposition technique. In some embodiments, a planarization tool is used to perform a CMP operation to planarize the dielectric layer 110.

[0085] like Figure 3Q As shown, a recess 314 can be formed through dielectric layer 110. For example, recess 314 can be formed over source / drain region 206a to expose metal silicide layer 230a on source / drain region 206a. As another example, recess 314 can be formed over source / drain region 206b to expose metal silicide layer 230b on source / drain region 206b. As another example, recess 314 can be formed over gate structure 208 to expose gate structure 208. As another example, recess 314 can be formed over main field substrate layer 218 to expose main field substrate layer 218.

[0086] In some embodiments, a pattern in the photoresist layer is used to form the recess 314. In these embodiments, a photoresist layer can be formed on the dielectric layer 110 using a deposition tool. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch through the dielectric layer 110 to form the recess 314. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching techniques. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to form the recess 314 based on the pattern.

[0087] like Figure 3RAs shown, contact structure 112a (e.g., a gate contact) can be formed in the recess 314 above the gate structure 208, such that contact structure 112a lands on the gate structure 208. Contact structure 112b (e.g., a source / drain contact) can be formed in the recess 314 above the source / drain region 206a, such that contact structure 112b lands on the metal silicide layer 230a on the source / drain region 206a. Contact structure 112c (e.g., a source / drain contact) can be formed in the recess 314 above the source / drain region 206b, such that contact structure 112c lands on the metal silicide layer 230b on the source / drain region 206b. Field plate contact 228 can be formed in a recess 314 above the main field plate layer 218, so that the field plate contact 228 lands on the main field plate layer 218.

[0088] Deposition tools can be used with CVD, PVD, ALD, electroplating, and / or another suitable deposition technique to deposit contact structures 112a-112c and field plate contacts 228. Contact structures 112a-112c and field plate contacts 228 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and contact structures 112a-112c and field plate contacts 228 are deposited on the seed layer. In some embodiments, a liner is deposited in a recess 314, and contact structures 112a-112c and field plate contacts 228 are deposited on the liner in the recess 314. The liner may include a barrier liner, an adhesive liner, and / or another suitable liner. Examples of liner materials include tantalum nitride (TaN), titanium nitride (TiN), and / or other suitable liner materials. In some embodiments, after depositing the contact structures 112a-112c and the field plate contact 228, a planarization operation (e.g., CMP operation) is performed using a planarization tool to planarize the contact structures 112a-112c and the field plate contact 228.

[0089] As mentioned above, providing Figures 3A-3R As an example, other examples may be related to... Figure 3A-3R The descriptions are different.

[0090] Figure 4 This is a diagram of Embodiment 400 of the integrated circuit device 108 described in this utility model. In Embodiment 400, the integrated circuit device 108 includes... Figure 2A and Figure 2B The combination and arrangement of layers and structures are similar to those in embodiment 200 of the integrated circuit device 108. However, as Figure 4As shown, in embodiment 400 of the integrated circuit device 108, the patterned field plate structure 222 is electrically short-circuited with the source / drain contacts of the source / drain region 206b, which is the opposite of the electrically floating structure in embodiment 200 of the integrated circuit device 108. Specifically, the fused contact structure 402 may be formed and included above the patterned field plate structure 222 and the source / drain region 206b, such that both the patterned field plate structure 222 and the source / drain region 206b are electrically connected to the fused contact structure 402.

[0091] As mentioned above, providing Figure 4 As an example. Other examples may be similar. Figure 4 The descriptions differ from those in the text.

[0092] Figure 5 This is a diagram of Embodiment 500 of the integrated circuit device 108 described in this utility model. In Embodiment 500, the integrated circuit device 108 includes... Figure 2A and Figure 2B The combination and arrangement of layers and structures are similar to those in embodiment 200 of the integrated circuit device 108. However, as Figure 5 As shown, in embodiment 500 of integrated circuit device 108, the patterned field plate structure 222 is electrically short-circuited with the contact structure 112c of the source / drain region 206b, which is the opposite of the electrically floating structure in embodiment 200 of integrated circuit device 108.

[0093] Specifically, the contact structure 112c of the patterned field plate structure 222 and the source / drain region 206b can be electrically coupled through one or more metallization structures 118 and / or one or more interconnect structures 120 (not shown) in the interconnect layer 104 of the semiconductor device 100. In some embodiments, the patterned field plate contact 502 can be included on the patterned field plate structure 222 in the dielectric layer 110, and the patterned field plate contact 502 can be electrically coupled to the contact structure 112c through one or more metallization structures 118 and / or one or more interconnect structures 120 in the interconnect layer 104.

[0094] As mentioned above, providing Figure 5 As an example. Other examples may be similar. Figure 5 The descriptions differ from those in the text.

[0095] Figure 6 This is a diagram of Embodiment 600 of the integrated circuit device 108 described in this utility model. In Embodiment 600, the integrated circuit device 108 includes... Figure 2A and Figure 2B The combination and arrangement of layers and structures are similar to those in embodiment 200 of the integrated circuit device 108. However, as Figure 6As shown, in embodiment 600 of integrated circuit device 108, the patterned field plate structure 222 is electrically short-circuited with the main field plate layer 218, which is the opposite of the electrically floating structure in embodiment 200 of integrated circuit device 108. Therefore, the edge of the patterned field plate structure 222 facing the gate structure 208 can directly and substantially contact the edge of the main field plate layer 218 facing the source / drain region 206b.

[0096] As mentioned above, providing Figure 6 As an example. Other examples may be similar. Figure 6 The descriptions differ from those in the text.

[0097] Figure 7 This is a flowchart of an exemplary process 700 related to the formation of the semiconductor device described in this utility model. In some embodiments, one or more semiconductor processing tools are used. Figure 7 One or more process blocks, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools and / or other types of semiconductor processing tools.

[0098] like Figure 7 As shown, process 700 may include forming a first dielectric layer over a substrate layer of a semiconductor device (block 710). For example, one or more semiconductor processing tools may be used to form a first dielectric layer (e.g., dielectric layer 302) on a substrate layer (e.g., substrate layer 106) of a semiconductor device (e.g., semiconductor device 100), as described in this invention.

[0099] like Figure 7 As further shown, process 700 may include forming a gate electrode layer over the first dielectric layer (block 720). For example, one or more semiconductor processing tools may be used to form the gate electrode layer (e.g., gate electrode layer 304) on the first dielectric layer, as described in this invention.

[0100] like Figure 7 As further shown, process 700 may include etching through the gate electrode layer and the first dielectric layer to form a gate structure and a gate dielectric layer of a transistor structure of a semiconductor device, and to form a patterned field structure spaced apart from the gate structure and the gate dielectric layer (block 730). For example, one or more semiconductor processing tools may be used to etch the gate electrode layer and the first dielectric layer to form a gate structure (e.g., gate structure 208) and a gate dielectric layer (e.g., gate dielectric layer 210) of a transistor structure of a semiconductor device, and to form a patterned field structure (e.g., patterned field structure 222) spaced apart from the gate structure and the gate dielectric layer, as described in this invention.

[0101] like Figure 7As further shown, process 700 may include forming a second dielectric layer over a substrate layer (box 740). For example, one or more semiconductor processing tools may be used to form the second dielectric layer (e.g., dielectric layer 308) on the substrate layer, as described in this invention.

[0102] like Figure 7 As further shown, process 700 may include etching a second dielectric layer to form a barrier layer over a substrate layer between the gate structure and the patterned field structure (box 750). For example, one or more semiconductor processing tools may be used to etch the second dielectric layer to form a barrier layer (e.g., barrier layer 220) over a substrate layer between the gate structure and the patterned field structure, as described in this invention.

[0103] Process 700 may include other embodiments, such as the embodiments described below and / or any single embodiment or any combination of one or more other processes described elsewhere in this utility model.

[0104] In the first embodiment, etching the second dielectric layer includes using a gate structure and a patterned field structure as a self-aligned mask to etch the second dielectric layer.

[0105] In the second embodiment, either alone or in combination with the first embodiment, process 700 includes forming a first source / drain region (e.g., source / drain region 206a) adjacent to the gate structure in the substrate layer, and forming a second source / drain region (e.g., source / drain region 206b) adjacent to the gate structure in the substrate layer.

[0106] In a third embodiment, alone or in combination with one or more of the first and second embodiments, process 700 includes forming a metal silicide layer (e.g., metal silicide layer 230b) on the second source / drain region, wherein the barrier layer and patterned field plate structure prevent the metal silicide layer from being formed in the substrate layer between the gate structure and the second source / drain region.

[0107] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, process 700 includes forming a master field sheet layer (e.g., master field sheet layer 218) on the barrier layer, such that the master field sheet layer is spaced apart from the patterned field sheet structure.

[0108] although Figure 7 An exemplary block diagram of process 700 is shown, but in some embodiments, process 700 includes more than Figure 7 The blocks depicted in the diagram may be more blocks, fewer blocks, different blocks, or blocks arranged differently. Alternatively, two or more blocks in process 700 may be executed in parallel.

[0109] Thus, the high-voltage transistor includes a main field plate layer between the gate structure and the drain region of the high-voltage transistor, a barrier layer between the main field plate layer and the substrate layer of the high-voltage transistor, and a patterned field plate structure laterally located between the barrier layer and the drain region. The patterned field plate structure can be formed from the same layers as the gate structure and the associated gate dielectric layer, which minimizes the cost, complexity, and manufacturing resources required to form the patterned field plate structure. The patterned field plate structure serves as a self-aligned mask for forming the barrier layer, the drain region, and / or the metal silicide layer on the drain region. This allows for closer positioning of the drain contacts on the barrier layer and the drain region, and reduces the lateral dimension of the drain region, enabling the high-voltage transistor to achieve a smaller lateral footprint without increasing (or minimally increasing) the peak electric field between the gate structure and the drain region of the high-voltage transistor.

[0110] As described in more detail above, some embodiments of the present invention provide a semiconductor device. The semiconductor device includes: a first source / drain region in a substrate layer; a second source / drain region in the substrate layer; a gate structure above the substrate layer and between the first source / drain region and the second source / drain region; a barrier layer on a first portion of the substrate layer, wherein the barrier layer is located between the gate structure and the second source / drain region; a main field plate layer on the barrier layer; and a patterned field plate structure on a second portion of the substrate layer, wherein the patterned field plate structure is laterally located between the barrier layer and the second source / drain region.

[0111] In some embodiments, the patterned field plate structure includes: a dielectric layer on the second portion of the substrate layer; and a metal layer on the dielectric layer. In some embodiments, the patterned field plate structure is spaced apart from the main field plate layer. In some embodiments, the main field plate layer is in contact with the patterned field plate structure. In some embodiments, the patterned field plate structure is electrically isolated from the second source / drain region. In some embodiments, the patterned field plate structure is electrically connected to the second source / drain region. In some embodiments, the patterned field plate structure is electrically connected to the second source / drain region via a fused contact structure. In some embodiments, the patterned field plate structure is electrically connected to the second source / drain region via a back-end metallization layer in the interconnect layer of the semiconductor device. In some embodiments, the barrier layer is in contact with the patterned field plate structure.

[0112] As described in more detail above, some embodiments of this invention provide methods. The methods include: forming a first dielectric layer on a substrate of a semiconductor device; forming a gate electrode layer on the first dielectric layer; etching the gate electrode layer and the first dielectric layer to form a gate structure and a gate dielectric layer of a transistor structure of the semiconductor device, and to form a patterned field structure spaced apart from the gate structure and the gate dielectric layer; forming a second dielectric layer over the substrate layer; and etching the second dielectric layer to form a barrier layer over the substrate layer between the gate structure and the patterned field structure.

[0113] In some embodiments, etching the second dielectric layer includes using the gate structure and the patterned field plate structure as a self-aligned mask to etch the second dielectric layer. In some embodiments, the method further includes forming a first source / drain region adjacent to the gate structure in the substrate layer; and forming a second source / drain region adjacent to the patterned field plate structure in the substrate layer. In some embodiments, the method further includes forming a metal silicide layer on the second source / drain region, wherein the barrier layer and the patterned field plate structure prevent the formation of the metal silicide layer in the substrate layer between the gate structure and the second source / drain region. In some embodiments, the method further includes forming a main field plate layer on the barrier layer, such that the main field plate layer is spaced apart from the patterned field plate structure.

[0114] As described in more detail above, some embodiments of the present invention provide a semiconductor device. The semiconductor device includes: a first source / drain region in a substrate layer; a second source / drain region in the substrate layer; a gate structure above the substrate layer and between the first source / drain region and the second source / drain region; a gate dielectric layer between the gate structure and the substrate layer; sidewall spacers on the sidewalls of the gate structure; a barrier layer on a first portion of the substrate layer, wherein the barrier layer is located between the sidewall spacers and the second source / drain region, and wherein a first end of the barrier layer is located above the gate structure; a main field plate layer on the barrier layer; and a patterned field plate structure on a second portion of the substrate layer, wherein the patterned field plate structure is laterally located between the barrier layer and the second source / drain region, and wherein a second end of the barrier layer opposite the first end is substantially in contact with the patterned field plate structure.

[0115] In some embodiments, the length of the patterned field plate structure is less than the length of the gate structure. In some embodiments, the distance between the patterned field plate structure and the sidewall spacers is less than the distance between the second source / drain region and the gate structure. In some embodiments, it further includes: a contact structure on the body implantation region, laterally adjacent to and electrically connected to the second source / drain region, wherein the distance between the patterned field plate structure and the main field plate layer is less than the distance between the patterned field plate structure and the contact structure. In some embodiments, the patterned field plate structure includes: a dielectric layer on the second portion of the substrate layer; and a metal layer on the dielectric layer. In some embodiments, the dielectric layer and the gate dielectric layer comprise the same first material composition; and the gate structure and the metal layer comprise the same second material composition.

[0116] The terms “about” and “generally” can indicate that a given quantity varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and are not intended to be limiting. It should be understood that the terms “about” and “generally” can refer to a percentage of the value of a given quantity in this invention.

[0117] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this utility model. Those skilled in the art should understand that this utility model can be used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages of the embodiments introduced in this utility model. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this utility model, and that various changes, substitutions, and modifications can be made to this utility model without departing from its spirit and scope.

Claims

1. A semiconductor device, characterized in that, include: The first source / drain region is in the substrate layer; The second source / drain region is located in the substrate layer; A gate structure is located above the substrate layer and between the first source / drain region and the second source / drain region; A barrier layer is provided on the first portion of the substrate layer. The barrier layer is located between the gate structure and the second source / drain region; The main plate layer, on the barrier layer; and A patterned field plate structure is located on the second portion of the substrate layer. The patterned field plate structure is laterally located between the barrier layer and the second source / drain region.

2. The semiconductor device according to claim 1, characterized in that, The patterned field plate structure includes: A dielectric layer is disposed on the second portion of the substrate layer; and A metal layer on the dielectric layer.

3. The semiconductor device according to claim 1, characterized in that, The patterned panel structure is separated from the main panel layer.

4. The semiconductor device according to claim 1, characterized in that, The main field plate layer is in contact with the patterned field plate structure.

5. The semiconductor device according to claim 1, characterized in that, The patterned field plate structure is electrically isolated from the second source / drain region.

6. The semiconductor device according to claim 1, characterized in that, The patterned field plate structure is electrically connected to the second source / drain region.

7. The semiconductor device according to claim 1, characterized in that, The barrier layer is in contact with the patterned field plate structure.

8. A semiconductor device, characterized in that, include: The first source / drain region is in the substrate layer; The second source / drain region is located in the substrate layer; A gate structure is located above the substrate layer and between the first source / drain region and the second source / drain region; A gate dielectric layer is located between the gate structure and the substrate layer; Sidewall spacers on the sidewalls of the gate structure; A barrier layer is provided on the first portion of the substrate layer. The barrier layer is located between the sidewall spacer and the second source / drain region, and The first end of the barrier layer is located above the gate structure; The main plate layer, on the barrier layer; and A patterned field plate structure is located on the second portion of the substrate layer. The patterned field plate structure is laterally located between the barrier layer and the second source / drain region, and The second end of the barrier layer opposite the first end is in substantial contact with the patterned field plate structure.

9. The semiconductor device according to claim 8, characterized in that, The length of the patterned field plate structure is less than the length of the gate structure.

10. The semiconductor device according to claim 9, characterized in that, The distance between the patterned field plate structure and the sidewall spacer is less than the distance between the second source / drain region and the gate structure.

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