semiconductor element

Abstract

Embodiments of the present disclosure provide a semiconductor device, for example, comprising: a channel region connected to a epitaxial structure in a first direction; a gate structure disposed above the channel region and having a longitudinal axis extending in a second direction substantially perpendicular to the first direction; a contact disposed above the epitaxial structure and having a sidewall in the second direction, wherein a first angle between the sidewall and a top surface of the contact is greater than 90 degrees.

Description

Technical Field

[0001] This disclosure pertains to semiconductor devices. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have spawned generation after generation of ICs, each smaller and more complex than the last. Throughout IC development, functional density (the number of interconnects per wafer area) has generally increased, while geometry (the smallest component (or line) that can be created using manufacturing processes) has decreased. This downsizing process typically benefits production efficiency and reduces associated costs. However, downsizing also increases the complexity of IC processing and manufacturing.

[0003] Therefore, improvements are needed in the processing and manufacturing of ICs. Utility Model Content

[0004] Some embodiments described herein provide a semiconductor element including a channel region connected to an epitaxial structure in a first direction; a gate structure disposed above the channel region and having a longitudinal axis extending in a second direction substantially perpendicular to the first direction; and a contact disposed above the epitaxial structure, the contact including a sidewall in the second direction, wherein a first angle between the sidewall of the contact and a top surface is greater than 90 degrees.

[0005] Some embodiments described herein provide a semiconductor device including a first gate structure and a second gate structure disposed laterally adjacent to a first dielectric layer; a second dielectric layer disposed above the first gate structure, the second gate structure, and the first dielectric layer; a first epitaxial structure disposed between the first gate structure and the second gate structure in a first direction; a contact electrically coupled to the first epitaxial structure, wherein the contact has a top surface that is horizontal to the top surface of the second dielectric layer; and a first isolation region and a second isolation region inserted into the contact in a second direction perpendicular to the first direction, wherein a first angle between a first sidewall of the contact and the top surface of the contact in the second direction is greater than 90 degrees.

[0006] Some embodiments described herein provide a semiconductor device including a first gate structure and a second gate structure laterally disposed adjacent to a first dielectric layer; a second dielectric layer disposed above the first gate structure, the second gate structure, and the first dielectric layer; a first epitaxial structure disposed between the first gate structure and the second gate structure in a first direction; a contact electrically coupled to the first epitaxial structure, wherein the contact has a top surface that is horizontal to the top surface of the second dielectric layer; and a first isolation region and a second isolation region, wherein the first isolation region and the second isolation region are inserted into the contact in a second direction perpendicular to the first direction, wherein a first angle between a first sidewall of the contact and the top surface of the contact in the second direction is greater than 90 degrees, and wherein a second angle between a second sidewall of the contact and the top surface of the contact in the first direction is less than 90 degrees. Attached Figure Description

[0007] The best understanding of this disclosure is achieved by reading the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figures 1 to 6 Perspective views of various stages in the manufacture of a semiconductor device, according to some embodiments;

[0009] Figures 7A to 24C Cross-sectional and plan views of various stages of manufacturing a semiconductor device, according to some embodiments;

[0010] Figures 25A to 25D Cross-sectional and plan views of intermediate stages in the manufacture of semiconductor devices, according to some embodiments;

[0011] Figures 26A to 26C These are cross-sectional and plan views of intermediate stages in the manufacture of semiconductor devices, according to some embodiments.

[0012] [Symbol Explanation]

[0013] 100: Semiconductor components

[0014] 101:Substrate

[0015] 102: Multi-layer stacking

[0016] 104: Semiconductor layer

[0017] 106: Semiconductor layer

[0018] 108: Semiconductor Beam

[0019] 110: Nanostructure

[0020] 112: Nanostructures

[0021] 114: Fins

[0022] 116: Trench

[0023] 118: Insulating materials

[0024] 120: Shallow Trench Isolation Zone (STI Zone)

[0025] 126: Dummy gate structure

[0026] 128: Dummy gate dielectric layer

[0027] 130: Dummy gate electrode

[0028] 132: Hard Mask

[0029] 134: Gate spacer

[0030] 136, 136a, 136b: Spacer layers

[0031] 138: Opening

[0032] 142: Opening

[0033] 144: Insulation layer

[0034] 150: Internal spacer

[0035] 158: Epitaxial Structure (Epitaxial Source / Drain Region)

[0036] 158a: Fin portion

[0037] 158b: Main Structure

[0038] 158N:n-type epitaxial structure

[0039] 158P:p-type epitaxial structure

[0040] 160: Contact Etching Stop Layer (CESL)

[0041] 162: Interlayer dielectric layer (ILD layer)

[0042] 162a: Part

[0043] 164: Opening

[0044] 168: Gate dielectric layer

[0045] 170: Gate electrode

[0046] 172: Gate Structure

[0047] 174: ILD layer

[0048] 176:CESL

[0049] 178: Trench

[0050] 180: Dielectric layer

[0051] 180a: Partial

[0052] 180b: Partial

[0053] 182: Conductive Structure

[0054] 182a: Metal silicide layer

[0055] 182b: Conductive pad

[0056] 182c: Conductive layer

[0057] 184: Source / Drain Contacts

[0058] 184a: First sidewall

[0059] 184b: Second sidewall

[0060] 186: Opening

[0061] 188: Quarantine Zone

[0062] 188a: Dielectric Pad

[0063] 188b: Dielectric filler

[0064] 190: Gate contact

[0065] 190a: Conductive pad

[0066] 190b: Conductive layer

[0067] 200: Semiconductor components

[0068] 282b: Conductive layer

[0069] 284: Source / Drain Contacts

[0070] 288: Quarantine Zone

[0071] 288a: Dielectric Pad

[0072] 288b: Filled dielectric

[0073] 300: Semiconductor Components

[0074] 388: Quarantine Zone

[0075] 388a: Dielectric Pad

[0076] 388b: Filled dielectric

[0077] AA: Section

[0078] BB: Section

[0079] CC: Section

[0080] DD: Section

[0081] Gα, Gβ: Angles

[0082] W1: First width

[0083] W2: Second width

[0084] W3: Third width

[0085] X, Y, Z: Direction

[0086] α: First angle

[0087] β: Second angle

[0088] θ: Third angle

[0089] Φ: Fourth angle Detailed Implementation

[0090] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, references to numbers and / or letters may be repeated. This repetition is for simplicity and clarity and does not, in itself, define relationships between the various embodiments and / or configurations discussed.

[0091] Additionally, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper,” and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another. These spatial relative terms are intended to cover not only the orientations depicted in the figures but also different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0092] The embodiments disclosed herein provide a method for forming source / drain contacts and their fabrication structure. In some embodiments, the method of forming source / drain contacts may include forming a metal line and cutting the metal line by an end-cutting process to separate the metal line from the source / drain contacts. The end-cutting process can provide precise critical dimension control and thus can help mitigate the risk of short circuits forming between adjacent source / drain contacts and / or between the gate structure and its adjacent source / drain contacts.

[0093] While the embodiments disclosed herein are discussed with regard to nanostructured channel FETs (e.g., gate full-loop (GAA) FETs, such as horizontal gate full-loop (HGAA) FETs or vertical gate full-loop (VGAA) FETs), embodiments of some aspects of this disclosure can be used with other processes and / or other devices, such as planar FETs, FinFETs, and other suitable devices. Those skilled in the art will readily understand that other modifications that can be made are also within the scope of this disclosure. In the case of a gate full-loop (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography with self-aligned processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. Next, the sacrificial layer is removed, and the remaining spacers can then be used to pattern the GAA structure.

[0094] Figures 1 to 24C According to embodiments disclosed herein, an exemplary process for manufacturing a semiconductor device 100 is illustrated. It should be understood that additional embodiments of this method may be implemented. Figures 1 to 24C Additional operations are provided before, during, and after the processes shown, and some of these operations can be substituted or eliminated. The order of operations / processes is unrestricted and can be interchanged.

[0095] Figures 1 to 6This is a perspective view of an intermediate stage in the fabrication of a semiconductor device 100 according to some embodiments. The semiconductor device 100 also includes a multilayer stack 102 formed over a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may contain crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), aluminum indium arsenide (InAlAs), gallium arsenide indium (InGaAs), gallium antimony phosphide (GaSbP), gallium antimonide arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. On one hand, the insulating layer is an oxygen-containing layer. The substrate 101 may include various regions in the substrate 101 doped with impurities (e.g., dopants having p-type or n-type conductivity). According to the circuit design, the substrate 101 may include a p-type doped well for an n-type field-effect transistor (NFET) and an n-type doped well for a p-type field-effect transistor (PFET).

[0096] The multilayer stack 102 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructured channels in multi-gate devices, such as nanostructured channel FETs. In some embodiments, the multilayer stack 102 includes first semiconductor layers 104 and second semiconductor layers 106 alternately stacked over a substrate 101. For example, for illustrative purposes, the multilayer stack 102 is shown as including three first semiconductor layers 104 and three second semiconductor layers 106. It should be understood that the multilayer stack 102 may include any number of first semiconductor layers 104 and second semiconductor layers 106. In some embodiments, the first semiconductor layer 104 is formed of a first semiconductor material, and the second semiconductor layer 106 is formed of a second semiconductor material different from the first semiconductor material. The second semiconductor material may have a different etch selectivity and / or oxidation rate than the first semiconductor material. In some embodiments, the first semiconductor material or the second semiconductor material is or includes materials such as SiGe, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, combinations thereof, or similar materials. In some embodiments, the first semiconductor material is formed of Si, and the second semiconductor material is formed of SiGe, or vice versa.

[0097] Each first semiconductor layer 104 may have a thickness ranging from about 5 nm to about 30 nm. Each second semiconductor layer 106 may have a thickness equal to, less than, or greater than that of the first semiconductor layer 104. In some embodiments, each second semiconductor layer 106 has a thickness ranging from about 2 nm to about 50 nm. The first semiconductor layer 104 and the second semiconductor layer 106 are formed by any suitable deposition process, such as epitaxial deposition. For example, the epitaxial deposition of the multilayer stack 102 may be performed by vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and / or other suitable epitaxial growth processes.

[0098] exist Figure 2 In some embodiments, a multilayer stack 102 and a substrate 101 are patterned by one or more etching processes to form semiconductor bundles 108. Each semiconductor bundle 108 may include a first nanostructure 110 and a second nanostructure 112, the first nanostructure 110 being patterned by a first semiconductor layer 104 and the second nanostructure 112 being patterned by a second semiconductor layer 106. After the etching process, the substrate 101 may include a plurality of fins 114. Semiconductor bundles 108 are respectively disposed above the fins 114. The term “nanostructure” is used herein to refer to any portion of material having a nanoscale or even micrometer-scale size and an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to elongated portions of material with circular and substantially circular cross-sections, as well as bundled or rod-shaped portions of material including, for example, cylindrical or substantially rectangular cross-sections.

[0099] The semiconductor bundle 108 can be formed by patterning a hard mask layer (not shown) formed on the multilayer stack 102 using a multi-patterning operation that includes photolithography and etching processes. The etching process can include dry etching, wet etching, and / or other suitable processes such as reactive ion etching (RIE) or neutral beam etching (NBE). The photolithography process can include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to the pattern, performing a post-exposure baking process, and developing the photoresist layer to form a mask element composed of the photoresist layer. In some embodiments, patterning the photoresist layer to form the mask element can be performed using an electron beam lithography process. The etching process forms trenches 116 in unprotected areas through the hard mask layer, through the multilayer stack 102, and into the substrate 101, thereby leaving the semiconductor bundle 108 and fins 114. The trenches 116 extend along the X direction. In some embodiments, the semiconductor bundle 108 and fins 114 have a longitudinal axis along the X direction.

[0100] Semiconductor device 100 may include multiple transistor structures. A first nanostructure 110 or a portion thereof may form the nanostructure channel of the transistor structure in a later manufacturing stage, while a second nanostructure 112 may serve as a sacrificial layer in a subsequent manufacturing stage to allow the nanostructure channel to be surrounded by a gate structure. The transistor structure having the nanostructure channel may be referred to as a nanostructure transistor, nanosheet transistor, nanowire transistor, gate all-ring (GAA) transistor, multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding the nanostructure channel.

[0101] exist Figure 3 In the process, after forming semiconductor bundles 108, an insulating material 118 is formed above substrate 101. The insulating material 118 fills the trenches 116 between adjacent semiconductor bundles 108 until the semiconductor bundles 108 are embedded in the insulating material 118. Next, a planarization operation, such as chemical mechanical polishing (CMP) and / or etching-back, is performed to expose the tops of the semiconductor bundles 108. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-k dielectric material (dielectric constant less than about 3.5), or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as flow CVD (FCVD), low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced CVD (PECVD).

[0102] exist Figure 4 In this process, insulating material 118 is recessed to form a shallow trench isolation (STI) region 120. The recess in insulating material 118 exposes portions of the semiconductor bundle 108 and the substrate 101. The recess in insulating material 118 exposes trenches 116 between adjacent semiconductor bundles 108. The STI region 120 can be formed by suitable processes, such as dry etching, wet etching, or a combination thereof. The top surface of the STI region 120 can be at the same level as or below the top surface of the fin 114, and in contact with the fin 114.

[0103] exist Figure 5 In this configuration, one or more dummy gate structures 126 (only one shown) are formed over a semiconductor element 100. The dummy gate structure 126 is formed over a portion of a semiconductor bundle 108. Each dummy gate structure 126 may include a dummy gate dielectric layer 128, a dummy gate electrode 130, and a hard mask 132. The dummy gate dielectric layer 128, the dummy gate electrode 130, and the hard mask 132 can be formed by sequentially depositing capping layers of the dummy gate dielectric layer 128, the dummy gate electrode 130, and the hard mask 132, and then patterning these layers into the dummy gate structure 126. The dummy gate structure 126 may have a direction substantially perpendicular to the longitudinal direction of the semiconductor bundle 108 (e.g., ...). Figure 5 The longitudinal direction of the X direction (e.g., the X direction in the equation). Figure 5 (in the Y direction). The dummy gate structure 126 can fall on the STI region 120 and span one or more semiconductor bundles 108.

[0104] The dummy gate dielectric layer 128 may include one or more dielectric materials, such as deposited oxide-based materials (e.g., silicon oxide) or materials oxidized from the substrate 101. The dummy gate electrode 130 may include silicon, such as polycrystalline silicon or amorphous silicon. The hard mask 132 may include one or more dielectric layers. For example, the hard mask 132 may be a combination of oxide layers and nitride layers.

[0105] Next, a gate spacer 134 is formed on the sidewall of the dummy gate structure 126. The gate spacer 134 can be formed by conformally depositing one or more layers for the gate spacer 134 and anisotropically etching (e.g., RIE) the one or more layers. Dielectric materials, such as silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), silicon oxide (SiOx), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), and combinations thereof, can be used for the gate spacer 134. In some embodiments, in the same process of forming the gate spacer 134, spacer layers 136a and 136b (… Figure 7C It also forms on the sidewall of fin 114.

[0106] exist Figure 6 In some embodiments, a first opening 138 is formed in the semiconductor bundle 108, fin 114, and substrate 101. The first opening 138 can be formed by removing at least a portion of the semiconductor bundle 108 and substrate 101 that is not protected by the gate spacer 134 and the dummy gate structure 126. In this way, the first opening 138 can be formed between adjacent dummy gate structures 126 in the X direction, such as... Figure 6 (or Figure 7A As shown in the cross-sectional view. The first opening 138 may be recessed below the top surface of the STI region 120, but the first opening may also be recessed to the same level as or above the top surface of the STI region 120. The first opening 138 may be formed by an etching process (isotropic or anisotropic etching process), and the etching process may be selective relative to one or more crystal planes of the substrate 101. The etching process may be dry etching, such as RIE, NBE, etc., or wet etching. The etchant from the etching process may include fluorocarbons or chlorocarbons, such as CH2Cl2, C2H2F2, C2F6, CF4, or the like.

[0107] Figure 7A , Figure 7B and Figure 7C They are along Figure 6 The figures are cross-sectional views of the semiconductor device 100 taken along sections AA, BB, and CC. Throughout this specification, figures with the number "A" are from... Figure 6 The reference section AA was obtained; the drawing number including "B" is from... Figure 6 The reference section BB is obtained from the reference section; the drawing number including "C" is from the reference section BB. Figure 6 The reference section CC was obtained. According to some embodiments, multiple dummy gate structures 126, multiple semiconductor bundles 108, and more details are shown in the cross-sectional view.

[0108] exist Figure 7A , Figure 7B and Figure 7C In this structure, the first opening 138 extends through the stack of the first nanostructure 110 and the second nanostructure 112 and enters the substrate 101. For example... Figure 7C As shown, according to some embodiments, spacer layers 136 are formed on opposite sidewalls of the fin 114. Each spacer layer 136 may include a first spacer layer 136a and a second spacer layer 136b. In some embodiments, the first spacer layer 136a has an L-shape and the second spacer layer 136b has an I-shape, or vice versa. A first opening 138 is interposed between the first spacer layers 136a and exposes the fin 114 / substrate 101. Although Figure 7C The diagram shows that fin 114 is located below spacer layer 136, but the top of fin 114 may be higher than the bottom of spacer layer 136, so that fin 114 can be in physical contact with spacer layer 136.

[0109] exist Figure 8A and Figure 8B In some embodiments, the second nanostructure 112 exposed by the first opening 138 is etched to form the second opening 142. In other words, the second opening 142 can be the space occupied by the second nanostructure 112, including the space between vertically adjacent first nanostructures 110 and the space between the bottommost first nanostructure 110 and the substrate 101. When a selective etchant is used to etch the second semiconductor material of the second nanostructure 112, the first nanostructure 110 and the substrate 101 remain relatively unetched. In embodiments where the second semiconductor material includes, for example, SiGe, an etching process utilizing a hydroxide etchant, such as tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like, is used.

[0110] exist Figure 9A and Figure 9BIn some embodiments, an insulating layer 144 is deposited in a first opening 138 and a second opening 142. In some embodiments, taking into account the dimensional difference between the first opening 138 and the second opening 142, the insulating layer 144 may substantially or completely fill the second opening 142 and form a conformal layer in the first opening 138. The insulating layer 144 may comprise an oxide-containing material, such as silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, or any suitable dielectric material. In some embodiments, the insulating layer 144 comprises a material similar to that of the STI region 120. The insulating layer 144 may be formed by any suitable deposition method, such as FCVD, ALD, PECVD, LPCVD, combinations thereof, etc.

[0111] exist Figure 10A and Figure 10B In some embodiments, an etching process is performed to remove the insulating layer 144 in the first opening 138 and to partially recess the insulating layer 144 in the second opening 142. Figure 8A The etching process can use a selective etchant to etch the insulating layer 144, while the first nanostructure 110 and the substrate 101 can remain relatively unetched. The etching process can be an isotropic etching process. In some embodiments, an isotropic etching process is performed for a sufficient time to remove the insulating layer 144 in the first opening 138 and to laterally recess the insulating layer 144 in the second opening 142. Thus, the insulating layer 144 in the first opening 138 is substantially or completely removed. In embodiments where the insulating layer 144 remains in the first opening 138 after the isotropic etching process, a further anisotropic process can be performed to substantially or completely remove the insulating layer 144 in the first opening 138.

[0112] exist Figure 11A and Figure 11B In some embodiments, an inner spacer 150 is formed in a lateral recess and on the sidewall of the insulating layer 144. The inner spacer 150 can serve as an isolation feature between the subsequently formed epitaxial structure and the gate structure. As will be discussed in more detail below, the epitaxial structure will be formed in the first opening 138, and the insulating layer 144 will be replaced by the gate structure.

[0113] In some embodiments, the inner isolation layer is deposited using a conformal deposition process such as CVD, ALD, or similar processes. The inner isolation layer may comprise a material such as silicon nitride or silicon oxynitride, but any suitable material such as a low-k dielectric material may also be used. The inner isolation layer can then be anisotropically etched, for example via RIE, NBE, etc., using the gate spacer 134 as a mask, to form the inner spacer 150. Although in Figure 11AThe outer wall of the inner spacer 150 is shown to be horizontal to the sidewall of the first nanostructure 110, but the outer wall of the inner spacer 150 may extend beyond or be recessed from the sidewall of the first nanostructure 110. Furthermore, although the outer wall of the inner spacer 150 is... Figure 11A The middle section is shown as straight, but the outer wall of the inner spacer 150 may be concave or convex.

[0114] exist Figures 12A to 12C In some embodiments, an epitaxial structure 158 is formed in a first opening 138. The epitaxial structure 158 can be a source / drain region of the semiconductor device 100 and can also be referred to as an epitaxial source / drain region 158. In this disclosure, the source region and drain region are used interchangeably, and their structures are substantially the same. Furthermore, the source / drain region may refer individually or jointly to a source or drain depending on the context. The epitaxial structure 158 can be formed using epitaxial growth methods such as CVD, ALD, MBE, and combinations thereof. In some embodiments, impurities can be doped on-site when the epitaxial structure 158 is epitaxially deposited. The epitaxial structure 158 can have approximately 1 x 10⁻⁶ ppm. 19 atoms / cm 3 Up to approximately 1x10 21 atoms / cm 3 The impurity concentration between them. The epitaxial structure 158 can apply pressure to the first nanostructure 110, thereby improving the device performance.

[0115] In some embodiments, the epitaxial structure 158 includes more than one epitaxial semiconductor layer. For example, each epitaxial structure 158 may include a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer. Any number of semiconductor material layers can be used in the epitaxial structure 158. The first, second, and third semiconductor material layers may each be formed of the same or different semiconductor materials and doped with different dopant concentrations. In some embodiments, the first semiconductor material layer may have a dopant concentration smaller than that of the second semiconductor material layer and greater than that of the third semiconductor material layer. In embodiments where the epitaxial structure 158 includes three semiconductor material layers, a first semiconductor material layer may be deposited, a second semiconductor material layer may be deposited over the first semiconductor material layer, and a third semiconductor material layer may be deposited over the second semiconductor material layer.

[0116] Figure 12CAn n-type epitaxial structure 158N for n-type FETs (e.g., NMOS) and a p-type epitaxial structure 158P for p-type FETs (e.g., PMOS) are illustrated. In some embodiments, the n-type epitaxial structure 158N for n-type FETs includes Si, SiP, SiC, SiCP, and SiAs, while the p-type epitaxial structure 158P for p-type FETs includes Si, SiGe, and Ge. For p-type FETs, p-type impurities such as boron, boron fluoride, indium, etc., can be incorporated into the p-type epitaxial structure 158P. For n-type FETs, n-type impurities such as phosphorus, arsenic, antimony, etc., can be incorporated into the n-type epitaxial structure 158N. In some embodiments, the p-type epitaxial structure 158P is grown to form facets that may correspond to crystal planes of the material used for the substrate 101. In some embodiments, both the p-type epitaxial structure 158P and the n-type epitaxial structure 158N include a fin portion 158a inserted by the spacer layer 136 and a main structure 158b extending laterally outside the spacer layer 136. In some embodiments, the main structure 158b of the p-type epitaxial structure 158P has a rhombic shape or the like. The n-type epitaxial structure 158N may not have facets.

[0117] exist Figure 13A , Figure 13B and Figure 13CIn some embodiments, a contact etch stop layer (CESL) 160 is conformally formed on the exposed surface of the semiconductor device 100. CESL 160 covers the sidewalls of the STI region 120, the source / drain region 158, and the gate spacer 134. CESL 160 may comprise an oxygen-containing or nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbide, combinations thereof, or similar materials. CESL 160 may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, a first interlayer dielectric (ILD) layer 162 is formed on the CESL 160 above the semiconductor device 100. The material used for the first ILD layer 162 may include compounds containing Si, O, C, and / or H, such as silicon oxide, SiOCH, SiOC, PSG, BSG, BPSG, combinations thereof, or similar materials. Organic materials such as polymers may also be used for the first ILD layer 162. The first ILD layer 162 can be deposited using FCVD, PECVD, or other suitable deposition techniques. In some embodiments, after depositing the first ILD layer 162, a thermal process is performed to cure the first ILD layer 162. After forming the first ILD layer 162, a planarization operation such as CMP is performed to make the top surface of the first ILD layer 162 level with the top surface of the dummy gate electrode 130 or the hard mask 132. In some embodiments that retain the hard mask 132, the planarization process makes the top surface of the first ILD layer 162 level with the top surfaces of the hard mask 132 and the gate spacer 134. In some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 130, the gate spacer 134, and the first ILD layer 162 are level within a process variation. In this embodiment, the top surface of the dummy gate electrode 130 is exposed through the first ILD layer 162.

[0118] exist Figure 14A and Figure 14BIn this process, the dummy gate electrode 130 and the hard mask 132 (if present) are removed. In some embodiments, after the dummy gate electrode 130 is removed, the dummy gate dielectric layer 128 is also removed. The hard mask 132, the dummy gate electrode 130, and the dummy gate dielectric layer 128 can be removed by one or more etching processes. For example, an etching process can be performed by etching the hard mask 132 using the dummy gate electrode 130 as an etch stop, etching the dummy gate electrode 130 using the dummy gate dielectric layer 128 as an etch stop, and then removing the dummy gate dielectric layer 128 by another etching process. In some embodiments, the etching process for etching the dummy gate electrode 130 and the dummy gate dielectric layer 128 may include using a reactive gas that selectively etches the dummy gate electrode 130 and the dummy gate dielectric layer 128 at a faster rate than the first ILD layer 162 or the gate spacer 134. Figure 14B As shown, after the dummy gate dielectric layer 128 and the dummy gate electrode 130 are removed, the insulating layer 144 is exposed.

[0119] exist Figure 15A and Figure 15B In some embodiments, the insulating layer 144 is removed. The insulating layer 144 can be removed by an isotropic etching process, such as wet etching with an etchant containing dilute HF or other suitable etchant. The removal of the hard mask 132, the dummy gate electrode 130, the dummy gate dielectric layer 128, and the insulating layer 144 forms the third opening 164.

[0120] exist Figure 16A and Figure 16B In some embodiments, a gate dielectric layer 168 and a gate electrode 170 are formed to replace the gate. The gate dielectric layer 168 is conformally disposed in a third opening 164. The gate dielectric layer 168 can be formed on the top surface and sidewalls of the substrate 101, and on the exposed surface of the first nanostructure 110. In some embodiments, the gate dielectric layer 168 is also disposed on the top surface of the first ILD layer 162, on the CESL 160, on the gate spacer 134, and on the STI region 120. In some embodiments, the gate dielectric layer 168 comprises one or more layers of dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO, Al2O, TiO, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 168 can be formed by CVD, ALD, or any suitable deposition technique.

[0121] Gate electrodes 170 are disposed above gate dielectric layer 168 and fill the remaining portion of third opening 164. Gate electrodes 170 may include a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. Although Figure 17A and Figure 17B A single-layer gate electrode 170 is shown, but the gate electrode 170 may include any number of pad layers, any number of work function adjustment layers, and filler material. The gate electrode 170 can be formed by CVD, ALD, electroplating, or other suitable deposition techniques. After filling the third opening 164, excess material of the gate dielectric layer 168 and the gate electrode 170 above the top surface of the first ILD layer 162 is removed by a planarization process, such as CMP, until the top surface of the first ILD layer 162 is exposed. The remaining portions of the gate electrode 170 and the gate dielectric layer 168 thus form an alternative gate structure for the semiconductor device 100. The gate electrode 170 and the gate dielectric layer can be collectively referred to as the gate structure 172. The gate structure 172 may surround a channel (i.e., the first nanostructure 110) of the semiconductor device 100.

[0122] like Figure 17A and Figure 17B As further shown, a second ILD layer 174 is disposed above the first ILD layer 162. In some embodiments, the second ILD layer 174 is composed of a dielectric material similar to that of the first ILD layer 162 and is formed by a method similar to the method for forming the first ILD layer 162. In some embodiments, a CESL 176 is also formed before the second ILD layer 174 is formed. CESL 176 may contain a material similar to that of CESL 160 and may be formed by a method similar to the method for forming CESL 160. For example, CESL 176 may contain silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbide, combinations thereof, or similar materials.

[0123] Figures 18A to 18D According to some embodiments, an etching process is performed to form trench 178 once the second ILD layer 174 and CESL 176 are formed. In some embodiments, Figure 18D This is a plan view of semiconductor device 100. Throughout the description, figures including "D" in the figure number are obtained from plan views of semiconductor device 100. According to some embodiments, Figure 18A yes Figure 18D Cross-sectional view of section AA in the middle. Figure 18B yes Figure 18D Cross-sectional view of section BB in the middle. Figure 18C yes Figure 18D A cross-sectional view of section CC. Section AA can be along the X direction, such as... Figure 6 or Figure 18D As shown, the BB section and the CC section can be along the Y direction, such as... Figure 6 or Figure 18D As shown. Reference Figure 18D Each trench 178 may have a straight line pattern. For example, each trench 178 may have a longitudinal axis extending along the longitudinal axis (such as along the Y direction) of the gate electrode 170.

[0124] Please refer to Figure 18A The etching process may include etching the second ILD layer 174, CESL 176, the first ILD layer 162, and CESL 160. In this way, trench 178 can extend from the top surface of the second ILD layer 174 to expose the epitaxial structure 158. Each trench 178 may have tapered or vertical sidewalls extending in the X direction from the top surface of the second ILD layer 174 to the epitaxial structure 158. In some embodiments implementing tapered sidewalls, a portion of the first ILD layer 162 and CESL 176 may remain in the X direction between the trench 178 and the gate structure 172.

[0125] Also refer to Figure 18C The trench 178 can extend below the top surface of the spacer layer 136 or below the main structure 158b of the epitaxial structure 158. In this way, after the trench 178 is formed, the first ILD layer 162 is divided into multiple portions. For example, as... Figure 18D As shown, the first ILD layer 162 may include a first portion 162a disposed above the sidewall of the gate spacer 134 and having a longitudinal axis extending in the Y direction. The first portion of the ILD layer 162 may include a portion disposed above the epitaxial structure 158. The first ILD layer 162 may also include a second portion disposed above the STI region 120 and recessed to have a height lower than the top surface of the spacer layer 136. Each ILD layer 162 may have a line shape extending in the Y direction and a length greater than the length of the epitaxial structure 158 in the Y direction, for example, a length greater than at least about 3 times the length of a corresponding epitaxial structure 158 in the Y direction.

[0126] In some embodiments, the formation of trench 178 includes one or more etching processes. For example, one or more masking layers, such as one or more photoresist layers and / or one or more dielectric layers, may be formed on the second ILD layer 174 and defined as having a pattern of trench 178. The second ILD layer 174, CESL 176, the first ILD layer 162, and CESL 160 may then be etched by one or more etching processes according to the pattern of the masking layers. In some embodiments, the epitaxial structure 158 is not significantly etched when trench 178 is formed. In some embodiments, the outer portions of the epitaxial structure 158 (e.g., at least a portion of the third semiconductor layer) may also be removed while trench 178 is being formed. One or more etching processes may include a first etching process that substantially stops at CESL 176, a second etching process for etching through the first ILD layer 162, and a third etching process for removing CESL 160. In some embodiments, the first, second, and third etching processes may be independently dry or wet etching processes using suitable etchants and etching conditions. CESL176 can reduce or prevent damage to the gate structure 172 by the first etching process. The trench 178 may not expose the gate structure 172. In some embodiments, depending on the size or shape of the trench 178, a portion of the gate spacer 134, such as the sidewall of the gate spacer 134, is exposed by the trench 178, while the top surface of the gate electrode 170 is not exposed by the trench 178.

[0127] exist Figures 19A to 19D In some embodiments, a dielectric layer 180 is formed within a trench 178 and covers the exposed portion of the epitaxial structure 158. The dielectric layer 180 may be conformally deposited in the trench 178 and above the top surface of the second ILD layer 174, for example, extending on the sidewalls of the trench 178, the top surface of the second portion of the first ILD layer 162, and the exposed surface of the epitaxial structure 158. In some embodiments, the dielectric layer 180 is formed of a material with a dielectric constant greater than silicon oxide (e.g., a dielectric constant greater than about 3.9), such as SiN, SiON, SiC, SiCN, SiOCN, combinations thereof, or similar materials. The dielectric layer 180 may have a different material than that of the CESL 160. For example, in one embodiment, the CESL 160 is a SiN layer, while the dielectric layer 180 is a SiON layer. In some embodiments, CESL 160 and dielectric layer 180 comprise the same substrate material (e.g., SiON or SiOCN), and the material of dielectric layer 180 contains more oxygen than the material of CESL 160. Dielectric layer 180 may have a different thickness than CESL 160, but they may also have the same thickness. Dielectric layer 180 may enhance the subsequently formed source / drain contacts 184. Figure 22AThe resistance between the gate electrode 170 and the source / drain contact 184 reduces or prevents short circuits or unwanted leakage between the gate 170 and the source / drain contact 184. The dielectric layer 180 can be formed by any suitable deposition method, such as ALD, CVD, PECVD, or other suitable deposition methods.

[0128] exist Figures 20A to 20D In some embodiments, an etching process is performed to partially remove the dielectric layer 180, exposing the epitaxial structure 158. The etching process may include dry etching, which involves vertically guiding an etchant to the dielectric layer 180. Dry etching may include RIE, NBE, or a combination thereof. Therefore, according to some embodiments, portions of the top surface of the second ILD layer 174, portions of the dielectric layer 180 on the epitaxial structure 158, and the bottom portion of the dielectric layer 180 on top of the first ILD layer 162 are removed, while retaining the sidewall portions 180a of the dielectric layer 180 and the bottom portion 180b of the dielectric layer 180 covered by the main structure 158b of the epitaxial structure 158. For example, as... Figure 20C As shown, the bottom portion 180b of the dielectric layer 180 located on the spacer layer 136 and the lower portion of the epitaxial structure 158 (e.g., the portion below the widest portion in the Y direction of the epitaxial structure 158) can be retained. The bottom portion 180b of the dielectric layer 180 can have a shape corresponding to the spacer layer 136 and the lower portion of the epitaxial structure 158.

[0129] exist Figures 21A to 21D In some embodiments, conductive structures 182 are formed in trenches 178. The conductive structures 182 may have a pattern corresponding to the trenches 178, such as a straight line extending along a longitudinal axis in the Y direction. According to some embodiments, each conductive structure 182 includes a metal silicide layer 182a, a conductive pad 182b, and a conductive layer 182c. The formation of the metal silicide layer 182a and the conductive pad 182b may include forming a conformal metal layer in the trenches 178 and above the top surface of the second ILD layer 174. The conformal metal layer may cover the exposed surface of the epitaxial structure 158, the sidewall portions 180a and bottom portions 180b of the dielectric layer 180, and the top surface of the first ILD layer 162. In some embodiments where the thickness of the dielectric layer 180 is thinner than the thickness of the CESL 160, the conformal metal layer may also contact the CESL 160. The conformal metal layer may be formed by ALD, CVD, PVD, or similar methods.

[0130] An annealing process is then performed to react between the conformal metal layer and the semiconductor material of the epitaxial structure 158, thereby forming a metal silicide layer 182a. Because the metal silicide layer 182a is formed by reacting the conformal metal layer and the epitaxial structure 158, the metal silicide layer 182a can be self-aligned with the epitaxial structure 158, for example, formed on the exposed surface of the epitaxial structure 158. In some embodiments, the conformal metal layer can have sufficient thickness such that the formation of the metal silicide layer 182a does not completely consume the conformal metal layer. In one embodiment, when the conformal metal layer has a thickness of about 5 nm, about 2.5 nm of the conformal metal layer on the epitaxial structure 158 can be consumed to form the metal silicide layer 182a. Thus, after the formation of the metal silicide layer 182a, the conformal metal layer can have a thickness of about 2.5 nm for the portion on the metal silicide layer 182a and a thickness of about 5 nm for the portion not on the metal silicide layer 182a. In some embodiments, the conformal metal layer may include materials such as Ti, W, Pt, Ni, or combinations thereof.

[0131] In some embodiments, a processing step is then performed to convert unreacted portions of the conformal metal layer to form conductive pad 182b. The processing step may include any possible treatment to convert the conformal metal layer into any suitable compound for becoming conductive pad 182b. In some embodiments, the processing step includes a nitriding process to nitrid the unreacted portions of the conformal metal layer into a metal nitride. In embodiments where the conformal metal layer is a Ti layer, conductive pad 182b is a TiN layer. Conductive pad 182b may have a first thickness for portions on the metal silicide layer 182a and a second thickness for portions not on the metal silicide layer 182b, the second thickness being greater than the first thickness.

[0132] In some embodiments, the conductive pad 182b is formed by a deposition process rather than a processing step. In such an embodiment, after the metal silicide layer 182a is formed, the conformal metal layer used to form the metal silicide layer 182a is removed, and the conductive pad 182b is deposited in the trench 178 to cover the metal silicide layer 182a. In embodiments where the conductive pad 182b is formed by a deposition process, the conductive pad 182b may be a conformal layer with a uniform thickness.

[0133] After the conductive pad 182b is formed, a conductive layer 182c is formed. According to some embodiments, the conductive layer 182c fills the remaining space in the trench 178. The conductive layer 182c may be formed of a metallic material having a lower resistivity than the conductive pad 182b and being suitable for etching. For example, the conductive layer 182c may be, or include, tungsten, cobalt, aluminum, ruthenium, or similar materials. The conductive layer 182c can be formed by any suitable deposition process, such as CVD, PVD, electroplating, or other suitable processes. In some embodiments, the conductive pad 182b and the conductive layer 182c include excess portions above the top surface of the second ILD layer 174, and a planarization process such as CMP can be performed to remove excess material from the conductive pad 182b and the conductive layer 182c. In some embodiments, the conductive pad 182b and the conductive layer 182c also extend to and / or fill, such as... Figure 21C The space between adjacent p-type epitaxial structure 158P and n-type epitaxial structure 158N is shown.

[0134] exist Figures 22A to 22E In some embodiments, an end-cutting process is performed on the conductive structure 182 to form source / drain contacts 184. Figure 22E It is drawn along such Figure 22D The diagram shows a cross-sectional view of the DD section. The end-cutting process includes etching the conductive structure 182 to separate the linear conductive structure 182 into discontinuous segments in the Y direction. These discontinuous segments can become source / drain contacts 184.

[0135] In some embodiments, the end-cutting process includes forming a cover mask (not shown) above the top surface of the conductive structure 182 and the second ILD layer 174. The cover mask may comprise one or more photoresist layers located above one or more hard mask layers. The cover mask may be defined as having a metal-cut region. The metal-cut region may have a length in the X direction and a width in the Y direction, with a length-to-width ratio of approximately 0.5:1 to 1:0.5. An etching process may be performed to etch the conductive structure 182 through the metal-cut region of the cover mask, thereby forming an opening 186. For example, the conductive layer 182c and conductive pad 182b below the metal-cut region may be removed to form the opening 186. The opening 186 extends through the conductive structure 182 to separate the conductive structure 182 from the source / drain contacts 184. In some embodiments, the opening 186 partially exposes the epitaxial structure 158. The conductive pad 182b may protect the underlying metal silicide layer 182a and the epitaxial structure 158 during the formation of the opening 186. The cover mask can be removed after the opening 186 and the source / drain contact 184 are formed.

[0136] Etching processes can include wet etching, dry etching, and / or combinations thereof. As an example, dry etching processes can be performed using fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases, and / or plasma, and / or combinations thereof. Due to the etching behavior, the opening 186 can gradually narrow towards the bottom, thus having a wide top width and a narrow bottom width. Therefore, as... Figure 22C As shown, according to some embodiments, the source / drain contact 184 may have a first width W1 at the top of the source / drain contact 184, a second width W2 (e.g., p-type epitaxial structure 158P) at a horizontal position near the top of the epitaxial structure 158, and a third width W3 at the bottom of the source / drain contact 184. The third width W3 is greater than the second width W2, and the second width W2 is greater than the first width W1.

[0137] In some embodiments, the source / drain contact 184 has a first sidewall 184a extending from the top surface of the source / drain contact 184 to the upper portion of the epitaxial structure 158, and a second sidewall 184b extending from the lower portion of the epitaxial structure 158 to the upper portion of the first ILD layer 162. The first sidewall 184a and the second sidewall 184b of the source / drain contact 184 may have different slopes relative to the z-axis, such as... Figure 6 As shown. In some embodiments, the first angle α between the first sidewall 184a of the source / drain contact 184 and the top surface of the source / drain contact 184 is greater than 90 degrees, for example, in the range of about 95 degrees to about 170 degrees, or in the range of about 100 degrees to about 135 degrees. The second angle β between the first sidewall 184a of the source / drain contact 184 and the upper surface of the source / drain contact 184 is less than 90 degrees, for example, in the range of about 10 degrees to about 80 degrees. The third angle θ between the first sidewall 184a of the source / drain contact 184 and the lower surface of the source / drain contact 184 is less than 90 degrees, for example, in the range of about 10 degrees to about 80 degrees. Figure 22C In the illustrated embodiment, the first sidewall 184a and the second sidewall 184b may have a vertical gap in the range of about 1 nm to about 10 nm. Figure 22A As shown, the source / drain contact 184 has a fourth angle Φ between the sidewall and the top surface, and the fourth angle Φ is less than 90 degrees, for example, in the range of about 50 degrees to about 85 degrees.

[0138] exist Figures 23A to 23E In some embodiments, isolation zone 188 is formed in opening 186. Figure 23E It shows along such Figure 23D The diagram shows a cross-sectional view of the DD section. Isolation regions 188 may each include a dielectric pad 188a and a dielectric filler 188b above the dielectric pad 188a. The dielectric pad 188a may be a conformal layer. The dielectric pad 188a may be formed by ALD, CVD, PECVD, or similar methods. In some embodiments, the dielectric pad 188a is formed of a material different from that of dielectric layers 180 and CESL 160, although the dielectric pad 188a may be formed of a material similar to that of dielectric layers 180 or CESL 160. For example, the dielectric pad 188a may include SiN, SiON, SiC, SiCN, SiOCN, combinations thereof, or similar materials. The dielectric pad 188a may provide good adhesion between the source / drain contacts 184 and the dielectric filler 188b, and / or may act as a protective layer for the second ILD layer 174 during planarization processes. In some embodiments, dielectric pad 188a has a thickness different from that of dielectric layer 180 or CESL 160. In some embodiments, dielectric pad 188a may be omitted.

[0139] Dielectric filler 188b may be formed over dielectric pad 188a and fill the remaining space of opening 186. Dielectric filler 188b may be formed of a material similar to that of the first ILD layer 162 and / or the second ILD layer 174, and by a process similar to that used for the first ILD layer 162 and / or the second ILD layer 174. For example, dielectric filler 188b may comprise a material composed of silicon oxide, silicon nitride, silicon oxynitride, SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-k dielectric material (dielectric constant less than about 3.5), or any suitable dielectric material. A planarization process may be performed to remove the dielectric filler layer 188b above the top surface of dielectric pad 188a and the second ILD layer 174. After the planarization process, the top surface of the dielectric pad 188a, the dielectric filler 188b, the source / drain contact 184, and the second ILD layer 174 can be level with each other.

[0140] exist Figures 24A to 24CIn some embodiments, a gate contact 190 is formed in a second ILD layer 174. In some embodiments, the gate contact 190 is formed by forming an opening in the second ILD layer 174 and CESL 176, followed by deposition of a conductive material in the opening. In some embodiments, the opening for the gate contact 190 can be formed by one or more etching processes. The etching process can be dry etching or wet etching. In one embodiment, RIE, NBE, or other suitable etching processes are used to form the opening for the gate contact 190. The opening for the gate contact 190 can extend from the top surface of the second ILD layer 174 and through the second ILD layer 174 and CESL 176 to expose the gate electrode 170. After forming the opening for the gate contact 190, a conductive pad 190a and a conductive layer 190b can then be formed in the opening. The conductive pad 190a can be a conformal layer. For example, the conductive pad 190a can be formed by ALD, CVD, PVD, etc. In some embodiments, the conductive pad 190a comprises a metal nitride, such as TaN, TiN, or WN, combinations thereof, or similar materials. The conductive layer 190b fills the remaining space of the opening. For example, the conductive layer 190b may comprise tungsten, cobalt, aluminum, ruthenium, copper, or similar materials. The conductive layer 190b of the gate contact 190 and the conductive layer 182c of the source / drain contact 184 may be formed of different materials.

[0141] In some embodiments, the deposited conductive pad 190a and the deposited conductive layer 190b also extend above the top surface of the second ILD layer 174. A planarization process such as CMP can be performed to remove excess portions of the conductive pad 190a and conductive layer 190b above the top surface of the second ILD layer 174. The conductive pad 190a can improve adhesion between the second ILD layer 174 and the conductive layer 190b and reduce diffusion of the conductive layer 190b into the second ILD layer 174. However, in some embodiments, the conductive pad 190a can be omitted.

[0142] Please refer to Figure 24A The angle Gα in the X direction between the sidewall of the gate contact 190 and the top surface of the gate contact is less than 90 degrees, for example, in the range of about 30 degrees to about 85 degrees. See also Figure 24B The angle Gβ in the Y direction between the sidewall of the gate contact 190 and the top surface of the gate contact 190 is also less than 90 degrees, for example, in the range of about 30 degrees to about 85 degrees.

[0143] The embodiments disclosed herein provide a method for mitigating the risk of short circuits or leakage between two source / drain contacts 184 in the Y direction or between source / drain contacts 184 and gate structure 172 in the X direction. For example, the process for forming the source / drain contacts 184 may include a metal line forming step (e.g., conductive structure 182) and a metal end-cutting step, wherein the metal end-cutting step can separate the metal line from the source / drain contacts. The end-cutting process can provide precise dimensional control over the spacing between the two contacts. Therefore, compared to methods that directly create the boundaries of source / drain contacts by directly transferring the pattern of the source / drain contacts from a mask (e.g., similar to the method for forming gate contact 190), the line forming / end-cutting method described above can provide better critical dimensional control over the spacing between two adjacent source / drain contacts 184 in the Y direction and the spacing between the source / drain contacts 184 and gate structure 172 in the X direction. Therefore, the risk of short circuits between the two source / drain contacts 184 in the Y direction or between the source / drain contacts 184 and the gate structure 172 in the X direction can be mitigated by using the line forming / end cutting method provided in the embodiments disclosed herein.

[0144] Figures 25A to 25D According to some embodiments, cross-sectional and plan views of an intermediate stage of semiconductor element 200 are shown. Figures 25A to 25C It can correspond to Figures 24A to 24C Furthermore, the isolation zone 288 does not come into contact with the epitaxial structure 158. Figure 25D This is a plan view of an intermediate stage of semiconductor device 200. The epitaxial structure 158 is not damaged during the metal end-cutting process. Isolation region 288 may include a material similar to that of isolation region 188, such as a filled dielectric 288b similar to dielectric filler 188b and an optional dielectric pad 288a similar to dielectric pad 188a. Isolation region 288 can be formed by a method similar to that used to form isolation region 188. Figure 25C As shown, the sidewalls of the source / drain contact 284 can extend continuously from the top surface of the source / drain contact 184 to the bottom surface of the source / drain contact 184. The source / drain contact 284 can be similar to the source / drain contact 184. In such an embodiment, the low-resistivity conductive layer 282b can have an increased volume, and the resistivity of the source / drain contact 284 can be correspondingly reduced. In an embodiment, the isolation region 188 can overlap with the epitaxial structure 158 in a plan view. In some embodiments, the isolation region 188 does not overlap with the epitaxial structure 158 in a plan view.

[0145] Figures 26A to 26C According to some embodiments, cross-sectional and plan views of an intermediate stage of semiconductor element 300 are shown. Figures 26A to 26CIt can correspond to Figures 24A to 24C The bottom of the isolation region 388 may be lower than the bottom of the source / drain contact 184. In some embodiments, the opening 186 ( Figure 22C The conductive structure 182 is over-etched, for example, recessed into the first ILD layer 162, to ensure complete removal of any residue of the conductive structure 182 in the opening 186. The isolation region 388 may include a material similar to that of the isolation region 188, such as a filled dielectric 388b similar to the dielectric filler 188b, and an optional dielectric pad 388a similar to the dielectric pad 188a.

[0146] The embodiments disclosed herein provide methods for forming source / drain contacts and structures manufactured therefrom. In some embodiments, the method of forming source / drain contacts may include forming a metal line and cutting the metal line using an end-cutting process to separate the metal line from the source / drain contacts. The end-cutting process can provide precise critical dimension control and thus can help mitigate the risk of short circuits forming between adjacent source / drain contacts and / or between the gate structure and its adjacent source / drain contacts.

[0147] One embodiment is a semiconductor device including a channel region connected to an epitaxial structure in a first direction; a gate structure disposed above the channel region and having a longitudinal axis extending in a second direction substantially perpendicular to the first direction; and a contact disposed above the epitaxial structure, the contact including a sidewall in the second direction, wherein a first angle greater than 90 degrees is between the sidewall and the top surface of the contact. In one embodiment, the semiconductor device further includes a first dielectric layer above the gate structure, wherein the contact extends through the first dielectric layer, and wherein the top surface of the contact is level with the top surface of the first dielectric layer. In one embodiment, the semiconductor device further includes a first isolation region and a second isolation region disposed on opposite sides of the contact in the second direction. In one embodiment, the top surface of the first isolation region is level with the top surface of the first dielectric layer. In one embodiment, the contact includes a conductive pad and a conductive layer above the conductive pad, wherein the conductive layer is in physical contact with the first and second isolation regions. In one embodiment, the semiconductor device further includes a second dielectric layer formed of a material with a dielectric constant greater than 3.9, wherein the second dielectric layer includes a first portion disposed between the contact and the gate structure. In one embodiment, the second dielectric layer further includes a second portion that is in physical contact with the epitaxial structure and is separated from the first portion of the second dielectric layer.

[0148] Another embodiment is a semiconductor device including a first gate structure and a second gate structure laterally adjacent to a first dielectric layer; a second dielectric layer disposed above the first gate structure, the second gate structure, and the first dielectric layer; a first epitaxial structure disposed between the first gate structure and the second gate structure in a first direction; a contact electrically coupled to the first epitaxial structure, wherein the top surface of the contact is horizontal to the top surface of the second dielectric layer; and a first isolation region and a second isolation region, wherein the first isolation region and the second isolation region are inserted into the contact in a second direction perpendicular to the first direction, wherein in the second direction, a first angle between a first sidewall of the contact and the top surface of the contact is greater than 90 degrees. In one embodiment, both the first isolation region and the second isolation region have a top surface horizontal to the top surface of the second dielectric layer, and both have a bottom surface lower than the bottom surface of the second dielectric layer. In one embodiment, the contact includes a conductive pad and a conductive layer above the conductive pad, wherein the conductive layer is in physical contact with the first isolation region and the second isolation region. In one embodiment, the conductive layer is separated from the first epitaxial structure and the first dielectric layer by a conductive pad. In one embodiment, the second angle between the second sidewall of the contact and the top surface of the contact in the first direction is less than 90 degrees. In one embodiment, the semiconductor element further includes a second epitaxial structure disposed between the first gate structure and the second gate structure, wherein the contact extends between the first epitaxial structure and the second epitaxial structure and is in physical contact with the second epitaxial structure. In one embodiment, the semiconductor element further includes a third dielectric layer, the third dielectric layer including a first portion disposed between the contact and the first gate structure, and a second portion disposed between the contact and the second gate structure, wherein the top surface of each of the first portion and the second portion of the third dielectric layer is horizontal to the top surface of the contact and has a longitudinal axis extending along the second direction.

[0149] Another embodiment is a method of forming a semiconductor device, the method comprising: forming an epitaxial structure connected to a channel region in a first direction; forming a gate structure over the channel region, wherein the gate structure has a longitudinal axis extending along a second direction substantially perpendicular to the first direction; forming a contact over the epitaxial structure, the contact including a first sidewall in the second direction, wherein a first angle between the first sidewall and the top surface of the contact is greater than 90 degrees. In one embodiment, forming the contact includes forming a first dielectric layer covering the epitaxial structure; forming a gate structure in the first dielectric layer; forming a second dielectric layer over the gate structure and the first dielectric layer; forming a first opening in the second dielectric layer and the first dielectric layer to expose the epitaxial structure, wherein the first opening has a longitudinal axis along the second direction; forming a conductive structure in the first opening; etching the conductive structure to form a second opening and a third opening, wherein the second opening and the third opening cut the conductive structure to the contact; and forming a first isolation region and a second isolation region in the second opening and the third opening, respectively. In one embodiment, the second opening and the third opening each have a bottom surface below the bottom surface of the second dielectric layer. In one embodiment, the length of the second opening in the second direction is less than the length of the first opening in the second direction. In one embodiment, the method further includes forming a third dielectric layer in the first opening, wherein forming the third dielectric layer includes depositing a conformal layer in the first opening and partially removing the bottom portion of the conformal layer. In one embodiment, the contact has a second sidewall in the first direction, wherein a second angle between the second sidewall and the top surface of the contact is less than 90 degrees.

[0150] Another embodiment is a semiconductor device including a first gate structure and a second gate structure disposed laterally adjacent to a first dielectric layer; a second dielectric layer disposed above the first gate structure, the second gate structure and the first dielectric layer; a first epitaxial structure disposed between the first gate structure and the second gate structure in a first direction; a contact electrically coupled to the first epitaxial structure, wherein the top surface of the contact is horizontal to the top surface of the second dielectric layer; and a first isolation region and a second isolation region, wherein the first isolation region and the second isolation region are inserted into the contact in a second direction perpendicular to the first direction, wherein in the second direction, a first angle between a first sidewall of the contact and the top surface of the contact is greater than 90 degrees, and wherein a second angle between a second sidewall of the contact and the top surface of the contact in the first direction is less than 90 degrees.

[0151] The foregoing summary outlines several features of the embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: A channel region is connected to an epitaxial structure in a first direction; A gate structure is disposed above the channel region and has a vertical axis that extends along a second direction substantially perpendicular to the first direction; as well as A contact element is disposed above the epitaxial structure, and the contact element includes a sidewall in the second direction, wherein a first angle between the sidewall of the contact element and a top surface is greater than 90 degrees.

2. The semiconductor device as claimed in claim 1, characterized in that, It further includes a first dielectric layer above the gate structure, wherein the contact extends through the first dielectric layer, and wherein the top surface of the contact is level with a top surface of the first dielectric layer.

3. The semiconductor device as described in claim 2, characterized in that, It further includes a first isolation zone and a second isolation zone, disposed on opposite sides of the contact member in the second direction.

4. The semiconductor device as claimed in claim 3, characterized in that, The top surface of the first isolation zone is at the same level as the top surface of the first dielectric layer.

5. The semiconductor device as claimed in claim 4, characterized in that, The contact includes a conductive pad and a conductive layer above the conductive pad, wherein the conductive layer is in physical contact with the first isolation area and the second isolation area.

6. The semiconductor device as claimed in claim 1, characterized in that, It further includes a second dielectric layer formed of a material with a dielectric constant greater than 3.9, wherein the second dielectric layer includes a first portion disposed between the contact and the gate structure.

7. The semiconductor device as claimed in claim 6, characterized in that, The second dielectric layer further includes a second portion that is in physical contact with the epitaxial structure and is spaced apart from the first portion of the second dielectric layer.

8. A semiconductor element, characterized in that, Include: A first gate structure and a second gate structure are laterally adjacent to a first dielectric layer; A second dielectric layer is disposed above the first gate structure, the second gate structure and the first dielectric layer; A first epitaxial structure is disposed between the first gate structure and the second gate structure in a first direction; A contact element is electrically coupled to the first epitaxial structure, wherein the contact element has a top surface that is level with a top surface of the second dielectric layer. as well as A first isolation zone and a second isolation zone are provided, and the contact is inserted in a second direction perpendicular to the first direction, wherein a first angle between a first sidewall of the contact and the top surface of the contact in the second direction is greater than 90 degrees.

9. The semiconductor device as claimed in claim 8, characterized in that, Each of the first isolation region and the second isolation region has a top surface that is level with the top surface of the second dielectric layer, and each of the first isolation region and the second isolation region has a bottom surface that is lower than the bottom surface of the second dielectric layer.

10. A semiconductor element, characterized in that, Include: A first gate structure and a second gate structure are laterally adjacent to a first dielectric layer; A second dielectric layer is disposed above the first gate structure, the second gate structure and the first dielectric layer; A first epitaxial structure is disposed between the first gate structure and the second gate structure in a first direction; A contact element is electrically coupled to the first epitaxial structure, wherein the contact element has a top surface that is level with a top surface of the second dielectric layer. as well as A first isolation zone and a second isolation zone are provided, and the contact is inserted in a second direction perpendicular to the first direction, wherein a first angle between a first sidewall of the contact and the top surface of the contact in the second direction is greater than 90 degrees, and wherein a second angle between a second sidewall of the contact and the top surface of the contact in the first direction is less than 90 degrees.

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