Semiconductor device

Abstract

A semiconductor device includes a substrate, a source region, a drain region, and a channel region separating the source region from the drain region, each formed in the substrate and offset from one another along a first direction. The semiconductor device includes a gate dielectric formed over the channel region, the channel region including a first dielectric material having a first dielectric constant and located over a central portion of the channel region, and a second dielectric material having a second dielectric constant and located over first and second ends of the channel region, the second dielectric constant being less than the first dielectric constant, the first and second ends of the channel region separated from one another by the central portion along a second direction, the second direction being perpendicular to the first direction. The semiconductor device further includes an insulating structure having a first portion and a second portion along opposite sides of the channel region along the second direction.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device that can improve current / voltage characteristics. Background Technology

[0002] The semiconductor industry has grown due to continuous advancements in the integration density of various electronic components, such as transistors, diodes, resistors, inductors, and capacitors. For the most part, these improvements in integration density stem from the continuous reduction in the smallest feature size, allowing more components to be integrated into a given area. In this regard, individual transistors, interconnects, and related structures have become increasingly smaller, and there is a continuous need to develop new materials, processes, and designs for semiconductor devices and interconnects to allow for further advancements. Utility Model Content

[0003] A semiconductor device includes a substrate, a source region, a drain region, a channel region, a gate dielectric, and an insulating structure. The channel region extends from the drain region to the source region, each formed in the substrate and separated from each other along a first direction. The gate dielectric is formed on the channel region and includes a first dielectric material and a second dielectric material, the first dielectric material including a first dielectric constant and the second dielectric material including a second dielectric constant, the second dielectric constant being less than the first dielectric constant. The insulating structure is formed in the substrate, including a first portion and a second portion, the first portion and the second portion being located on multiple opposite sides of the channel region along a second direction perpendicular to the first direction. The first dielectric material is located on a central portion of the channel region, and the second dielectric material is located on a first end and a second end of the channel region, the first end and the second end being separated from each other along the second direction through the central portion of the channel region.

[0004] A semiconductor device includes a substrate, a source region, a drain region, a channel region, a gate dielectric, and an insulating structure. The channel region extends from the drain region to the source region, each formed in the substrate and separated from each other along a first direction. The gate dielectric is formed on the channel region and includes a first dielectric material and a second dielectric material, the first dielectric material including a first dielectric constant and the second dielectric material including a second dielectric constant. The insulating structure is formed in the substrate and includes a first portion and a second portion, the first portion and the second portion being located on multiple opposite sides of the channel region along a second direction perpendicular to the first direction. The first dielectric material includes a first width and the second dielectric material includes a second width, the first width being between 70% and 90% of the total width, the total width being the sum of the first width and the second width, and the first dielectric material being located on a central portion of the channel region and the second dielectric material being located on a first end and a second end of the channel region, the first end and the second end being separated from each other along the second direction through the central portion of the channel region.

[0005] A semiconductor device includes a substrate, a source region, a drain region, a channel region, a gate dielectric, and an insulating structure. The channel region extends from the drain region to the source region, each formed in the substrate and separated from each other along a first direction. The gate dielectric is formed on the channel region and includes a first dielectric material and a second dielectric material, the first dielectric material including a first dielectric constant and the second dielectric material including a second dielectric constant, the second dielectric constant being less than the first dielectric constant. The insulating structure is formed in the substrate and includes a first portion and a second portion, wherein the first dielectric material is located on a central portion of the channel region and the second dielectric material is located on a first end and a second end of the channel region, the first end and the second end being separated from each other along a second direction through the central portion of the channel region, and the second dielectric material further extends over a plurality of separate edges of the first end of the channel region and over the second end of the channel region. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, the features disclosed herein are readily understood from the detailed description that follows. It is worth noting that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features have been arbitrarily increased or decreased.

[0007] Figure 1 According to various embodiments, this is a vertical cross-sectional view of a semiconductor structure after the formation of a complementary metal-oxide-semiconductor (CMOS) transistor, wherein a first metal interconnect structure is formed in a low-level dielectric material layer and an insulating dielectric layer.

[0008] Figure 2 According to various comparative embodiments, a vertical cross-sectional view of an intermediate structure that can be used in the formation of a semiconductor device is provided.

[0009] Figure 3A According to the comparative embodiment, this is a top view of the semiconductor device;

[0010] Figure 3B yes Figure 3A A vertical cross-sectional view of a semiconductor device;

[0011] Figure 4A According to the comparative embodiment, this is a vertical cross-sectional view of a semiconductor device showing details of the channel region and the insulation structure;

[0012] Figure 4B Is for Figure 4A A current-voltage diagram of a semiconductor device;

[0013] Figure 5A According to various embodiments, this is a top view of a semiconductor device having two gate dielectric materials;

[0014] Figure 5B According to various implementation methods, it is Figure 5A A vertical cross-sectional view of a semiconductor device;

[0015] Figure 6A According to various embodiments, this is a top view of a further semiconductor device having two gate dielectric materials;

[0016] Figure 6B According to various implementation methods, it is Figure 6A A vertical cross-sectional view of a semiconductor device;

[0017] Figure 7A According to various embodiments, this is a top view of a semiconductor device having three dielectric materials;

[0018] Figure 7B According to various implementation methods, it is Figure 7A A vertical cross-sectional view of a semiconductor device;

[0019] Figure 8A According to various embodiments, this is a top view of a semiconductor device having three dielectric materials;

[0020] Figure 8B According to various implementation methods, it is Figure 8A A vertical cross-sectional view of a semiconductor device;

[0021] Figure 9A According to various embodiments, this is a top view of a semiconductor device having four dielectric materials;

[0022] Figure 9B According to various implementation methods, it is Figure 9A A vertical cross-sectional view of a semiconductor device;

[0023] Figure 10A According to various embodiments, this is a top view of a semiconductor device having four dielectric materials;

[0024] Figure 10B According to various implementation methods, it is Figure 10A A vertical cross-sectional view of a semiconductor device;

[0025] Figure 11 According to various embodiments, flowcharts illustrating the operation of a method for forming a semiconductor device are provided;

[0026] Figure 12 According to various embodiments, flowcharts illustrating further methods for forming semiconductor devices are provided.

[0027] [Symbol Explanation]

[0028] Wa: First width

[0029] Wb: Second width

[0030] VTa: First threshold voltage

[0031] VTb: Second threshold voltage

[0032] 100, 300, 400a, 500, 600, 700, 800, 900, 1000: Semiconductor structure, semiconductor device

[0033] 102,202,302:Substrate

[0034] 104: Semiconductor material layer

[0035] 106: Shallow trench insulation structure

[0036] 106a, 106b: Shallow trench insulation structure

[0037] 108: Field-Effect Transistor

[0038] 110: Source Region

[0039] 112: Drain region

[0040] 114: Passage Area

[0041] 114a: Central Section

[0042] 114b: First end

[0043] 114c: Second end

[0044] 116: Gate dielectric, gate structure

[0045] 118, 118a, 118b, 118c, 118d: Gate dielectric layer, gate dielectric, dielectric material

[0046] 120: Gate electrode, gate

[0047] 122: Gate cap dielectric

[0048] 124: Dielectric gate spacer

[0049] 126, 128: Metal-semiconductor alloy region

[0050] 130: Memory Array Area

[0051] 132: Outer Zone

[0052] 134: Complementary Metal-Oxide-Semiconductor Circuits

[0053] 136, 138, 140: Dielectric material layers

[0054] 142, 144, 146, 148: Metal internal structure, metal perforated structure, metal wire structure

[0055] 150: Insulation Matrix Layer

[0056] 200: intermediate structure, structure

[0057] 204: Etching Stop Layer

[0058] 206: First inner dielectric layer

[0059] 304: Source electrode

[0060] 306: Drain electrode

[0061] 308a: Part 1, Insulation Structure

[0062] 308b: Part Two, Insulation Structure

[0063] 310: Gate contact

[0064] 400b: Current-Voltage Diagram

[0065] 402a: First current

[0066] 402b: Second Current

[0067] 602a, 602b: Structure of silicon local oxidation technology

[0068] 602L: Semiconductor oxide layer

[0069] 1100, 1200: Method

[0070] 1102, 1104, 1106, 1108, 1202, 1204, 1206: Operations

[0071] B-B': Cross section Detailed Implementation

[0072] The following disclosure provides many different implementations, for example, different features for implementing the subject matter. Specific examples of elements and arrangements are described below to simplify this disclosure. These are, of course, merely examples and not intended to be limiting. For example, in the description, the formation of a first feature on or over a second feature includes an implementation in which the first and second features are formed in direct contact, and may also include an implementation in which an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, references to numbers and / or letters may be repeated in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself define the relationship between the various implementations and / or configurations discussed.

[0073] Furthermore, spatially related terms such as “below,” “below,” “lower,” “above,” “upper,” etc., may be used herein for the sake of simplicity in describing the relationship between another element or feature and another element or feature illustrated in the accompanying drawings. In addition to describing orientation in the accompanying drawings, spatially related terms are intended to include different orientations of the apparatus in use or operation. Instruments may be oriented in other ways (rotated 90 degrees or otherwise). The spatially relative descriptions used herein are also to be interpreted accordingly. Unless otherwise expressly stated, each element having the same reference numerals is assumed to have the same material composition and thickness within the same thickness range.

[0074] In the context of power semiconductor devices, a "double peak" or "peak source" typically refers to the phenomenon where the device exhibits two distinct peaks or spikes in its behavior, often in the current-voltage characteristic curve (e.g., as shown in the image). Figure 4B (As shown). The presence of these double peaks increases noise problems associated with such devices, complicating device operation and introducing unwanted interference. A significant noise problem in high-voltage components characterized by double peaks is related to switching dynamics. During switching, such as the transition between on and off, the device can experience sudden changes in current or voltage levels. These rapid transitions can lead to the generation of high-frequency noise, including electromagnetic interference (EMI) and radio frequency interference (RFI). Such noise propagates through the circuit, affecting adjacent components and potentially causing malfunctions or performance degradation. Furthermore, the presence of double peaks in device behavior can be characterized by non-ideal features such as oscillation or instability. These non-ideal behaviors can exacerbate noise-related problems, leading to unpredictable device performance and reduced reliability.

[0075] The disclosed embodiments offer advantages in the presence of semiconductors. In this regard, embodiments of the semiconductor device include a gate dielectric having a channel region of varying width, such that at least one of the work function or dielectric constant has a first value above the central portion of the channel region and a second value above the first and second ends of the channel region. The variation in the gate dielectric composition compensates for non-uniform electric field distributions occurring within the channel region, resulting in a smooth current-voltage relationship without "peaks," which can exist in other devices with gate dielectrics of uniform composition.

[0076] According to various implementation methods Figure 1 This is a vertical cross-sectional view of semiconductor structure 100. Semiconductor structure 100 includes a substrate 102, such as a silicon substrate. Substrate 102 includes a semiconductor material layer 104 at least on its upper portion. Semiconductor material layer 104 is a surface portion of the overall semiconductor substrate or an upper semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, semiconductor material layer 104 includes a single-crystal semiconductor material, such as single-crystal silicon.

[0077] The shallow trench insulating structure 106 (STI) includes a dielectric material such as silicon oxide formed in the upper portion of the semiconductor material layer 104. Suitable doping of semiconductor voids, such as p-type voids and n-type voids, is formed in each region, each region being laterally covered by a portion of the shallow trench insulating structure 106. The field-effect transistor 108 includes a source region 110, a drain region 112, a channel region 114 extending over the drain region 112 and the source region 110 along the surface of the substrate 102, and a gate structure 116. The channel region 114 comprises a single-crystal semiconductor material in some embodiments.

[0078] Each gate structure 116 includes a gate dielectric layer 118, a gate electrode 120, a gate cap dielectric 122, and a dielectric gate spacer 124. Source-side metal-semiconductor alloy regions 126 are formed on each source region 110, and drain-side metal-semiconductor alloy regions 128 are formed on each drain region 112. In some embodiments, devices are formed on the upper surface of the semiconductor material layer 104, including complementary metal-oxide-semiconductor (CMOS) transistors and optionally additional semiconductor devices (e.g., resistors, diodes, capacitors, etc.), collectively referred to as complementary metal-oxide-semiconductor circuit 134.

[0079] Figure 1 The semiconductor structure 100 includes a memory array region 130, in which an array of memory cells can subsequently be formed. The first exemplary structure also includes a peripheral region 132 in which metal wiring for the storage device array is provided. Generally, field-effect transistors 108 in the complementary metal-oxide-semiconductor circuit 134 are electrically connected to electrodes of respective memory cells via metal interconnects.

[0080] The devices in the peripheral region 132 (such as field-effect transistor 108) provide functionality for the subsequent formation of an array of memory cells. Specifically, the devices in the peripheral region are configured to control programmed operations, erase operations, and sensing (read) operations of the memory cell array. For example, the devices in the peripheral region include sensing circuitry and / or programming circuitry in some embodiments.

[0081] One or more field-effect transistors 108 in the complementary metal-oxide-semiconductor (CMOS) circuit 134 include a channel region 114, which comprises a portion of a semiconductor material layer 104 in the substrate 102. If the semiconductor material layer 104 comprises a single-crystal semiconductor material such as single-crystal silicon, the channel region 114 of each CMOS transistor 108 in the CMOS circuit 134 includes a single-crystal semiconductor channel such as a single-crystal silicon channel. In one embodiment, the plurality of CMOS transistors 108 in the CMOS circuit 134 include separate nodes subsequently electrically connected to the nodes of separate memory cells for subsequent formation. For example, the plurality of CMOS transistors 108 in the CMOS circuit 134 include separate source regions 110 or separate drain regions 112, which are subsequently electrically connected to the nodes of separate memory cells for subsequent formation.

[0082] In one embodiment, the complementary metal-oxide-semiconductor circuit 134 includes a programmable control circuit configured to control the gate voltage of a set of field-effect transistors 108 used for programming individual memory cells (e.g., ferroelectric memory cells) and to control the gate voltage of transistors (e.g., thin-film transistors) subsequently formed. In this embodiment, the programmable control circuit is configured to provide a first programmed pulse for programming individual ferroelectric dielectric layers in selecting a ferroelectric memory cell into a first polarization state at a plurality of ferroelectric dielectric layer points toward a first electrode of the selected ferroelectric memory cell, and to provide a second programmed pulse for a second polarization state at a plurality of ferroelectric dielectric layer points toward a second electrode of the selected ferroelectric memory cell.

[0083] According to one embodiment, a field-effect transistor 108 is then electrically connected to a drain electrode and a gate electrode of an access transistor, and includes a semiconductor metal oxide disk formed on the field-effect transistor 108. In one embodiment, a subset of the field-effect transistor 108 is then electrically connected to at least one of the drain electrode and the gate electrode. For example, the field-effect transistor 108 includes a first word line driver configured to apply a first gate voltage to a first subset of the first word line through a lower-level metal interconnect to be formed, and a second word line driver configured to apply a second gate voltage to a second subset of the second word line through a lower-level metal interconnect to be formed. Furthermore, the field-effect transistor 108 includes a bit line driver configured to apply a bit line bias to a bit line to be formed, and a sense amplifier configured to detect electrical current passing through during a bit read operation.

[0084] Various metal interconnect structures formed within the dielectric material layer are then formed on the substrate 102 and the mentioned semiconductor device (e.g., field-effect transistor 108). In the illustrated example, the dielectric material layer includes, for example, a first dielectric material layer 136, which surrounds a first interconnect level dielectric material layer 138 and a second interconnect level dielectric material layer 140 connected to the source or drain (sometimes meaning such as a contact level dielectric material layer). The metal interconnect structures include a device contact via structure 142 formed in the first dielectric material layer 136, which contacts various elements of the complementary metal-oxide-semiconductor circuit 134; a first metal line structure 144 formed in the first interconnect level dielectric material layer 138; a first metal via structure 146 formed in the lower portion of the second interconnect level dielectric material layer 140; and a second metal line structure 148 formed in the upper portion of the second interconnect level dielectric material layer 140.

[0085] The dielectric material layers (136, 138, 140) comprise dielectric materials such as undoped silicon glass, doped silicon glass, organosilicon glass, amorphous fluorinated carbon, porous variants thereof, or compositions thereof. Each metal inlay structure (142, 144, 146, 148) comprises at least one conductive material, which in some embodiments is a composition of a metal pad (such as a metal nitride or metal carbide) and a metal filler material. Each metal pad comprises at least one of titanium nitride, tantalum nitride, tungsten nitride, titanium carbide, tantalum carbide, and tungsten carbide, and each metal filler material portion comprises at least one of tungsten, copper, aluminum, cobalt, ruthenium, molybdenum, tantalum, titanium, and titanium nitride, and in some embodiments, is an alloy of them and / or a composition thereof.

[0086] Other suitable metal pads and metal fillers within the intended disclosure range may also be used. In one embodiment, the first metal through-hole structure 146 and the second metal wire structure 148 are formed, such as an integrated wire and through-hole structure, by a dual damascene process. The dielectric material layers (136, 138, 140) herein refer to the underlying dielectric material layer. The metal interconnect structures (142, 144, 146, 148) formed within the underlying dielectric material layer refer to the underlying metal interconnect structures.

[0087] Although this disclosure is described using an embodiment in which memory cell arrays are formed on a second wire and through-hole level dielectric material layer 140, the embodiment explicitly envisions memory cell arrays being formed on different metal interconnect levels.

[0088] An array of thin-film transistors and an array of ferroelectric memory cells (or other types of semiconductor devices) are then formed on a dielectric material layer (136, 138, 140) of the metal interconnects (142, 144, 146, 148) formed thereon. All dielectric material layers formed prior to the formation of the array of thin-film transistors, ferroelectric memory cells, or other semiconductor devices generally refer to the lower dielectric material layer (136, 138, 140). A group of all metal interconnects formed within the lower dielectric material layers (136, 138, 140) refers to the first metal interconnect structure (142, 144, 146, 148). Generally, the first metal interconnect structure (142, 144, 146, 148) formed in at least one of the lower dielectric material layers (136, 138, 140) is formed on a semiconductor material layer 104 located in the substrate 102.

[0089] According to one embodiment, a thin-film transistor or other semiconductor device is then formed in a metal interconnect layer, which covers the metal interconnect layer including a lower dielectric material layer (136, 138, 140) and a first metal interconnect structure (142, 144, 146, 148). In one embodiment, a panel dielectric material layer having an average thickness is formed on top of the lower dielectric material layer (136, 138, 140). Here, the panel dielectric material layer is referred to as an insulating matrix layer 150. The insulating matrix layer 150 includes a dielectric material such as undoped silicon glass, doped silicon glass, organosilicon glass, or porous dielectric material, and in some embodiments, is deposited by chemical vapor deposition. The thickness of the insulating matrix layer 150 is in the range of 20 nanometers (i.e., 200 angstroms) to 300 nanometers (i.e., 300 angstroms), although thicknesses less or greater than this are also used.

[0090] In some embodiments, the inner-layer dielectric layer (such as the lower dielectric material layer (136, 138, 140)) includes a metal interconnect structure (such as a first metal interconnect structure (142, 144, 146, 148)) formed on the semiconductor device. An insulating matrix layer 150 is formed on the inner-layer dielectric layer. In addition to other active devices formed subsequently, passive devices are also formed in the back-end process (BEOL). For example, various capacitors, inductors, resistors, and integrated passive devices are used through other back-end process devices.

[0091] Figure 2 This is a vertical cross-sectional view of intermediate structure 200, which, according to various embodiments, can be used in the formation of semiconductor devices. Intermediate structure 200 includes a substrate 202 formed in subsequent process steps. Therefore, substrate 202 is a dielectric layer (e.g., from...) Figure 1 Inner dielectric or insulating matrix layer 150).

[0092] Substrate 202 includes, for example, undoped silicon glass, doped silicon glass (e.g., deposited by decomposition of tetraethyl orthosilicate (TEOS), organosilicon glass, silicon oxynitride, or silicon carbonitride. Other dielectric materials are within the scope of the intended disclosure. The dielectric material of substrate 202 is deposited by conformal deposition processes (e.g., chemical vapor deposition) or self-planarization deposition processes (e.g., spin coating). In some embodiments, the thickness of substrate 202 ranges from approximately 15 nanometers to approximately 60 nanometers, and in other embodiments, it ranges from approximately 20 nanometers to approximately 40 nanometers, although thicknesses smaller or larger may also be used.

[0093] Figure 2 Structure 200 further includes an etch stop layer 204 and a first inner dielectric layer 206. The etch stop layer 204 includes an etch stop material, such as silicon nitride, silicon carbide, silicon nitride carbide, or a dielectric oxide metal, such as aluminum oxide, titanium oxide, tantalum oxide, etc. The etch stop layer 204 is deposited by conformal or non-conformal deposition processes. In one embodiment, the etch stop layer 204 is deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). In some embodiments, the thickness of the etch stop layer 204 ranges from approximately 2 nanometers to approximately 20 nanometers, and in other embodiments from approximately 3 nanometers to 12 nanometers, although thicknesses smaller or larger are also possible.

[0094] The first inner dielectric layer 206 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, tantalum hafnium oxide, hafnium titanium oxide, zirconium hafnium oxide, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-aluminum oxide, or various other insulating structures. The first inner dielectric layer 206 is deposited by any suitable technique, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), etc.

[0095] In this example, the first inner dielectric layer 206 is formed as a planar overlay (i.e., unpatterned) layer having a planar top surface and a planar bottom surface. Additional portions of the first inner dielectric layer 206 are removed from the upper surface of the intermediate structure 200 by a planarization process, for example, by chemical mechanical planarization (CMP). In some embodiments, the thickness of the first inner dielectric layer 206 ranges from approximately 5 nanometers to approximately 50 nanometers, and in other embodiments from approximately 20 nanometers to 40 nanometers, although embodiments include thicknesses less than or greater.

[0096] Additional semiconductor devices, such as thin-film transistors (TFTs), can then be formed in or on the first inner dielectric layer 206. TFTs composed of semiconductor oxide are an attractive option for back-end process (BEOL) integration because they are fabricated at low temperatures, thus avoiding damage to previously manufactured devices. For example, the fabrication conditions and techniques may not disrupt previously manufactured front-end process (FEOL) and middle-end process (MEOL) devices. TFT-based circuits may also include other components fabricated in back-end processes, such as capacitors, inductors, resistors, and integrated passive devices.

[0097] Various semiconductor oxides can be used to form thin-film transistors, such as, but not limited to, inorganic silicon, indium gallium zinc oxide, indium gallium oxide, indium tungsten indium oxide, zinc indium oxide, indium tin oxide, zinc oxide, gallium oxide, indium oxide, and alloys thereof. Other suitable semiconductor materials are within the scope of disclosure. For example, in various embodiments, the semiconductor oxide layer 602L may comprise In… x Ga y Zn z MO is a composition given where 0 ≤ x ≤ 1; 0 ≤ y ≤ 1; 0 ≤ z ≤ 1; and M is one of titanium, aluminum, silver, cerium, and tin. Such oxide semiconductor materials can be produced by any suitable method such as atomic layer deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, etc.

[0098] According to the comparative implementation method, Figure 3A This is a top view of semiconductor device 300 and Figure 3B yes Figure 3A A vertical cross-sectional view of the semiconductor device 300. Definition Figure 3B The vertical plane of the vertical cross-section view is through Figure 3A The cross-section is marked B-B'. Semiconductor device 300 is a transistor structure including a source region 110, a drain region 112, and a channel region 114 branching from the drain region 112 to the source region 110. (As shown...) Figure 3A and 3B As shown, source region 110, drain region 112, and channel region 114 are each formed on substrate 302 (e.g., see...). Figure 3B ) and from each other along the first direction (that is, in Figure 3A (The y-direction setting in the text).

[0099] According to some embodiments, substrate 302 is a semiconductor substrate, such as... Figure 1 The substrate 102 and the semiconductor device 300 are formed in a front-end process. Alternatively, in other embodiments, the substrate 302 is an inner dielectric layer, such as... Figure 2The first inner dielectric layer 206 and the semiconductor device 300 are formed in a subsequent process. The source region 110 is electrically connected to the source electrode 304, and the drain region 112 is electrically connected to the drain electrode 306. Each of the source electrode 304 and drain electrode 306 is electrically connected to a metal interconnect structure (142, 144, 146, 148), which is formed in various dielectric material layers (136, 138, 140). Reference Figure 1 As described above.

[0100] like Figure 3B As shown, the semiconductor device 300 also includes insulating structures (308a, 308b) formed in the substrate 302, including a first portion 308a and a second portion 308b located on opposite sides of the channel region 114 along a second direction (i.e., the x-direction), the second direction being perpendicular to the first direction (i.e., the y-direction). In this example, the insulating structures (308a, 308b) are illustrated as shown in the reference diagram. Figure 1 The shallow trench insulation structures (106a, 106b) described above are shown. Various other structures (not shown) can be used in other embodiments. For example, other insulation structures include localized silicon oxide (LOCOS) structures, deep trench insulation structures (DTI), etc.

[0101] The semiconductor device 300 also includes a gate dielectric 118 formed on the channel region 114 and a gate electrode 120 formed on the gate dielectric 118. For simplicity, only the gate dielectric 118 and the gate electrode 120 are shown. Figure 3A and 3B In other implementations (i.e.) Figure 1 The semiconductor device 300 also includes a gate cap dielectric 122, a dielectric gate spacer 124, etc. The gate electrode 120 is electrically connected to a gate contact 310, which is electrically connected to a metal interconnect structure (142, 144, 146, 148). The metal interconnect structure (142, 144, 146, 148) is formed on various dielectric material layers (136, 138, 140), as described above. Figure 1 .

[0102] like Figure 3BAs shown, the channel region 114 includes a central portion 114a, a first end 114b, and a second end 114c, with the first end 114b and the second end 114c spaced apart from each other along a second direction (i.e., the x-direction) through the central portion 114a. For a specific electrostatic potential (i.e., voltage) applied to the gate electrode 120, a non-uniform electric field distribution is formed in the channel region 114. This is because the electric field has a larger quantity at the individual ends (114b, 114c) of the channel region 114 relative to the central portion 114a of the channel region 114, due to the discontinuous material properties between the two ends (114b, 114c) of the channel region 114 and the individual portions (308a, 308b) of the insulating structure (308a, 308b). Thus, for a specific electrostatic potential applied to the gate electrode 120, a non-uniform electric field distribution is formed in the channel region 114. Thus, the charge carriers at both ends (114b, 114c) of channel region 114 have a higher carrier density and a correspondingly lower resistance compared to the charge carriers in the central portion 114a. This non-uniform carrier density causes irregularities in the current-voltage distribution of the element, as described in more detail below. Figure 4A and Figure 4B Reference.

[0103] According to the comparative implementation method, Figure 4A This is a vertical cross-sectional view of a semiconductor device 400a showing channel region 114 and insulating structures (308a, 308b), and Figure 4B Is for Figure 4A A schematic current-voltage diagram of a semiconductor device, 400b. Figure 4A As shown, there are discontinuous material properties between the two ends (114b, 114c) of the channel region 114 and between individual portions (308a, 308b) of the insulating structure (308a, 308b). Thus, the electric field distribution (not shown) in the channel region 114 develops into a non-uniform spatial distribution.

[0104] For example, the fringing field develops at the corners of the adjacent insulating structures (308a, 308b). For applications applied to the gate electrode 120 (see...) Figure 3A and 3B A specific voltage is applied to the edge electric field, resulting in a larger electric field strength at the two ends (114b, 114c) of the channel region 114 compared to that at the central portion (114a) of the channel region 114. Thus, the source-drain current Isd caused by the applied gate voltage Vg can explain the sum of the first current 402a with respect to the charge carriers at the two ends (114b, 114c) of the channel region 114 and the second current 402b with respect to the carrier current at the central portion (114a) of the channel region 114. Figure 4BAs shown, the first current 402a is characterized by a first threshold voltage VTa that is less than the second threshold voltage VTb of the second current 402b. The two thresholds (VTa, VTb) lead to undesirable device performance, especially in intermediate to high voltage applications, resulting in a "double peak source" as illustrated and described above. Figure 4B .

[0105] Explaining the “double peak” characteristic of the current-voltage relationship, the disclosed embodiment provides that the gate dielectric 118 in the semiconductor device structure (500, 600, 700, 800, 900, 1000) has a composition that varies along a second direction (i.e., the x-direction) such that at least one of the work function or dielectric constant has a first value above the central portion 114a of the channel region 114 and a second value above the first end 114b and the second end 114c of the channel region 114.

[0106] When adjusting the threshold voltage of a semiconductor device, both the dielectric constant and work function of the gate material are relevant considerations, although their relative importance varies depending on the specific device requirements and performance targets. The dielectric constant of the gate dielectric directly affects the gate capacitance, which in turn affects the threshold voltage. High-dielectric materials, typically meaning high-k dielectrics, do not allow for increased capacitance without requiring a substantial increase in thickness, thus reducing the threshold voltage. This is particularly important in modern semiconductor manufacturing, where high-k materials replace traditional silicon dioxide gate dielectrics.

[0107] Conversely, the work function of the gate dielectric determines the energy barrier for carrier injection into the semiconductor channel. Adjusting the work function directly affects the threshold voltage by influencing the ease with which the carrier is attracted into the channel. Thus, a larger work function increases the threshold voltage. Device design can be optimized to achieve the ideal threshold voltage by balancing the dielectric constant and work function adjustment, while considering factors such as leakage current, reliability, and manufacturing feasibility. Finally, it is emphasized that the choice between the dielectric constant and the work function depends on specific operating constants and the performance objectives of the semiconductor device.

[0108] According to various implementation methods Figure 5A This is a top view of a semiconductor device 500 having two gate dielectric materials (118a, 118b). Figure 5B yes Figure 5A A vertical cross-sectional view of a semiconductor device. Definition Figure 5B The vertical plane of the profile passes through Figure 5A The section B-B' is marked in the diagram. For example... Figure 5A and 5B As shown, the semiconductor device 500 includes a substrate 302, a source region 110, a drain region 112, and a channel region 114 branching from the drain region 112 to the source region 110, each of which is formed on the substrate 302 and offset from each other along a first direction (i.e., the y-direction).

[0109] Semiconductor device 500 also includes gate dielectrics (118a, 118b) formed on channel region 114 and a second dielectric material 118b having a second dielectric constant. This is to increase the first threshold voltage VTa and / or decrease the second threshold voltage VTb (e.g., see...). Figure 4B The second dielectric constant is chosen to be less than the first dielectric constant. This is described above, whereby the threshold voltage is approximately reduced by increasing the dielectric constant and approximately increased by decreasing the dielectric constant, as described in more detail below.

[0110] The semiconductor device 500 also includes insulating structures (308a, 308b) formed on a substrate, including a first portion 308a and a second portion 308b located on opposite sides along a second direction (i.e., the x direction) perpendicular to the first direction (i.e., the y-direction). In this embodiment, the insulating structures (308a, 308b) are formed as shallow trench insulating structures (106a, 106b). In other embodiments, the insulating structures (308a, 308b) are formed as silicon local oxidation technology structures (602a, 602b), see reference. Figure 6A and 6B A more detailed explanation follows.

[0111] like Figure 5A and 5B As shown, the first dielectric material 118a is located on the central portion 114a of the channel region 114 and on the second end 114c of the channel region 114. Figure 5B As shown, the first end 114b and the second end 114c are separated from each other along the second direction (i.e., the x-direction) through the central portion 114a of the channel region 114. Figure 5A As shown, the first dielectric material 118a has a first width Wa and the second dielectric material 118b has a second width Wb. The Wa / Wb ratio can be selected based on the spatial distribution of the edge electric field in the central portion 114a and the two end portions (114c, 114b) of the channel region 114. For example, in a particular embodiment, the first width Wa is between approximately 70% and 90% of the total width Wa+Wb. In other embodiments, Wa is between approximately 75% and 85% of the total width Wa+Wb. Similarly, in some embodiments, the second width Wb is between approximately 10% and 30% of the total width Wa+Wb and between approximately 15% and 25% of the total width Wa+Wb.

[0112] By appropriately selecting the first dielectric material 118a and the second dielectric material 118b, the first threshold voltage VTa and the second threshold voltage VTb can be adjusted to match or approximately match, thus eliminating or reducing the... Figure 4BThe “double peak” characteristic is shown. The threshold voltage of this metal-oxide-semiconductor field-effect transistor (MOSFET) depends on the dielectric constant K and the thickness tox of the gate dielectric, according to the following equation.

[0113]

[0114] Here:

[0115] V th Threshold voltage of a metal-oxide-semiconductor field-effect transistor

[0116] V FB Flat band voltage

[0117] φ B Volume potential (or Fermi potential)

[0118] q: Elementary charge (approximately 1.602 × 10⁻⁶) -19 C)

[0119] K ε Relative permittivity of semiconductors

[0120] ε0: Free space permittivity (approximately 8.854 × 10⁻⁶) -12 F / m)

[0121] N A Doping concentration in semiconductors

[0122] T ox Thickness of the gate dielectric layer

[0123] K: Relative permittivity of the gate dielectric (dielectric constant)

[0124] Therefore, from Eq(1), the dielectric constant K of the gate dielectric layer causes a decrease at the threshold voltage V. th In this equation, it exhibits an inverse dependence on K in the third term of Eq(1). Similarly, from Eq(1), increasing the gate dielectric layer thickness tox causes an increase in the threshold voltage V. th In this context, the thickness t of the gate dielectric layer varies with the third term of Eq(1). ox The dependence increases by the square root of the first gate dielectric layer 118a and the second gate dielectric layer 118b. For the specific material selection of the first gate dielectric layer 118a and the second gate dielectric layer 118b, Eq(1) can be used with design optimization devices by replacing the thickness t. ox And the relative value of the dielectric constant K to reduce the difference in threshold voltage.

[0125] Equation (1) can be used for accurate prediction when all the listed variables are known. For many embodiments, experimental results indicating a threshold voltage difference of 10% or greater (e.g., VTa-VTb) can be reduced by a dielectric constant difference of 20% or greater (Ka-Kb). Similarly, in various embodiments, a threshold voltage difference of 10% or greater (VTa-VTb) can be reduced by the thickness of the first dielectric layer 118a and a second dielectric layer of 6.5% or greater.

[0126] As described above, the first threshold voltage VTa and the second threshold voltage VTb are adjusted to match each other, the first dielectric material 118a is selected to have a relatively high dielectric constant and the second dielectric material 118b is selected to have a relatively low dielectric constant. For example, the first dielectric material 118a may be selected as a high-k dielectric material such as one or more hafnium oxides, hafnium lanthanum oxide, hafnium silicon oxide, tantalum hafnium oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, and hafnium dioxide-alumina. Similarly, the second dielectric material 118b may be selected as a lower dielectric material such as silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, and silicon carbide.

[0127] Besides the dielectric constant of the gate dielectrics (118a, 118b), various other geometric properties, such as thickness (as described above), affect the values ​​of the first threshold voltage VTa and the second threshold voltage VTb. Furthermore, the spatial extent of the first dielectric materials 118a and 118b can be adjusted to control the values ​​of the first threshold voltage VTa and the second threshold voltage VTb. For example, as... Figure 5A and 5B As shown, the second dielectric material extends over the respective edges of the first end 114b and the second end 114c of the channel region 114, such that the second dielectric material 118b is partially located in the first portion 308a and the second portion 308b of the insulating structure (308a, 308b).

[0128] Alternatively, in other embodiments, the first dielectric material 118a and the second dielectric material 118b are formed not to overlap with the insulating structure (308a, 308b). The selection of the first dielectric material 118a, the second dielectric material 118b, and the various thicknesses of the materials, as well as the spatial extent of the gate dielectric (118a, 118b), can be optimized using numerical simulations to determine the device attributes based on the specific application.

[0129] The semiconductor device 500 described above is a planar device that can be formed in front-end or back-end engineering operations. Other structures, such as FinFET devices, gate-enclosed-area (GAA) devices, 2D material devices, and back-film transistor devices, may also include a gate dielectric with a position-varying composition. As described above, the gate electrode 120 may include metals, polysilicon, or other conductive materials and may include various dopants such as nitrogen, phosphorus, arsenic, tin, bismuth, oxygen, sulfur, selenium, tellurium, fluorine, chlorine, bromine, iodine, boron, aluminum, gallium, indium, titanium, tantalum, and silicon. The source and drain regions may also include various dopants such as nitrogen, phosphorus, arsenic, tin, bismuth, oxygen, sulfur, selenium, tellurium, fluorine, chlorine, bromine, iodine, boron, aluminum, gallium, indium, titanium, tantalum, and silicon.

[0130] According to various implementation methods Figure 6A This is a top view of a semiconductor device 600 having two gate dielectric materials (118a, 118b). Figure 6B yes Figure 6A A vertical cross-sectional view of a semiconductor device. Definition Figure 6B The vertical plane of the cross-sectional view passes through Figure 6A The section B-B' is indicated in the diagram. Semiconductor device 600 includes features of multiple semiconductor devices 500, excluding insulating structures (308a, 308b). For example... Figure 6B As shown, the insulating structures (308a, 308b) are formed as in the silicon local oxidation technique structures (602a, 602b).

[0131] The silicon local oxidation technology structures (602a, 602b) are formed as follows. The process begins with a silicon substrate (302, 102) on a layer of silicon nitride deposited (in the previous process). This nitride layer acts as an oxide mask, shielding the silicon from specific areas of oxidation. Using a photomask, photoresist is applied and exposure is performed through the mask to define the oxidation pattern. The exposed nitride is then etched away to expose the silicon areas designed for oxidation. Once the substrate is ready, it is placed in an oxidation furnace, where the exposed silicon is oxidized to form silicon dioxide.

[0132] This oxide grows upwards and laterally, penetrating the silicon substrate. This characteristic "beak" shape is a prominent feature in the process, formed by the oxidation diffusion at the edges of the nitride. After the oxidation step, the silicon nitride mask is removed, leaving the silicon oxide. This oxide acts as an insulator, defining active regions and insulating elements to improve device performance and reduce electronic interference. The silicon local oxidation (SNO) process effectively insulates active elements (e.g., source region 110, channel region 114, and drain region 112) on the wafer, although the beak effect consumes additional space, which is detrimental to high-scale integrated circuits. However, for specific applications, the SNO structures (602a, 602b) are advantageous in providing the material properties of channel region 114 and a smoother spatial transition between insulating materials (308a, 308b). This allows for a smoother spatial dependence of the electric field distribution, resulting in less of the "dual-peak source" effect when using the SNO structures (602a, 602b) in certain embodiments.

[0133] After the silicon local oxidation technology structure (602a, 602b) is formed, the gate dielectric (118a, 118b) is deposited and patterned, and the gate 120 (e.g., metal or polysilicon) is then formed on the gate dielectric (118a, 118b). Figure 6B As shown, the gate dielectric (118a, 118b) and gate 120 are no longer planar structures, as... Figure 5B The state of the semiconductor device 500, the electric field distribution in the channel region 114 (not shown) is different from that occurring in... Figure 5A and 5B The semiconductor device 500 can have different configurations. Thus, the different geometries result from the use of silicon local oxidation technology structures (602a, 602b), rather than... Figure 5B The shallow trench insulation structures (106a, 106b) lead to different design considerations, taking into account the selection of gate dielectric (118a, 118b) materials, thickness, width, etc.

[0134] According to various implementation methods Figure 7A This is a top view of a semiconductor device 700 having three gate dielectric materials (118a, 118b, 118c), and Figure 7B yes Figure 7A A vertical cross-sectional view of a semiconductor device. Definition Figure 7B The vertical plane of the cross-sectional view passes through Figure 7A The section B-B' is marked in the diagram. For example... Figure 7A and 7BAs shown, the semiconductor device 700 includes a substrate 302, a source region 110, a drain region 112, and a channel region 114 branching from the drain region 112 to the source region 110, each of which is formed in the substrate 302 and offset from each other along a first direction (i.e., the y-direction).

[0135] The semiconductor device 500 also includes a gate dielectric (118a, 118b, 118c) formed on the channel region 114 and comprising a first gate dielectric material 118a having a first dielectric constant, a second gate dielectric material 118b having a second dielectric constant, and a third gate dielectric material 118c having a third dielectric constant. The first, second, and third dielectric constants are different from each other. The use of three dielectric constants allows for greater flexibility to fine-tune the spatial variability of the dielectric material properties. For example, the three dielectric materials have dielectric constants (Ka, Kb, Kc) that satisfy Ka ≥ Kb ≥ Kc. In some embodiments, for example, the dielectric constants are in the ranges 25 ≤ Ka ≤ 30; 15 ≤ Kb ≤ 20; and 5 ≤ Kc ≤ 10.

[0136] like Figure 7A As shown, the third dielectric material 118c is partially located on the first end 114b and the second end 114c of the channel region 114 adjacent to the second dielectric material 118b. In this regard, the second dielectric material 118b and the third dielectric material 118c are located adjacent to each other along the edge of the channel region 114, and are offset from each other on each side of the channel region 114 along the first direction (i.e., the y-direction).

[0137] Various other geometric arrangements of the first dielectric material 118a, the second dielectric material 118b, and the third dielectric material 118c are also within the scope of this disclosure. For example, in other embodiments (not shown), the second dielectric material 118b and the third dielectric material 118c are formed adjacent to each other along one edge of the channel region 114 (i.e., along the edge of the first end 114b), although only a single dielectric material (i.e., one of the first dielectric material 118a, the second dielectric material 118b, or the third dielectric material 118c) is formed along the edge of the second end 114c of the channel region 114. As in other embodiments disclosed herein, numerical simulations can be performed to determine the optimal selection of the material, thickness, width, relative placement, etc., of the gate dielectrics (118a, 118b, 118c).

[0138] According to various implementation methods Figure 8A This is a top view of a semiconductor device 800 having three gate dielectric materials (118a, 118b, 118c). Figure 8B yes Figure 8A A vertical cross-sectional view of a semiconductor device. Definition Figure 8B The vertical plane of the vertical cross-section view is through Figure 8AThe section B-B' is indicated in the diagram. Semiconductor device 800 includes many features of semiconductor device 700, except for the insulating structures (308a, 308b). For example... Figure 8B As shown, the insulating structures (308a, 308b) are formed as in the silicon local oxidation technology structures (602a, 602b).

[0139] After the silicon local oxidation technology structure (602a, 602b) is formed, the gate dielectric (118a, 118b, 118c) is deposited and patterned, and the gate 120 (e.g., metal or multi-silicon) is then formed on top of the gate dielectric (118a, 118b, 118c). Figure 6B As shown, the gate dielectric (118a, 118b, 118c) gate 120 is no longer a planar structure, but... Figure 7B The semiconductor device 700 is present. Thus, the electric field distribution (not shown) in the channel region 114 can be compared to that occurring in... Figure 7A and 7B The semiconductor device 700 in the middle has different configurations. Thus, different geometries result from the use of silicon local oxidation technology structures (602a, 602b), rather than... Figure 7B The shallow trench insulation structures (106a, 106b) lead to different design considerations, taking into account the selection of gate dielectric (118a, 118b, 118c) materials, thickness, width, etc.

[0140] According to various implementation methods Figure 9A The top view of semiconductor device 900 with four dielectric materials (118a, 118b, 118c, 118d) is shown. Figure 9B yes Figure 9A A vertical cross-sectional view of a semiconductor device. Definition Figure 9B The vertical plane of the vertical cross-section view is through Figure 9A The section B-B' is marked in the diagram. For example... Figure 9A and 9B As shown, the semiconductor device 900 includes a substrate 302, a source region 110, a drain region 112, and a channel region 114 branching from the drain region 112 to the source region 110, each formed on the substrate 302 and offset from each other along a first direction (i.e., the y-direction). The use of four dielectric constants allows for greater flexibility to fine-tune spatial variations in the dielectric material properties; conversely, the use of four dielectric constants allows for tuning Vt to have a wider tunable range. In various embodiments, the four materials have dielectric constants (Ka, Kb, Kc, Kd) that satisfy Ka ≥ Kb ≥ Kc ≥ Kd. For example, the dielectric constant values ​​can be in the ranges of 30 ≤ Ka ≤ 80; 25 ≤ Kb ≤ 30; 15 ≤ Kc ≤ 20; and 5 ≤ Kd ≤ 10.

[0141] The semiconductor device 900 further includes gate dielectrics (118a, 118b, 118c, 118d) formed on the channel region 114 and includes a first dielectric material 118a having a first dielectric constant, a second dielectric material 118b having a second dielectric constant, a third dielectric material 118c having a third dielectric constant, and a fourth dielectric material 118d having a fourth dielectric constant. The first, second, third, and fourth dielectric constants are different from each other. Figure 9B As shown, the second dielectric material 118b and the third dielectric material 118c are partially located on the first end 114b of the channel region 114, and the fourth dielectric material 118d is located on the second end 114c of the channel region 114. Furthermore, the second dielectric material 118b and the third dielectric material 118c are adjacent to each other along the edge of the first end 114b of the channel region 114 and are offset from each other along the first direction (i.e., the y-direction).

[0142] Various other geometric arrangements of the first dielectric material 118a, the second dielectric material 118b, the third dielectric material 118c, and the fourth dielectric material 118d are also within the scope of this disclosure. As in other embodiments, numerical simulations can be performed to determine the optimal selection of the material, thickness, width, relative placement, etc., of the gate dielectrics (118a, 118b, 118c, 118d).

[0143] According to various implementation methods Figure 10A The top view shows a semiconductor device 1000 with four dielectric materials (118a, 118b, 118c, 118d). Figure 10B yes Figure 10A A vertical cross-sectional view of a semiconductor device. Definition Figure 10B The vertical plane of the vertical cross-section view is through Figure 10A The section B-B' is indicated in the diagram. Semiconductor device 1000 includes features of multiple semiconductor devices 900, excluding insulating structures (308a, 308b). For example... Figure 10B As shown, the insulating structures (308a, 308b) are formed as in the silicon local oxidation technology structures (602a, 602b).

[0144] After the silicon local oxidation technology structure (602a, 602b) is formed, the gate dielectric (118a, 118b, 118c, 118d) is deposited and patterned, and the gate 120 (e.g., metal or multi-silicon) is then formed on top of the gate dielectric (118a, 118b, 118c, 118d). Figure 6B As shown, the gate dielectric (118a, 118b, 118c, 118d) and gate 120 are no longer planar structures, but have... Figure 9B Given the condition of the semiconductor device 900, the electric field distribution (not shown) in the channel region 114 is different from that occurring in... Figure 9A and9B The semiconductor device 900 can have different configurations. Thus, the different geometries result from the use of silicon local oxidation technology structures (602a, 602b), rather than... Figure 9B The shallow trench insulation structures (106a, 106b) lead to different design considerations, taking into account the selection of gate dielectric (118a, 118b, 118c, 118d) materials, thickness, width, etc.

[0145] Semiconductor device structures (500, 600, 700, 800, 900, 1000) are shown to have gate dielectrics (118, 118a, 118b, 118c, 118d) where the composition of the gate dielectric varies discontinuously from one dielectric material to another (e.g., from the first dielectric material 118a to the second dielectric material 118b, etc.). However, in other embodiments (not shown), the gate dielectric material is formed to have a composition that varies continuously along a second direction (i.e., the x-direction), thus creating a smooth composition gradient. Furthermore, the embodiments described above indicate that the gate dielectric material is selected to have a specific value for the dielectric constant. The work function of the gate dielectric is also a relevant consideration and can be selected to optimize the current-voltage characteristics of the semiconductor device (500, 600, 700, 800, 900, 1000).

[0146] As described above, the relationship between the gate dielectric work function and the threshold voltage of a semiconductor device is a key variable in understanding its operation. The threshold voltage represents the voltage level at which a transistor begins to conduct current between its source and drain. The threshold voltage is influenced by various factors, among which the gate dielectric work function has a significant impact. The work function determines the energy barrier for electrons injected from the gate electrode into the semiconductor channel. When the work function of the gate material matches that of the semiconductor material, the threshold voltage is typically lower, allowing for easier electron injection and thus requiring a lower voltage to turn on the transistor.

[0147] Conversely, if the work function of the gate dielectric differs significantly from that of the gate material of the semiconductor, the threshold voltage increases. Therefore, by selecting appropriate materials and compatible work functions for the gate electrode and semiconductor material, the threshold voltage of a semiconductor device can be precisely controlled to specifically tailor its performance to meet particular application requirements. This relationship underscores the importance of understanding and optimizing the work function of the gate dielectric 118 in the design and manufacture of semiconductor devices. The thickness of the gate dielectric 118 is also a relevant consideration.

[0148] The relationship between the work function of the gate dielectric and its thickness in semiconductor devices is complex and depends on several factors. As the thickness of the gate dielectric decreases, the work function can change due to quantum mechanical effects. When the gate dielectric is thicker, the influence of the semiconductor material on the work function of the gate electrode weakens, making the work function more consistent with the inherent properties of the gate material. However, as the gate dielectric becomes thinner, the quantum tunneling effect becomes more pronounced, leading to changes in the effective work function. Furthermore, the choice of gate dielectric material also affects this relationship; some materials exhibit a stronger dependence on thickness variations. Overall, understanding and controlling the relationship between the work function of the gate dielectric and its thickness is relevant to optimizing the performance of semiconductor devices, especially in the field of field-effect transistors (FETs) where precise control of the threshold voltage is required.

[0149] When the gate dielectric is sufficiently thick to mitigate quantum tunneling, the work function can remain relatively stable with increasing thickness. This stability stems from the reduced influence of quantum mechanical phenomena, as the thickness of the dielectric layer ensures a stronger insulating barrier between the gate electrode and the semiconductor channel. Therefore, the work function tends to be more consistent with the intrinsic properties of the gate material. However, this behavior may vary depending on specific material composition and fabrication techniques. Overall, in the absence of quantum tunneling, the work function of the gate dielectric tends to remain constant with increasing thickness.

[0150] According to various implementation methods Figure 11 This illustrates the operation of method 1100 for forming a semiconductor device (500, 600, 700, 800, 900, 1000). In operation 1102, method 1100 includes forming a source region 110, a drain region 112, and a channel region 114 branching from the drain region 112 to the source region 110, and misaligning the source region 110, the channel region 114, and the drain region 112 with respect to each other along a first direction (i.e., the y-direction). In operation 1104, method 1100 includes forming gate dielectrics (118a, 118b) over the channel region 114, such that the gate dielectrics (118a, 118b) include a first dielectric material 118a having a first dielectric constant and a second dielectric material 118b having a second dielectric constant, the second dielectric constant being smaller than the first dielectric constant.

[0151] In operation 1106, method 1100 includes an insulating structure (308a, 308b) formed in a substrate (102, 202, 302), such that the insulating structure (308a, 308b) includes a first portion 308a and a second portion 308b on opposite ends (114a, 114b) of the channel region 114 along a second direction (i.e., the x-direction), the second direction (i.e., the x-direction) being perpendicular to the first direction (i.e., the y-direction). According to operation 1108, in forming the gate dielectric (118a, 118b), method 1100 further includes a second dielectric material 118b formed on the central portion 114a of the channel region 114 and a first dielectric material 118a formed on the first end 114b and the second end 114c of the channel region 114, which are separated from each other along the second direction through the central portion 114a of the channel region 114.

[0152] According to operation 1104, in forming the gate dielectric (118a, 118b), in some embodiments, method 1100 further includes forming a second dielectric material 118b such that the edges of the first end 114b and the second end 114c of the extended channel region 114 are respectively located on the first portion 308a and the second portion 308b of the insulating structure (308a, 308b).

[0153] In some embodiments, during the formation of the gate dielectric (118a, 118b, 118c) according to operation 1104, method 1100 further includes forming the gate dielectric (118a, 118b) over the channel region 114, such that the gate dielectric (118a, 118b, 118c) includes a third dielectric material 118c having a third dielectric constant, the third dielectric constant being different from the first dielectric constant of the first dielectric material 118a and the second dielectric constant of the second dielectric material 118b. In some embodiments, during the formation of the gate dielectric (118a, 118b, 118c) according to operation 1104, method 1100 further includes forming the third dielectric material 118c over a portion of at least one of the first ends 114b or over the second end 114c of the channel region 114, such that the third dielectric material 118c is adjacent to the second dielectric material 118b. In some embodiments, during the formation of gate dielectrics (118a, 118b, 118c) according to operation 1104, method 1100 further includes a third dielectric material 118c formed on both the first end 114b and the second end 114c of the channel region 114, adjacent to the second dielectric material 118b.

[0154] In some embodiments, the formation of the gate dielectric (118a, 118b, 118c, 118d) according to operation 1104 includes a fourth dielectric material 118d having a fourth dielectric constant, the fourth dielectric constant being different from the dielectric constants of the first dielectric material 118a, the second dielectric material 118b, and the third dielectric material 118c. In some embodiments, the formation of the gate dielectric (118a, 118b, 118c, 118d) according to operation 1104, method 1100 further includes forming the first dielectric material 118a to include one or more hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, tantalum hafnium oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, and hafnium dioxide-alumina; and forming the second dielectric material 118b to include one or more silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, and silicon carbide.

[0155] According to various implementation methods Figure 12 This illustrates the operation of method 1200 for forming semiconductor devices (500, 600, 700, 800, 900, 1000). In operation 1202, method 1200 includes forming a source region 110, a drain region 112, and a channel region 114 in a substrate (102, 202, 302), such that the channel region 114 separates from the drain region 112 from the source region 110, and such that each of the source region 110, the channel region 114, and the drain region 112 is offset from each other along a first direction (i.e., the y-direction). In operation 1204, method 1200 includes forming a gate dielectric 118 on the channel region 114. The channel region 114 includes a component that varies along a second direction (i.e., the x-direction), which is perpendicular to the first direction (i.e., the y-direction), such that at least one of the work function or dielectric constant has a first value above the central portion 114a of the channel region 114 and a second value above the first end 114b and the second end 114c of the channel region 114, the first end 114b and the second end 114c of the channel region 114 being separated from each other along the second direction through the central portion 114a of the channel region 114. In operation 1206, method 1200 includes forming a gate electrode 120 over the gate dielectric 118.

[0156] In some embodiments, according to operation 1204, in forming the gate dielectric 118, method 1200 further includes a variation in the composition of the gate dielectric 118 to include a gradient that varies smoothly along a second direction. According to operation 1204, in forming the gate dielectric (118a, 118b), method 1200 includes forming a first dielectric material 118a over the central portion 114a of the channel region 114 and forming a second dielectric material 118b over the first end 114b and the second end 114c of the channel region 114, such that the composition of the gate dielectric 118 changes discontinuously from the first dielectric material 118a to the second dielectric material 118b.

[0157] In some embodiments, during the formation of the gate dielectric (118a, 118b) according to operation 1204, method 1200 further includes forming a first dielectric material 118a to have a first dielectric constant and forming a second dielectric material 118b to have a second dielectric constant, the second dielectric constant being less than the first dielectric constant. Alternatively, method 1200 may include forming a first dielectric material 118a to have a first work function and forming a second dielectric material 118b to have a second work function, the second work function being greater than the first work function. According to various embodiments, method 1200 further includes forming insulating structures (308a, 308b) in the substrate (102, 202, 302) such that the insulating structures (308a, 308b) include a first portion 308a and a second portion 308b, the first portion 308a and the second portion 308b being located on opposite sides of the channel region 114 along a second direction. According to operation 1204, in forming the gate dielectric (118a, 118b), method 1200 further includes forming a second dielectric material 118b extending over the edges of the first end 114b and the second end 114c of the channel region 114, such that the second dielectric material 118b is partially located over the first portion 308a and the second portion 308b of the insulating structure (308a, 308b).

[0158] Referring to all the accompanying drawings and various embodiments disclosed herein, semiconductor devices (500, 600, 700, 800, 900, 1000) are provided. According to some embodiments, the semiconductor device (500, 600, 700, 800, 900, 1000) includes a substrate (102, 202, 302), a source region 110, a drain region 112, and a channel region 114, the channel region 114 branching off from the drain region 112 to the source region 110, each formed on the substrate (102, 202, 302) and offset from each other along a first direction. Semiconductor devices (500, 600, 700, 800, 900, 1000) include gate dielectrics (118a, 118b) formed on a channel region 114. The channel region 114 includes a first dielectric material 118a having a first dielectric constant and a second dielectric material 118b having a second dielectric constant, the second dielectric constant being smaller than the first dielectric constant. Insulating structures (308a, 308b) are formed in a substrate (102, 202, 302). The insulating structures (308a, 308b) include a first portion 308a and a second portion 308b located on opposite sides of the channel region 114 along a second direction perpendicular to the first direction.

[0159] According to various embodiments, a first dielectric material 118a is located on the central portion 114a of the channel region 114, and a second dielectric material 118b is located on the first end 114b and the second end 114c of the channel region 114, the first end 114b and the second end 114c of the channel region 114 being separated from each other along a second direction through the central portion 114a of the channel region 114. According to other embodiments, the second dielectric material 118b further extends on the respective edges of the first end 114b and the second end 114c of the channel region 114, such that the second dielectric material 118b is partially located on the first portion 308a and the second portion 308b of the insulating structure (308a, 308b). According to a further embodiment, the gate dielectric (118a, 118b, 118c) further includes a third dielectric material 118c, which includes a third dielectric constant that is different from the dielectric constants of the first dielectric material 118a and the second dielectric material 118b.

[0160] According to various embodiments, a third dielectric material 118c is located at least a portion of the first end 114b and the second end 114c of the channel region 114 adjacent to the second dielectric material 118b. According to various embodiments, the third dielectric material 118c is partially located above the first end 114b and the second end 114c of the channel region 114 adjacent to the second dielectric material 118b. According to other embodiments, the gate dielectric 118 further includes a fourth dielectric material 118d having a fourth dielectric constant, which is different from the dielectric constants of the first dielectric material 118a, the second dielectric material 118b, and the third dielectric material 118c. In various embodiments, the first dielectric material 118a includes one or more hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, tantalum hafnium oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, and hafnium dioxide-alumina; and the second dielectric material 118b includes one or more silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, and silicon carbide.

[0161] The disclosed embodiments offer advantages over conventional semiconductor devices. In this regard, the semiconductor devices (500, 600, 700, 800, 900, 1000) include a gate dielectric (118, 118a, 118b, 118c, 118d) having a composition varying across the width of a channel region 114, such that at least one of the work function or dielectric constant has a first value at the central portion 114a of the channel region 114, and a second value at the first end 114b and the second end 114c of the channel region 114. The variation in the composition of the gate dielectric (118, 118a, 118b, 118c, 118d) compensates for the non-uniform electric field distribution within the channel region 114, thus resulting in a smooth current-voltage relationship, without the "double-peak source" present in other devices with gate dielectrics 118 having an average composition.

[0162] The disclosed embodiments include a method of forming a semiconductor device, comprising forming a source region, a drain region, and a channel region in a substrate, such that the channel region separates from the source region from the drain region, and such that each of the source region, channel region, and drain region is offset from each other along a first direction. The method further includes forming a gate dielectric over the channel region, such that the gate dielectric includes a first dielectric material having a first dielectric constant and a second dielectric material having a second dielectric constant less than the first dielectric constant; and forming an insulating structure in the substrate, such that the insulating structure includes a first portion and a second portion located at opposite ends of the channel region along a second direction perpendicular to the first direction. According to this method, forming the gate dielectric further includes forming a first dielectric material over a central portion of the channel region, and forming a second dielectric material over a first end and a second end of the channel region, the channel regions being separated from each other along the second direction through the central portion of the channel region.

[0163] In various embodiments, forming the gate dielectric also includes forming a second dielectric material extending over the respective edges of the first and second ends of the channel region, such that the second dielectric material partially lies over the first and second portions of the isolation structure. In other embodiments, forming the gate dielectric further includes forming a gate dielectric over the channel region, such that the gate dielectric includes a third dielectric material having a third dielectric constant different from the dielectric constants of the first and second dielectric materials. In various embodiments, forming the gate dielectric also includes forming a third dielectric material adjacent to the second dielectric material on a portion of at least one of the first or second ends of the channel region.

[0164] In various embodiments, forming the gate dielectric further includes forming a third dielectric material on a portion of at least one of the first or second ends of the channel region, adjacent to the second dielectric material. In various embodiments, forming the gate dielectric further includes forming a gate dielectric on the channel region such that the gate dielectric includes a fourth dielectric material having a fourth dielectric constant different from the dielectric constants of the first, second, and third dielectric materials. In various embodiments, forming the gate dielectric further includes forming a first dielectric material comprising one or more of hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, europium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, and hafnium dioxide-alumina; and forming a second dielectric material comprising one or more of silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, and silicon carbide.

[0165] Another embodiment of this disclosure is a method of forming a semiconductor device, including a source region, a drain region, and a channel region formed in a substrate, such that the channel region separates from the drain region from the source region, and that each of the source region, channel region, and drain region is offset from each other along a first direction. This method also includes a gate dielectric formed on the channel region, the gate dielectric including a composition varying along a second direction perpendicular to the first direction, such that at least one of a work function or a dielectric constant includes a first value on a central portion of the channel region and a second value on a first end and a second end of the channel region, which are separated from each other along the second direction through the central portion of the channel region; and a gate electrode formed on the gate dielectric.

[0166] In various embodiments, forming the gate dielectric further includes changing the composition of the gate dielectric to include a gradient that smoothly varies along a second direction. In other embodiments, forming the gate dielectric also includes forming a first dielectric material at the central portion of the channel region; and forming a second dielectric material at a first end and a second end of the channel region, such that the composition of the gate dielectric material changes discontinuously from the first dielectric material to the second dielectric material. In other embodiments, forming the gate dielectric further includes forming a first dielectric material having a first dielectric constant and forming a second dielectric material having a second dielectric constant less than the first dielectric constant. Alternatively, the first dielectric material may be formed to have a first work function, and the second dielectric material may be formed to have a second work function greater than the first work function.

[0167] In some embodiments, the method further includes an insulating structure formed in the substrate, such that the insulating structure includes a first portion and a second portion located on opposite sides of the channel region along a second direction. In other embodiments, forming the gate dielectric further includes forming a second dielectric material extending over the respective edges of the first and second ends of the channel region, such that a portion of the second dielectric material is located above the first dielectric material.

[0168] Another embodiment of this disclosure is a semiconductor device including a substrate, a source region, a drain region, and a channel region separating the source region from the drain region, each formed in the substrate and formed on the channel region along a first gate dielectric, and including a first dielectric material having a first dielectric constant and a second dielectric material having a second dielectric constant less than the first dielectric constant. The semiconductor device also includes an insulating structure formed in the substrate, the insulating structure including a first portion and a second portion located on opposite sides of the channel region along a second direction perpendicular to the first direction. The first dielectric material is located on the central portion of the channel region, and the second dielectric material is located on the first end and the second end of the channel region, the first end and the second end of the channel region being separated from each other along the second direction.

[0169] In various embodiments, a first dielectric material has a first width and a second dielectric material has a second width, the first width being between 70% and 90% of a total width, the total width being the sum of the first and second widths. In various embodiments, the second dielectric material further extends above the respective edges of a first end and a second end of the channel region, such that the second dielectric material partially lies over the first and second portions of the channel region. In other embodiments, the gate dielectric further includes a third dielectric material having a third dielectric constant different from the dielectric constants of the first and second dielectric materials. In other embodiments, the third dielectric material lies over a portion of at least one of the first or second ends of the channel region adjacent to the second dielectric material. In various embodiments, the third dielectric material partially lies over both the first and second ends of the channel region adjacent to the second dielectric material. In various embodiments, the gate dielectric further includes a fourth dielectric material having a fourth dielectric constant different from the dielectric constants of the first, second, and third dielectric materials.

[0170] In some embodiments, the first dielectric material includes one or more of hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium hafnium oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, and hafnium dioxide-alumina; the second dielectric material includes one or more of silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, and silicon carbide. The features of several embodiments outlined above enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized by comprising: include: One substrate; A source region, a drain region, and a channel region, wherein the channel region separates the source region from the drain region, each being formed in a substrate and separated from each other along a first direction; A gate dielectric is formed over the channel region and includes a first dielectric material and a second dielectric material, the first dielectric material including a first dielectric constant and the second dielectric material including a second dielectric constant, the second dielectric constant being smaller than the first dielectric constant; and An insulating structure is formed in the substrate, comprising a first portion and a second portion, the first portion and the second portion being located on multiple opposite sides of the channel region along a second direction perpendicular to the first direction. The first dielectric material is located on a central portion of the channel region and the second dielectric material is located on a first end and a second end of the channel region, the first end and the second end being separated from each other along the second direction through the central portion of the channel region.

2. The semiconductor device as claimed in claim 1, characterized in that, in: The first dielectric material includes a first width; The second dielectric material includes a second width; The first width is between 70% and 90% of the total width, and the total width is the sum of the first width and the second width.

3. The semiconductor device as claimed in claim 1, characterized in that, The second dielectric material extends over a plurality of respective edges of the first end of the channel region and over the second end of the channel region, such that the second dielectric material is partially located over the first and second portions of the insulating structure.

4. The semiconductor device as claimed in claim 1, characterized in that, The gate dielectric further includes a third dielectric material, which and the second dielectric material are located adjacent to each other along the edge of the channel region and offset from each other on each side of the channel region along the first direction.

5. The semiconductor device as claimed in claim 4, characterized in that, The third dielectric material is located on a portion of at least one of the first end or the second end of the channel region adjacent to the second dielectric material.

6. The semiconductor device as claimed in claim 4, characterized in that, The gate dielectric further includes a fourth dielectric material located above the second end of the channel region.

7. A semiconductor device, characterized in that, include: One substrate; A source region, a drain region, and a channel region, wherein the channel region separates the source region from the drain region, each being formed in a substrate and separated from each other along a first direction; A gate dielectric is formed over the channel region and includes a first dielectric material and a second dielectric material, the first dielectric material including a first dielectric constant and the second dielectric material including a second dielectric constant; and An insulating structure is formed in the substrate, comprising a first portion and a second portion, the first portion and the second portion being located on multiple opposite sides of the channel region along a second direction perpendicular to the first direction. The first dielectric material includes a first width and the second dielectric material includes a second width. The first width is between 70% and 90% of the total width, and the total width is the sum of the first width and the second width. The first dielectric material is located on a central portion of the channel region, and the second dielectric material is located on a first end and a second end of the channel region. The first end and the second end are separated from each other along a second direction through the central portion of the channel region.

8. The semiconductor device as claimed in claim 7, characterized in that, The gate dielectric further includes a third dielectric material, which and the second dielectric material are located adjacent to each other along the edge of the channel region and offset from each other on each side of the channel region along the first direction.

9. A semiconductor device, characterized in that, include: One substrate; A source region, a drain region, and a channel region, wherein the channel region separates the source region from the drain region, each being formed in a substrate and separated from each other along a first direction; A gate dielectric is formed over the channel region and includes a first dielectric material and a second dielectric material, the first dielectric material including a first dielectric constant and the second dielectric material including a second dielectric constant, the second dielectric constant being smaller than the first dielectric constant; and An insulating structure is formed in the substrate, comprising a first portion and a second portion. The first dielectric material is located on a central portion of the channel region and the second dielectric material is located on a first end and a second end of the channel region, the first end and the second end being separated from each other along a second direction through the central portion of the channel region, and the second dielectric material further extending on a plurality of separate edges of the first end of the channel region and on the second end of the channel region.

10. The semiconductor device as claimed in claim 9, characterized in that, in: The first dielectric material includes a first width, and the second dielectric material includes a second width, wherein the first width is between 70% and 90% of a total width, and the total width is the sum of the first width and the second width.

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