Semiconductor device

Abstract

A semiconductor device includes a stack of semiconductor channels over a substrate, wherein at least one semiconductor channel of the stack includes a channel sidewall defined by a vertical portion and a rounded portion, wherein the vertical portion comprises a majority of the channel sidewall; an interface layer surrounding each semiconductor channel of the stack of semiconductor channels, wherein the interface layer has a thicker portion at the rounded portion of the semiconductor channel and a thinner portion at the non-rounded portion of the semiconductor channel; a high-k dielectric layer over the interface layer and surrounding the interface layer, wherein the high-k dielectric layer has a thicker portion over the thicker portion of the interface layer and a thinner portion over the thinner portion of the interface layer; and a gate electrode over the high-k dielectric layer.

Description

Technical Field

[0001] This utility model relates to semiconductor manufacturing technology, and more particularly to semiconductor devices. Background Technology

[0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices that can simultaneously support a greater number of increasingly complex and sophisticated functions. To meet these demands, the integrated circuit (IC) industry has continuously developed trends towards low-cost, high-efficiency, and low-power integrated circuits. To date, these goals have been largely achieved by reducing the size of integrated circuits (e.g., the smallest possible size of an integrated circuit component), thereby improving production efficiency and reducing associated costs. However, such size reduction also increases the complexity of the integrated circuit manufacturing process. Therefore, continued progress in integrated circuit devices and their performance requires similar advancements in integrated circuit manufacturing processes and technologies.

[0003] One advancement is the development of gate-all-around (GAA) field-effect transistors (FETs). A GAA is a transistor with a gate stack (gate electrode and gate dielectric layer) surrounding the transistor channel, such as a vertically stacked GAA metal-oxide-semiconductor field-effect transistor (MOSFET) device made of horizontal nanowires or nanosheets. Nanowire or nanosheet transistor channels are typically formed with circular, elliptical, or rounded square profiles, with curvature portions greater than 50% on their channel sidewalls. However, the high curvature of the channel sidewalls can induce localized external electric fields, which limit and reduce the reliability and lifetime of the transistor device. Furthermore, these transistor channels are typically surrounded by a conformal and uniform gate insulator. The gate insulator conforms to the curved shape of the channel corners. This limits the gate insulator's ability to address the external electric field effects caused by the channel curvature.

[0004] Therefore, while existing fully-wound gate field-effect transistors with nanosheet channels are generally sufficient for their intended purpose, they are not entirely satisfactory in all aspects. Utility Model Content

[0005] The purpose of this invention is to provide a semiconductor device to solve at least one of the above-mentioned problems.

[0006] A semiconductor device is provided according to some embodiments. This semiconductor device includes a stack of semiconductor channels located above a substrate, wherein at least one of the stacked semiconductor channels includes a channel sidewall defined by a vertical portion and a rounded corner portion, wherein the vertical portion constitutes a majority of the channel sidewall; an interface layer covering each semiconductor channel of the stack surrounding the semiconductor channels, wherein the interface layer has a thicker portion located at a corner portion of the semiconductor channel and a thinner portion located at a non-corner portion of the semiconductor channel; a high-dielectric-constant dielectric layer located above and covering the interface layer, wherein the high-dielectric-constant dielectric layer has a thicker portion located on the thicker portion of the interface layer and a thinner portion located on the thinner portion of the interface layer; and a gate electrode located above the high-dielectric-constant dielectric layer.

[0007] According to one embodiment of the present invention, the thinner portion of the interface layer is... to The range.

[0008] According to one embodiment of the present invention, the thickness difference between the thicker portion and the thinner portion of the interface layer is... to The range.

[0009] According to one embodiment of the present invention, the thinner portion of the high dielectric constant dielectric layer is... to The range.

[0010] According to one embodiment of the present invention, the thickness difference between the thicker portion and the thinner portion of the high dielectric constant dielectric layer is... to The range.

[0011] According to one embodiment of the present invention, the percentage of the plurality of vertical portions is greater than the percentage of the plurality of rounded portions.

[0012] According to one embodiment of the present invention, the percentage of the plurality of said rounded corner portions is 5% to 50% of the plurality of said channel sidewalls.

[0013] According to one embodiment of the present invention, the ratio of the thicker portion of the interface layer to the thinner portion of the interface layer is in the range of 1.05 to 1.17.

[0014] According to one embodiment of the present invention, the ratio of the thicker portion of the high dielectric constant dielectric layer to the thinner portion of the high dielectric constant dielectric layer is in the range of 1.05 to 1.17.

[0015] According to one embodiment of the present invention, the thicker portion of the interface layer is... to The range, and the thinner portion of the high dielectric constant dielectric layer in to The range. Attached Figure Description

[0016] The aspects of this utility model can be better understood through the following detailed description in conjunction with the accompanying drawings. It should be emphasized that, according to industry standard practice, many components are not drawn to scale. In fact, the dimensions of various components may be arbitrarily increased or decreased for clarity of discussion. It should also be emphasized that the accompanying drawings only show typical embodiments of this utility model and should not be considered as limiting the scope, as this utility model can be equally applied to other embodiments. Furthermore, the accompanying drawings may implicitly describe components not explicitly described in the detailed description.

[0017] Figure 1 A flowchart illustrating a method for forming a semiconductor device having a square channel according to an embodiment of the present invention is shown, wherein the device has a thicker gate dielectric insulator at or throughout the corner portions of its channel.

[0018] Figure 2 A three-dimensional schematic diagram of a semiconductor workpiece is shown, in which lines A-A', B-B', and C-C' cross the workpiece.

[0019] Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A and Figure 13A This invention illustrates an embodiment of the present invention. Figure 1 The intermediate stages of manufacturing and processing Figure 2 A cross-sectional view of a semiconductor device cut by line A-A'.

[0020] Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B and Figure 13B This invention illustrates an embodiment of the present invention. Figure 1 The intermediate stages of manufacturing and processing Figure 2 A cross-sectional view of a semiconductor device cut by line B-B'.

[0021] Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C and Figure 13C This invention illustrates an embodiment of the present invention. Figure 1 The intermediate stages of manufacturing and processing Figure 2 A cross-sectional view of a semiconductor device cut by line C-C'.

[0022] Figure 14A and Figure 14B The present invention illustrates a semiconductor device having a square channel according to different embodiments.

[0023] Figure 15A and Figure 15B Show Figure 14A and Figure 14B Enlarged views to show respectively Figure 14A and Figure 14B Further dimensional details of the semiconductor device.

[0024] Figure 16 A flowchart illustrating a method for forming a metal gate structure with a thicker gate dielectric insulator at a transistor channel corner, in part or all of an embodiment of the present invention.

[0025] Figure 17 A semiconductor device having first and second fully wound gate devices is shown according to an embodiment of the present invention.

[0026] Figure 18 A semiconductor device having first and second fully wound gate devices is shown according to another embodiment of the present invention.

[0027] Figure 19 A semiconductor device having first and second fully wound gate devices is shown according to another embodiment of the present invention.

[0028] The attached figures are labeled as follows:

[0029] 100: Method

[0030] 102, 104, 106, 108, 110, 112, 114, 116: Operations; 115, 117: Work function layer

[0031] 119: Gate filler

[0032] 120: Gate electrode

[0033] 200: Semiconductor devices

[0034] 202: Base

[0035] 202a: Highlighted parts

[0036] 204: Semiconductor Stacking

[0037] 204a: First semiconductor layer

[0038] 204b: Second semiconductor layer

[0039] 205: Intermediary Layer

[0040] 206: Isolation Structure

[0041] 208: Dummy gate structure

[0042] 209: Dummy Gate Stack

[0043] 211: Gate spacer

[0044] 212: Source / Drain Trench

[0045] 214: Semiconductor Stacking Section

[0046] 215: Semiconductor fins

[0047] 216: Internal spacer

[0048] 240: Channel

[0049] 242: Interface Layer

[0050] 244: High dielectric constant dielectric layer

[0051] 250: Workpiece

[0052] 260: Gate dielectric layer

[0053] 275: Gate Trench

[0054] 308: Metal gate structure

[0055] 500a, 500b: Dashed box

[0056] 800: Source / Drain Components

[0057] 900: Interlayer dielectric layer

[0058] 1002, 1004, 1006, 1008, 1010, 1012: Steps

[0059] A-A', B-B', C-C': Lines

[0060] CR: Channel Area

[0061] h1, h2: Height

[0062] SDR: Source / Drain Region

[0063] t HK ,t HK ',t IL ,t IL ':thickness

[0064] X, Y, Z: Direction Detailed Implementation

[0065] The following provides many different embodiments or examples for implementing various components of this utility model. Specific examples of components and configurations are described below to simplify this utility model. Of course, these are merely examples and not intended to be limiting. For example, the description mentioning that a first component is formed on or above a second component may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components, so that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in different examples of this utility model. This repetition is for simplification and clarity and does not represent a specific relationship between the different embodiments and / or states discussed.

[0066] Additionally, this document may use spatial relative terms such as “under,” “below,” “below,” “below,” “above,” “above,” “above,” and similar terms to describe the relationship between one or more elements or components as shown in the figures. Besides the orientations depicted in the figures, these spatial relative terms are also used to cover different orientations of the device in use or operation. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatial relative adjectives used herein will also be interpreted according to the orientation after the turn.

[0067] Furthermore, when using terms such as "approximately," "about," "roughly," and similar expressions to describe numbers or ranges of numbers, these terms are used to cover numbers within a reasonable range that includes the number, such as within + / - 10% of the number or other values ​​understood by those skilled in the art to which this invention pertains. For example, the term "approximately 5nm" can cover a size range of 4.5nm to 5.5nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to which this invention pertains, typically + / - 10%. And when comparing the size or dimensions of one component with another, the terms "approximately the same," "substantially the same," "similar in size," and similar expressions can be understood as within + / - 10% of the compared components. Moreover, the disclosed dimensions of different components can implicitly disclose the size ratios between the different components.

[0068] This invention relates to a fully wound gate (GAA) field-effect transistor (FET) with a square channel, wherein the gate dielectric insulator is thicker at the channel corners. The square channel is defined by a channel with sidewalls having a flatter vertical portion than the curved portion. In other words, each sidewall of the channel is formed with a curvature portion of less than 50% on its channel sidewall. By reducing the curvature of the channel sidewalls, the local external electric field caused by the curved channel surface is minimized, thereby improving the reliability and performance of the transistor device. Furthermore, the square plate channel shape is advantageous for higher drive current (Id). on Lower leakage current (I) off This results in improved reliability and lifespan. However, due to process limitations, the corners (i.e., rounded corners) of square channels still retain relatively sharp bends. As a result, external electric fields can still be induced at the channel corners and propagate outwards. This invention addresses this problem by forming a non-conformal gate dielectric layer with a thicker portion around the channel corners to improve the reliability of the gate oxide. The thicker gate dielectric insulator at the channel corners compensates for the problem of localized electric field enhancement caused by the sharp curvature of the channel corners.

[0069] Figure 1 The flowchart illustrates a method 100 for forming a semiconductor device 200 according to an embodiment of the present invention. The semiconductor device 200 has a square channel with a thicker gate dielectric insulator at or throughout its corner portions. Note that further details regarding the formation of the thicker gate dielectric insulator are provided in... Figure 16 The flowchart is expanded to show the operation steps of expansion method 100. The following refers to... Figure 2 , Figures 3A to 13A , Figures 3B to 13B and Figures 3C to 13C Describe method 100, and refer to Figures 14A-15A and Figures 14B to 15BFurther details are described below. For clarity, these figures have been simplified to better understand the concept of this invention. Additional components may be added to the semiconductor device 200, and some components described below may be replaced, modified, or eliminated in other embodiments of the semiconductor device 200.

[0070] The semiconductor device 200 described herein may be an integrated circuit (IC) wafer, a system on chip (SoC), or a portion thereof, comprising a variety of passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), FinFETs, nanosheet field-effect transistors, nanowire field-effect transistors, other types of multi-gate field-effect transistors, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused metal-oxide-semiconductor (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. In some embodiments, the device is contained in a non-volatile memory, such as non-volatile random access memory (NVRAM), flash memory, electrically erasable programmable read-only memory (EEPROM), electrically programmable read-only memory (EPROM), other suitable memory types, or combinations thereof.

[0071] Figure 2A three-dimensional schematic diagram of semiconductor workpiece 250 is shown, in which lines A-A', B-B', and C-C' cross workpiece 250. Semiconductor workpiece 250 corresponds to semiconductor device 200 at the start of method 100. Line A-A' longitudinally cuts along semiconductor fin 215 in the x-direction and crosses multiple dummy gate structures 208. Line B-B' longitudinally crosses multiple source / drain regions (SDRs) of semiconductor fin 215 in the y-direction. Line C-C' longitudinally crosses the dummy gate stack 209 of dummy gate structure 208 in the y-direction. Figures 3A to 13A , Figures 3B to 13B and Figures 3C to 13C Shown in accordance with Figure 1 Cross-sectional views of a semiconductor device 200 cut along lines A-A', B-B', and C-C' respectively during the intermediate stages of manufacturing and processing by method 100. Figure 3A , Figure 3B and Figure 3C At the same manufacturing stage Figure 4A , Figure 4B and Figure 4C At the same manufacturing stage Figure 5A , Figure 5B and Figure 5C Being in the same manufacturing stage, etc.

[0072] Now let's refer to each other. Figure 2 and Figures 3A-3C In method 100, operation 102 receives a workpiece 250 having semiconductor fins 215, the semiconductor fins 215 having interleaved first semiconductor layers 204a and second semiconductor layers 204b extending over an isolation structure 206 above a substrate 202. The workpiece 250 also includes a dummy gate structure 208 above a channel region CR of the semiconductor fins 215.

[0073] The workpiece 250 can be formed by the following process. First, a substrate 202 is received. The substrate 202 can be a silicon (Si) substrate, or a substrate having other semiconductor materials, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. The substrate 202 can be doped with a p-type dopant, such as boron, or an n-type dopant, such as phosphorus. In another embodiment, the substrate 202 can be doped with nitrogen for growing a defect-free silicon crystal stack (e.g., semiconductor stack 204) or a defect-free silicon crystal source / drain component (e.g., source / drain component 800 described later).

[0074] Subsequently, a semiconductor stack 204 is formed over the substrate 202. In one embodiment, the semiconductor stack 204 is epitaxially grown over the substrate 202. The semiconductor stack 204 includes staggered first semiconductor layers 204a and second semiconductor layers 204b. The first semiconductor layers 204a have a different material composition than the second semiconductor layers 204b. For example, each first semiconductor layer 204a is made of silicon and each second semiconductor layer 204b is made of silicon-germanium.

[0075] Subsequently, the semiconductor stack 204 and the substrate 202 can be patterned to form semiconductor fins 215. Each semiconductor fin 215 includes a protrusion 202a of the substrate 202 and a semiconductor stack portion 214 of the semiconductor stack 204. The semiconductor fins 215 can be formed by a patterning process including lithography and etching. In some embodiments, the lithography process forms a patterned mask layer covering the area used to form the semiconductor fins 215, and the etching process uses the patterned mask layer as an etching mask to etch exposed portions of the patterned mask layer. The etching process forms grooves that separate and define the semiconductor fins 215.

[0076] Subsequently, an isolation layer for forming the isolation structure 206 can be deposited over the semiconductor fins. The isolation layer rests on the top surface of the substrate 202, fills the grooves between the semiconductor fins 215, and rests on the top surface of the semiconductor fins 215. In other words, the isolation layer is overfilled to surround all exposed surfaces of the semiconductor fins 215. The isolation layer can be deposited using any suitable deposition process, and the isolation layer can comprise silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-dielectric-constant dielectric, a combination of the foregoing, and / or other suitable materials.

[0077] Subsequently, the isolation layer can be etched to form an isolation structure 206 surrounding the bottom portion (e.g., protrusion 202a) of the semiconductor fin 215. The isolation structure 206 can be formed by first performing chemical mechanical polishing (CMP) to remove excess portions of the isolation layer above the top surface of the semiconductor fin 215. The remaining portion of the isolation layer forms isolation regions laterally between the semiconductor fins 215. Next, the isolation regions are etched in an etching step such that the semiconductor stack portion 214 of the semiconductor fin 215 lies above the top surface of the isolation regions. The resulting isolation regions form the isolation structure 206. In this embodiment, the isolation structure 206 is a shallow trench isolation (STI) structure.

[0078] Subsequently, a dummy gate structure 208 with a dummy gate stack 209 and a gate spacer 211 is formed above the channel region CR of the semiconductor fin 215. The semiconductor fin 215 (also known as the active region or fin active region) extends longitudinally in the x direction, and the dummy gate structure 208 extends longitudinally in the y direction.

[0079] Reference Figure 3A The channel region CR is the region of the semiconductor fin 215 beneath the dummy gate structure 208. The source / drain (S / D) region SDR is the region of the semiconductor fin 215 adjacent to the channel region CR and extending between the dummy gate structures 208. Each dummy gate structure 208 includes a dummy gate stack 209 and gate spacers 211 located above the sidewalls of the dummy gate stack 209. The dummy gate stack 209 may be made of polysilicon, and the gate spacers 211 may be made of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbide, metal nitride, or a suitable dielectric material. (See reference...) Figures 3B-3C Because the dummy gate structure 208 is only located above the channel region CR and not above the source / drain region SDR, only Figure 3C A dummy gate stack 209 covering semiconductor fin 215 is shown. Although not shown, the dummy gate structure 208 stack 209 may include various layers, such as a dummy gate electrode layer, a dummy gate dielectric layer, and / or a dummy hard mask layer.

[0080] Now let's refer to each other. Figures 4A to 4C In method 100, in operation 104, a source / drain trench 212 is formed in the source / drain region SDR adjacent to the channel region CR. The source / drain trench 212 exposes the side surfaces of the remaining portion of the semiconductor fin 215 (i.e., the portion in the channel region CR). The formation of the source / drain trench 212 can be achieved by a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process is a multi-step etching process. For example, the etching process may include alternating etchants to remove the first semiconductor layer 204a and the second semiconductor layer 204b separately and alternately. In some embodiments, the parameters of the etching process are configured to selectively etch the semiconductor stack portion 214 while minimally (or even not at all) etching the dummy gate structure 208 (i.e., the dummy gate stack 209 and the gate spacer 211). In some embodiments, a lithography process is performed to form a patterned mask layer covering the dummy gate structure 208, and the patterned mask layer is used as an etching mask during the formation of the source / drain trench 212. In the illustrated embodiment, the etching process may partially etch the isolation structure 206, resulting in some loss of the isolation structure 206.

[0081] Now let's refer to each other. Figures 5A to 5C , Figures 6A to 6C and Figures 7A to 7C In method 100, operation 106 replaces the second semiconductor layer 204b with an interposer layer 205. Operation 106 may include lateral etching to completely remove the second semiconductor layer 204b, while minimally (or even not at all) etching the first semiconductor layer 204a (see [link to method 100]). Figure 5A and Figure 5C For example, etching involves a high selectivity for etching SiGe compared to etching Si. As a result, one or more of the first semiconductor layers 204a can be suspended in the vertical direction. Then, an interposer layer 205 is formed in the space left by removing the second semiconductor layer 204b (see...). Figure 6A and Figure 6C Intermediate layer 205 can be formed by an intermediate layer deposition process and an intermediate layer etching process. For example, an intermediate layer deposition process is performed to conformally fill the source / drain trench 212 with dielectric material. The dielectric material penetrates into the gaps left by the removal of the second semiconductor layer 204b, thereby filling the gaps. In this embodiment, the dielectric material of intermediate layer 205 is an oxide-based dielectric, such as silicon oxide. Then, an intermediate layer etching process is performed to selectively etch the dielectric material to form intermediate layer 205 (see [link to documentation]). Figure 7A The interposer etching process can be a dry etching process to remove excess dielectric material in the source / drain trench 212 and outside the channel region CR.

[0082] In addition, and specifically refer to Figure 7A The interposer etching process may include a side etching process to selectively etch the sidewalls of the interposer 205 without etching (or substantially without etching) the first semiconductor layer 204a. In other words, the side etching process is configured to etch the interposer 205 laterally (e.g., along the x-direction), thereby reducing the length of the interposer 205 along the x-direction. The side etching process is a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. After the side etching process, an air gap is formed beneath each of the first semiconductor layers 204a.

[0083] Interposer 205 is subsequently removed during the channel release phase when the metal gate is formed later. Note that in some embodiments (not shown), the second semiconductor layer 204b is not replaced by interposer 205. Instead, the second semiconductor layer 204b is retained until removal during the later channel release phase. In these embodiments, the resulting channel is more curved along its sidewalls (e.g., having a curvature greater than 50% at its channel sidewalls). This is because the etchant selectivity is not optimal when removing the second semiconductor layer 204b instead of interposer 205 during channel release (partially). For this embodiment, by replacing the second semiconductor layer 204b with interposer 205, damage to the silicon channel and source / drain components during channel release is reduced. As a result, the resulting channel is more square and less curved along its sidewalls (e.g., having a curvature less than 50% at its channel sidewalls). This is because the interposer 205 can be selectively and precisely removed with little or no semiconductor residue (e.g., no SiGe residue), as opposed to directly removing the second semiconductor layer 204b during the channel release phase.

[0084] Now let's refer to each other. Figures 8A to 8C In method 100, an inner spacer 216 is formed at operation 108 in the interposer 205 adjacent to the channel region CR. The inner spacers 216 are formed in the air gap beneath each first semiconductor layer 204a. The inner spacers are disposed directly beneath the gate spacer 211 and may be substantially perpendicularly aligned to the gate spacer 211 along the z-direction. The inner spacers 216 may be formed by any suitable process. In one embodiment, the formation of the inner spacers 216 may be performed by a spacer deposition process and a spacer etching process. For example, a spacer deposition process is performed to form a spacer layer over the dummy gate structure 208 and over the components defining the source / drain trench 212 (e.g., the first semiconductor layer 204a, the interposer 205, and the substrate 202). The spacer layer partially (and in some embodiments, completely) fills the source / drain trench 212. The spacer deposition process is configured to ensure that the spacer layer fills the air gaps between the substrate 202 beneath the gate spacer 211 and the first semiconductor layer 204a, as well as between the first semiconductor layers 204a. A spacer etching process is then performed, which selectively etches the spacer layer to form, as shown in the image. Figure 8AThe inner spacer 216 shown is used where the first semiconductor layer 204a, the dummy gate stack 209, and the gate spacer 211 are etched with minimal (or even no) etching. The spacer layer (and therefore the inner spacer 216) comprises a material different from the material of the first semiconductor layer 204a and the gate spacer 211 to achieve desired etch selectivity. In some embodiments, the spacer layer comprises a dielectric material comprising silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxynitride). In some embodiments, the spacer layer comprises a low dielectric constant dielectric material.

[0085] Now let's refer to each other. Figures 9A to 9C In method 100, source / drain components 800 are epitaxially grown in the source / drain trench 212 and over the protrusions 202a of the semiconductor fin 215 during operation 110. The source / drain components 800 may comprise n-type source / drain components corresponding to n-type GAA transistor regions or p-type source / drain components corresponding to p-type GAA transistor regions. The source / drain components 800 can be formed by epitaxial processes using chemical vapor deposition (CVD) techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum chemical vapor deposition (UHV-CVD)), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The epitaxial process may use gaseous and / or liquid precursors that interact with the composition of the substrate 202 (or its protrusions 202a) and / or the semiconductor stack portion 214 (specifically, the first semiconductor layer 204a). The epitaxial source / drain component 800 is doped with n-type and / or p-type dopants. In some embodiments, for an n-type GAA transistor, the epitaxial source / drain component 800 comprises silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., forming a Si:C epitaxial source / drain component, a Si:P epitaxial source / drain component, or a Si:C:P epitaxial source / drain component). In some embodiments, for a p-type GAA transistor, the epitaxial source / drain component 800 comprises silicon-germanium or germanium and may be doped with boron, other p-type dopants, or combinations thereof (e.g., forming a Si:Ge:B epitaxial source / drain component).

[0086] In some embodiments, the epitaxial source / drain component 800 includes materials and / or dopants in the respective channel region CR to achieve the desired tensile and / or compressive stresses. In some embodiments, doping of the epitaxial source / drain component 800 is achieved by adding impurities to the source material of the epitaxial process during deposition (i.e., in-situ). In some embodiments, doping of the epitaxial source / drain component 800 is achieved by an ion implantation process following the deposition process. In some embodiments, an annealing process (e.g., rapid thermal annealing (RTA) and / or laser annealing) is performed to activate the dopants in the epitaxial source / drain component 800 and / or other source / drain regions (e.g., heavily doped source / drain regions and / or lightly doped source / drain (LDD) regions). In some embodiments, the epitaxial source / drain components 800 are formed in a separate process sequence, including, for example, shielding the p-type GAA transistor region when forming the epitaxial source / drain components 800 in the n-type GAA transistor region, and shielding the n-type GAA transistor region when forming the epitaxial source / drain components 800 in the p-type GAA transistor region.

[0087] In some embodiments (not shown), the epitaxial source / drain components 800 are formed to include more than one epitaxial layer. For example, each source / drain component 800 includes one (or more) inner heavily doped layers and outer lightly doped layers. In one embodiment, an outer lightly doped layer is first epitaxially grown in a source / drain trench 212 from the side surfaces of the substrate 202 and the first semiconductor layer 204a. Then, an inner heavily doped layer is epitaxially grown from the outer lightly doped layer to fill the source / drain trench 212. The source / drain components 800 may grow to a height above the topmost first semiconductor layer 204a and between the gate spacers 211 of the different dummy gate structures 208. Figure 9B As shown, source / drain components 800 are grown above the isolation structure 206.

[0088] Now let's refer to each other. Figures 10A to 10C In method 100, in operation 112, an interlayer dielectric (ILD) layer 900 is formed above the source / drain component 800. For example... Figure 10AAs shown, the interlayer dielectric layer 900 also fills the space between adjacent dummy gate structures 208. The interlayer dielectric layer 900 can be formed by deposition processes (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), metal-organic chemical vapor deposition (MOCVD), reduced pressure chemical vapor deposition (RPCVD), plasma-assisted chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer chemical vapor deposition (ALCVD), ambient pressure chemical vapor deposition (APCVD), electroplating, other suitable methods, or combinations thereof). In some embodiments, the interlayer dielectric layer 900 is formed by a flowable chemical vapor deposition (FCVD) process, which includes, for example, depositing a flowable material (e.g., a liquid compound) over the semiconductor device 200 and converting the flowable material into a solid material using suitable techniques, such as thermal annealing and / or ultraviolet radiation treatment.

[0089] The interlayer dielectric layer 900 comprises a dielectric material, including, for example, silicon oxide, silicon nitride, silicon oxynitride, an oxide formed from tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borosilicate glass (BPSG), a low-dielectric-constant dielectric material, other suitable dielectric materials, or combinations thereof. Exemplary low-dielectric-constant dielectric materials include fluorosilicate glass (FSG), carbon-doped silicon oxide, and black diamond. (Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, phenylcyclobutene (BCB), SiLK (Dow Chemical, Midland, Michigan), polyimide, other low-dielectric-constant dielectric materials, or combinations thereof. In the depicted embodiments, interlayer dielectric layer 900 is a dielectric layer comprising a low-dielectric-constant dielectric material (generally referred to as a low-dielectric-constant dielectric layer). Interlayer dielectric layer 900 may comprise a multilayer structure having a variety of dielectric materials. In some embodiments, a contact etch-stop layer (CESL) (not shown) is disposed between interlayer dielectric layer 900 and isolation structure 206, source / drain components 800, and gate spacer 211. The contact etch-stop layer comprises a material different from that of interlayer dielectric layer 900, for example, a dielectric material different from the dielectric material of interlayer dielectric layer 900. For example, when the interlayer dielectric layer 900 contains silicon oxide or a low dielectric constant dielectric material, the contact etch stop layer contains silicon and nitrogen, such as silicon nitride or silicon oxynitride. After depositing the interlayer dielectric layer 900 and / or the contact etch stop layer, chemical mechanical polishing and / or other planarization processes may be performed until the top (or top surface) of the dummy gate stack 209 is exposed.

[0090] Now let's refer to each other. Figures 11A to 11C and Figures 12A-12C In operation 114, method 100 forms a suspended semiconductor channel 240 by removing the dummy gate stack 209 from the dummy gate structure 208 and removing the interposer layer 205.

[0091] First, such as Figures 11A to 11C As shown, operation 114 removes the dummy gate stack 209 to expose the channel region CR beneath the dummy gate stack 209. The dummy gate stack 209 is removed by a suitable etching process, thereby obtaining the gate trench 275 and exposing the semiconductor stack portion 214. The etching process is designed to selectively remove the dummy gate stack 209 using an etchant. In the depicted embodiment, the etching process completely removes the dummy gate stack 209 to expose the surfaces of the first semiconductor layer 204a and the interposer layer 205 in the yz plane (see...). Figure 11CThe etching process is a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process is a multi-step etching process. For example, the etching process may include alternating etchants to individually remove individual layers of the dummy gate stack 209, such as the dummy gate electrode layer, the dummy gate dielectric layer, and / or the dummy hard mask layer. In some embodiments, the etching process is configured to selectively etch the dummy gate stack 209 while minimally (or even not at all) etching other components of the semiconductor device 200, such as the interlayer dielectric layer 900, the gate spacer 211, the first semiconductor layer 204a, and the interposer layer 205. In some embodiments, a lithography process is performed to form a patterned mask layer covering the interlayer dielectric layer 900 and / or the gate spacer 211, and the etching process uses the patterned mask layer as an etching mask.

[0092] Secondly, such as Figures 12A-12C As shown, the interposer 205 (exposed by the gate trench 275) is selectively removed from the channel region CR to form a suspended semiconductor channel 240. In other words, the remaining portion of the first semiconductor layer 204a now becomes the suspended semiconductor channel 240. This removal process is also referred to as channel release, and this stage of the manufacturing process is referred to as the channel release stage. In the depicted embodiment, the etching process selectively etches the interposer 205 while etching the first semiconductor layer 204a with minimal (or even no) etching, and in some embodiments, the gate spacer 211 and / or the inner spacer 216 are etched with minimal (or even no) etching. Various etching parameters can be adjusted to achieve selective etching of the second semiconductor layer 204b, such as etchant composition, etching temperature, etchant concentration, etching time, etching pressure, source power, RF bias, RF bias power, etchant flow rate, other suitable parameters, or combinations thereof. For example, an etchant is selected for the etching process to etch the material of the interposer 205 (silicon oxide in the depicted embodiment) at a higher rate than the material of the first semiconductor layer 204a (silicon in the depicted embodiment) (that is, the etchant has high etch selectivity relative to the material of the interposer 205). The etching process is a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof.

[0093] As previously described, because the interposer 205 (instead of the second semiconductor layer 204b) is etched during the channel release phase, the resulting suspended semiconductor channel 240 has a more square profile (e.g., a curvature portion of less than 50%). The suspended semiconductor channel 240 then becomes a square channel 240, and will be discussed later. Figures 15A-15B Describe the dimensional details of the square channel 240.

[0094] Now let's refer to each other. Figures 13A-13CIn method 100, in operation 116, a metal gate structure 308 is formed over the channel region CR and surrounds each suspended semiconductor channel 240. Although not shown in... Figures 13A-13C (But shown later), each metal gate structure 308 may include a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. In some embodiments, the gate dielectric layer includes an interface layer and a high-dielectric-constant dielectric layer disposed on the interface layer. The gate electrode may include one or more conductive materials, such as a capping layer, a work function metal layer, a barrier layer, a metal fill layer, and / or other suitable conductive material layers. The work function layers (if present) may be the same or different, and may be n-type or p-type work function layers, depending on the type of the corresponding GAA transistor. The gate dielectric layer contains a high-dielectric-constant dielectric material, such as a material with a dielectric constant greater than silicon oxide (k≈3.9). The gate electrode may be formed by a chemical vapor deposition process or a physical vapor deposition process to deposit a metal fill layer that fills the remainder of the gate trench 275 and is located above the gate dielectric layer. The metal fill layer contains a suitable conductive material, such as Al, W, and / or Cu. The metal fill layer may additionally or collectively contain other metals, metal oxides, metal nitrides, other suitable materials, or combinations thereof. Alternatively, another suitable deposition process can be used to form the metal filler layer, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), high-density plasma chemical vapor deposition (HDPCVD), metal-organic chemical vapor deposition (MOCVD), reduced pressure chemical vapor deposition (RPCVD), plasma-assisted chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer chemical vapor deposition (ALCVD), atmospheric pressure chemical vapor deposition (APCVD), spin coating, electroplating, other deposition processes, or combinations thereof.

[0095] Method 100 may include further steps to complete the fabrication of the semiconductor device 200. For example, method 100 may further form source / drain contacts over the source / drain component 800, a gate contact over the metal gate structure 308, and an interconnect structure with interconnect metal lines and vias over the source / drain and gate contacts. Additional operations may be provided before, during, and after method 100. Furthermore, in additional embodiments of method 100, some of the described operations may be moved, replaced, or eliminated.

[0096] As described in further detail below (see below) Figure 14A , Figure 15A and Figure 16Operation 116 may include forming a metal gate structure 308 having a thicker gate dielectric insulator covering the channel corners surrounding the square channel 240. This can provide additional insulation to reduce parasitic electric fields at the channel corners.

[0097] Figure 13C Dashed box 500a shows a first stack containing a square channel 240 surrounded by a metal gate structure 308, and dashed box 500b shows a second stack containing a square channel 240 surrounded by a metal gate structure 308. The first stack and the second stack are adjacent to each other and can share the common metal gate structure 308.

[0098] Figure 14A and Figure 14B Semiconductor devices (e.g., semiconductor device 200 or a portion thereof) having square channels 240 are shown according to different embodiments of the present invention. Figure 14A The semiconductor device in can correspond to Figure 13C The area contained in dashed boxes 500a, 500b, or both dashed boxes 500a and 500b. Figure 14B The semiconductor device in can correspond to Figure 13C One of the regions contained in dashed box 500a or dashed box 500b. For example, the first device in dashed box 500a and the second device in dashed box 500b both correspond to Figure 14A Semiconductor devices (such as Figure 17 (As shown). Or, the first device in dashed box 500a is Figure 14A The semiconductor device, the second device in dashed box 500b is Figure 14B The semiconductor device, or vice versa (as shown in Figures 18 and 19). In one embodiment, Figure 14A The device is an n-type fully wound gate field-effect transistor. Figure 14B The device is a p-type fully wound gate field-effect transistor, or vice versa. In one embodiment, Figure 14A and Figure 14B Both devices are n-type fully wound gate field-effect transistors. In one embodiment, Figure 14A and Figure 14B Both devices are p-type fully wound gate field-effect transistors.

[0099] Figure 14A and Figure 14BSimilar to the semiconductor devices described above, each has a square channel 240, and each channel 240 is surrounded by a metal gate structure 308. The channel 240 is made of a semiconductor material, including, but not limited to, Si, SiGe, Ge, GaAs, or InGaAs. The metal gate structure 308 includes a gate dielectric layer 260 covering the square channel 240 and a gate electrode 120 disposed on and surrounding the gate dielectric layer 260. The gate dielectric layer 260 includes sublayers of a gate dielectric insulator. These sublayers include an interface layer 242 covering the channel 240 and a high-dielectric-constant dielectric layer 244 covering the interface layer 242. The interface layer 242 may be an oxide-based dielectric, which may include, but is not limited to, SiOx, GeOx, SiGeOx, and their composites. In one embodiment, the interface layer 242 includes silicon oxide. The high-dielectric-constant dielectric layer 244 may comprise, but is not limited to, HfOx, ZrOx, LaOx, YOx, ScOx, AlOx, and their composites. In one embodiment, the high-dielectric-constant dielectric layer 244 comprises hafnium oxide or zirconium oxide. Both the interface layer 242 and the high-dielectric-constant dielectric layer 244 may be doped or undoped. Possible dopants include, but are not limited to, Si, La, Al, Y, Ge, Ga, Zn, N, F, Cl, C, and / or S. Although not explicitly shown, the gate electrode 120 may comprise several conductive layers, such as a capping layer, a work function metal layer, a barrier layer, a metal-filled layer, and / or other suitable conductive material layers.

[0100] The metal gate structure 308 is formed by first forming a gate dielectric layer 260 and then depositing a gate electrode 120 over the gate dielectric layer 260. The gate dielectric layer 260 can be formed by thermally growing oxide over the square channel and over the protrusion 202a of the substrate 202. The grown oxide forms an interface layer 242. Then, a high-dielectric-constant dielectric layer 244 is deposited over the interface layer 242. As shown, the high-dielectric-constant dielectric layer 244 not only covers the portion of the interface layer 242 surrounding the channel 240, but also is disposed over the portion of the interface layer 242 located on the protrusion 202a of the substrate 202. Furthermore, the high-dielectric-constant dielectric layer 244 can also be deposited over the isolation structure 206.

[0101] Figure 14A and Figure 14B The difference in the device lies in the shape of the gate dielectric layer 260. Figure 14A In this configuration, the gate dielectric layer 260 is non-conformally deposited (or grown) over the square channel 240, such that the gate dielectric layer 260 is thicker at the corner portions of the square channel 240 than at the non-corner portions. Figure 14BIn this process, due to patterning losses, the gate dielectric layer 260 can be formed thinner at the corner portion of the square channel 240 than at the non-corner portion of the square channel 240.

[0102] Figure 15A and Figure 15B Show Figure 14A and Figure 14B Enlarged views of specific areas in the image are shown separately. Figure 14A and Figure 14B Further dimensional details of the semiconductor device.

[0103] Figure 15A Show Figure 14A The channel 240 is nonconformally encapsulated and surrounded by an interface layer 242 and a high-dielectric-constant dielectric layer 244. The channel 240 has a total sheet height h1, and the vertical sidewall portion (or flat sidewall portion) of the channel 240 has a height h2. The channel 240 also includes a curvature portion defining the rounded corners of the channel 240. As previously mentioned, the channel 240 has a curvature portion of less than 50% on its channel sidewalls. In other words, the vertical sidewall portion constitutes the majority of the channel sidewalls. In one embodiment, the percentage of the curvature portion to the total channel sheet height is equal to about 5% to less than 50% (i.e., (h1-h2) / h1 = ~5% to <50%). If the percentage is greater than 50%, the channel 240 is more rounded than when it is square, thus introducing the aforementioned performance problems. In one embodiment, the total sheet height h1 is equal to about 3 nm to about 15 nm.

[0104] Continue to refer to Figure 15A Interface layer 242 has a thickness t around the non-corner portion of channel 240. IL and the thickness t of the corner portion surrounding channel 240 IL’ The non-corner portion of channel 240 refers to the flat section (vertical and horizontal) of channel 240. Thickness t IL’ Greater than thickness t IL In one embodiment, the thickness t IL’ Subtract thickness t IL equal to approximately to approximately In one embodiment, the thickness t IL In Approximate to approximately The range. In one embodiment, the thickness t IL’ In Approximate to approximately The range. In one embodiment, when the thickness t IL For the agreement At that time, thickness t IL’ For the agreement to approximately In one embodiment, t IL’ With tIL The ratio ranges from about 1.05 to about 1.17.

[0105] Continue to refer to Figure 15A The high dielectric constant dielectric layer 244 has a thickness t around the non-corner portion of the channel 240. HK And has a thickness t around the corner portion of channel 240. HK’ Thickness t HK’ Greater than thickness t HK In other words, the high-dielectric-constant dielectric layer 244 has a thicker portion on the thicker portion (corner portion) of the interface layer 242 and a thinner portion on the thinner portion (non-corner portion) of the interface layer 242. In one embodiment, the thickness t HK’ Subtract thickness t HK equal to approximately to approximately In one embodiment, the thickness t HK In Approximate to approximately The range. In one embodiment, the thickness t HK’ In Approximate to approximately The range. In one embodiment, when the thickness t HK For the agreement At that time, thickness t HK’ For the agreement to approximately In one embodiment, t HK’ With t HK The ratio ranges from about 1.05 to about 1.17.

[0106] Figure 15B similar Figure 15A Besides the thickness t IL’ and t HK’ Less than the corresponding thickness t IL and t HK In other words, the gate dielectric layer 260 can be formed thinner at the corner portions of the square channel 240 than at the non-corner portions. This is likely due to patterning losses caused by additional exposure to patterning when forming different types of field-effect transistors with a common-metal gate structure 308 (i.e., the bimetallic gate current causes additional patterning in the PFET or NFET region, which etches away the corner portions of the gate dielectric layer 260).

[0107] Continue to refer to Figure 15B Thickness t IL’ Less than thickness t IL In one embodiment, the thickness t IL’ Subtract thickness t IL equal to approximately to approximately In one embodiment, the thickness t IL In Approximate to approximately The range. In one embodiment, the thickness t IL’ In Approximate to approximately The range. In one embodiment, when the thickness t IL For the agreement At that time, thickness t IL’ For the agreement to approximately In one embodiment, t IL’ With t IL The ratio ranges from approximately 0.33 to approximately 0.98. Thickness t HK’ Less than thickness t HK In one embodiment, the thickness t HK’ Subtract thickness t HK equal to approximately to approximately In one embodiment, the thickness t HK In Approximate to approximately The range. In one embodiment, the thickness t HK’ In Approximate to approximately The range. In one embodiment, when the thickness t HK For the agreement At that time, thickness t HK’ For the agreement to approximately In one embodiment, t HK’ With t HK The ratio ranges from about 0.33 to about 0.98.

[0108] Figure 16 A flowchart illustrating a method (e.g., operation 116) for forming a metal gate structure 308 with a thicker gate dielectric insulator (e.g., gate dielectric layer 260) at a transistor channel corner according to an embodiment of the present invention is shown. For example, operation 116 of method 100 can be based on... Figure 16 Flowchart formation Figure 14A and Figure 15A The metal gate structure 308 is shown. Operation 116 includes steps 1002 to 1012.

[0109] In step 1002, operation 116 thermally grows an interface layer (e.g., interface layer 242) on the semiconductor channel 240. In this embodiment, the grown interface layer comprises an oxide layer thermally grown by introducing a chemical gas (e.g., an oxygen-containing gas and / or an inert gas) over the semiconductor channel 240. To achieve thicker oxide growth around channel corners rather than on flat channel portions, careful adjustment of the thermal operating temperature is required. Experiments show that the thermal oxide growth rates on the (100) and (111) crystal surfaces converge with increasing temperature. Specifically, at high temperatures (above 1000°C), the thermal oxide growth rates on the (100) and (111) crystal surfaces converge to have similar or identical growth rates. However, at lower temperatures (below 950°C), the thermal growth rate on the (111) crystal surface becomes greater than that on the (100) crystal surface. Because the corner portions of channel 240 have (111) crystal planes and the planar portions of channel 240 have (100) crystal planes, growing the oxide layer at a lower temperature (below 950°C) allows the corner portions to grow at a higher rate than the planar portions to obtain the desired profile. The oxide layer can be grown in a rapid thermal processing (RTP) process, resulting in the formation of the aforementioned interface layer (e.g., interface layer 242). In one embodiment, oxygen is intentionally and / or unintentionally introduced at a pressure ranging from 1 Torr to 25 atm at a rate of 0.02% to 100% [O] / N2.

[0110] In one embodiment, the chemical gas introduced for growing the oxide layer comprises a molecular-based oxidant gas, including O2, O3, H2O, and OH. - O -2 And N2O or a diluent gas containing N2 or other inert gases. In this case, an oxygen source is intentionally added as part of the heat treatment. This can facilitate the formation of a thicker interface layer, resulting in a more significant thickness difference between the channel corner portions and the channel planar portion. For this case, the target thermal growth temperature can be in the range of about 500°C to about 950°C, the pressure in the range of about 1 Torr to about 760 Torr, and the duration from about 0 seconds to about 120 seconds. Alternatively, to promote a more distinct growth rate between the (100) and (111) crystal surfaces, a lower temperature is used, but the temperature is applied for a longer time at a higher pressure. For example, the target temperature for growing the oxide layer can be in the range of about 250°C to about 450°C, the pressure in the range of about 700 Torr to about 30 atm, and the duration from about 10 minutes to about 120 minutes.

[0111] In another embodiment, the chemical gas introduced for growing the oxide layer comprises N2, Ar, He, or other inert gases. In this case, oxygen is not intentionally added but may be unintentionally introduced during a previous process or during N2 or inert gas annealing. By unintentionally introducing oxygen, the interface layer can be finely tuned. In this case, the target thermal growth temperature can be in the range of about 500°C to about 950°C, the pressure in the range of about 1 Torr to about 760 Torr, and the duration from about 0 seconds to about 120 seconds. Alternatively, to promote more distinct growth rates between the (100) and (111) crystal surfaces, a lower temperature is used, but the temperature is applied for a longer time at a higher pressure. For example, the target temperature for growing the oxide layer can be in the range of about 250°C to about 450°C, the pressure in the range of about 700 Torr to about 30 atm, and the duration from about 10 minutes to about 120 minutes.

[0112] In another embodiment, the chemical gas introduced for growing the oxide layer comprises an oxidant gas primarily composed of free radicals, which contains O -2 O3, H2O2. Alternatively, the introduced chemical gas can be a free radical gas, such as N2, Ar, He, H2, without intentionally adding oxygen. In both cases, the target temperature for growing the oxide layer can range from room temperature (e.g., 25°C) to approximately 600°C, the pressure from approximately 0.01 Torr to approximately 10 Torr, and the duration from approximately 5 seconds to approximately 300 seconds.

[0113] In step 1004, operation 116 performs wet chemical cleaning, such as RCA cleaning, to remove organic and / or ionic contaminants generated by thermal oxidation. In one embodiment, RCA cleaning includes a first cleaning step (SC-1) for organic cleaning and / or a second cleaning step (SC-2) for ionic cleaning. The cleaning chemicals may include ammonia (NH3), hydrogen peroxide (H2O2), hydrochloric acid (HCl), or combinations thereof. It is noteworthy that wet chemical cleaning does not strip or substantially remove the oxides grown in operation 116. Furthermore, wet chemical cleaning may also form separate oxide layers due to reaction with certain cleaning chemicals (e.g., hydrogen peroxide). The oxide layer formed via wet chemical cleaning can be a conformal, homogeneous layer. The separately formed oxide layer and the oxide layer formed via thermal growth (if both are present) can together form a desired interface layer (e.g., interface layer 242). Note that steps 1002 and 1004 can be performed recursively in a cycle until the aforementioned t is formed. IL and t IL’The desired thickness and thickness ratio of the desired oxide profile. In one embodiment, the formation of the interface layer (e.g., interface layer 242) includes thermal growth, wet chemical cleaning, or both during a cycling process. The cycling process may include a first step 1002 that intentionally introduces oxygen and a second step 1002 that unintentionally introduces oxygen. One or more steps 1004 may be performed between the first step 1002 and the second step 1002.

[0114] In step 1006, operation 116 deposits a high-dielectric-constant dielectric layer (e.g., high-dielectric-constant dielectric layer 244) over a thermally grown interface layer (e.g., interface layer 242) via atomic layer deposition (ALD). The high-dielectric-constant dielectric layer is deposited by sequentially and recursively applying a first precursor followed by a second precursor to form a thin film surrounding the interface layer. The first precursor may be a metal-containing precursor and the second precursor may be an oxidant, or vice versa. A purge or evacuation step is performed between the application of the first and second precursors to pump out gas between each dose of the respective first and second precursors. In one embodiment, the high-dielectric-constant dielectric layer comprises hafnium oxide (HfO2), wherein the first precursor is one or more of HfCl4, TEMA-Hf, or TDMA-Hf, and the second precursor is one or more of H2O, H2O2, O3, or O2. In one embodiment, the high-dielectric-constant dielectric layer comprises zirconium oxide (ZrO2), wherein the first precursor is one or more of ZrCl4, TEMA-Zr, or TDMA-Zr, and the second precursor is one or more of H2O, H2O2, O3, or O2. To achieve a thicker high-dielectric-constant dielectric around the channel corners (above the thicker portion of the interface layer) than around the flat channel portions (above the thinner portion of the interface layer), the atomic layer deposition parameters need to be carefully tuned. Specifically, the high-dielectric-constant dielectric layer is deposited using non-conformal atomic layer deposition parameters. To achieve this, in this embodiment, the deposition of the high-dielectric-constant dielectric layer is performed under a diffusion-limited rule (opposite to a reaction-limited rule), and the diffusion-limited rule has a low diffusion coefficient, high reaction probability, and high aspect ratio. Under the diffusion-limited rule, reactant molecules are adsorbed before complete diffusion, while under the reaction-limited rule, the adsorption of gas-phase reactant molecules takes longer than the diffusion of these molecules. Diffusion limitation rules can be defined by a Thiele modulus Φ much greater than 1. To achieve this, atomic layer deposition parameters are adjusted to have high operating pressure, high precursor flow rate, short precursor pulse time, or a combination thereof. For example, during atomic layer deposition growth, the operating pressure in the atomic layer deposition chamber is greater than about 5 Torr, for example, from about 5 Torr to about 100 Torr; the precursor flow rate fraction between the precursors (first and second precursors) and other gases (e.g., purge gas, carrier gas, etc.) is greater than about 35%, for example, from about 35% to about 70%; and / or the precursor pulse time of the first and / or second precursors is less than about 1.5 seconds, for example, from about 0.1 seconds to about 1.5 seconds.

[0115] In step 1008, operation 116 performs thermal annealing to improve the surface topology and electrical properties of the deposited high-dielectric-constant dielectric. Note that steps 1006 and 1008 can be performed recursively during the cycle until the aforementioned t is formed. HK and tHK’ The desired thickness and thickness ratio of the desired high dielectric constant dielectric profile. At the end of step 1008, a thermal insulator (e.g., gate dielectric layer 260) with a thicker portion is formed in the channel portion.

[0116] In one embodiment, step 1008 involves annealing with an intentional interface layer re-growth (e.g., re-growth interface layer 242). This may include removing oxygen-related substances or introducing trace amounts of oxidants from byproducts, capping layers, or adsorbed layers via thermal annealing. Step 1008 may be similar to step 1002 in terms of growth parameters and behavior, and for simplicity, similar parameters and behaviors will not be described further. In another embodiment, step 1008 may include introducing nitriding gases (e.g., NH3, N2H4), fluorinated gases (e.g., NF3, F2), or radical-based nitriding substances (e.g., N*, NH4). x *) or free radical fluorinated substances (e.g., F*, FH) x *) As part of thermal annealing. In the case where steps 1006 and 1008 are performed recursively during the cycle, the annealing step between high dielectric constant dielectric deposits may include intentional interface layer retardation, while the final annealing step before step 1010 may be normal annealing without intentional interface layer retardation.

[0117] In step 1010, operation 116 can be performed on a square success function layer (see example) on a high dielectric constant dielectric layer (e.g., high dielectric constant dielectric layer 244). Figures 17-19 The work function layers 115 and 117 in the diagram are used to adjust the critical voltage of different devices to suit design requirements. As previously mentioned, the work function layers (if present) can be the same or different, and can be either n-type or p-type work function layers, depending on the type of the corresponding GAA transistor. In one embodiment, the n-type work function layer contains aluminum and the p-type work function layer does not contain aluminum (or, when both are present, has less aluminum than the n-type work function metal). In one embodiment, when both n-type and p-type work function layers are present, the n-type work function layer has less nitrogen than the p-type work function layer.

[0118] In some embodiments, step 1010 is optional. For example, instead of forming a work function layer to regulate the critical voltage, a dipole treatment can be performed to directly change the work function of the high-dielectric-constant dielectric deposited in different devices. The dipole treatment may involve depositing an n-doped or p-doped dipole layer for the different devices, and then thermally driving the corresponding dopant of the dipole layer into the corresponding high-dielectric-constant dielectric layer of the different devices. In some embodiments, the dipole layer can then be removed before proceeding to step 1012.

[0119] In step 1012, operation 116 can be performed on the work function metal (if present) (see example). Figures 17-19A gate fill metal is formed above the work function layers 115 and 117 (see example). Figures 17-19 (Gate filling 119 in the middle). As previously described, the metal filling layer comprises a suitable conductive material, such as Al, W and / or Cu. The metal filling layer may additionally or collectively comprise other metals, metal oxides, metal nitrides, other suitable materials or combinations thereof.

[0120] Figures 17-19 Semiconductor devices 200 having first and second GAA devices according to different embodiments of the present invention are shown, the first and second GAA devices having a shared metal gate structure 308. In each of these embodiments, the first and second GAA devices each have a respective stack of square channels 240 above a protrusion 202a of a substrate 202, a gate dielectric layer 260 surrounding each semiconductor channel 240, and a gate electrode 120 above the gate dielectric layer 260. Figures 17-19 The different embodiments shown illustrate different device configurations depending on design requirements. While it is generally expected that both the first and adjacent second GAA devices will have gate dielectric layers with thicker portions at the channel corners, this is not always possible. For example, adjacent GAA devices may result in thinner portions of the gate dielectric layer at the channel corners due to patterning losses over multiple patterning cycles, over-etching due to patterning defects, and / or other manufacturing cost issues (see, for example). Figure 18 and Figure 19 However, in all embodiments, at least one of the two adjacent devices can have a thicker insulator at the channel corner. Furthermore, to meet performance requirements, devices requiring greater performance margin will have a thicker insulator at the channel corner, while devices requiring less performance can adjust in other ways, such as using a specific work function metal (see, for example, [link to relevant documentation]). Figure 19 ).

[0121] Now refer to Figure 17 In the illustrated embodiment, each square channel 240 in the first and second GAA devices contains information about... Figures 14A-15A The described gate dielectric layer 260 (i.e., the thicker portion at the channel corner) is surrounded and bordered by the same work function layer 115. The work function layer 115 may be a p-type work function layer for a p-type GAA device or an n-type work function layer for an n-type GAA device. A gate filler 119 is formed over the work function layer 115. In this embodiment, the work function layer 115 and the gate filler 119 together form a gate electrode 120 disposed over the gate dielectric layer 260. In another embodiment, the gate electrode 120 includes an additional conductive layer.

[0122] Now refer to Figure 18In the illustrated embodiment, the square channel 240 in the first GAA device includes information about Figures 14A-15A The described gate dielectric layer 260 (i.e., the thicker portion at the channel corner), and the square channel 240 in the second GAA device contain information regarding... Figures 14B to 15B The described gate dielectric layer 260 (i.e., the thinner portion at the channel corner) is surrounded and bordered by the same work function layer 115. The work function layer 115 may be a p-type work function layer for a p-type GAA device or an n-type work function layer for an n-type GAA device. A gate filler 119 is formed over the work function layer 115. In this embodiment, the work function layer 115 and the gate filler 119 together form a gate electrode 120 disposed over the gate dielectric layer 260. In another embodiment, the gate electrode 120 includes an additional conductive layer.

[0123] Now refer to Figure 19 In the illustrated embodiment, the square channel 240 in the first GAA device includes information about Figures 14A-15A The described gate dielectric layer 260 (i.e., the thicker portion at the channel corner), and the square channel 240 in the second GAA device contain information regarding... Figures 14B to 15B The described gate dielectric layer 260 (i.e., the thinner portion at the channel corner) is shown. In this embodiment, the gate dielectric layer 260 in the first and second GAA devices borders different work function layers 115 and 117. Work function layer 115 surrounds and borders the gate dielectric layer 260 of the first GAA device, and work function layer 117 surrounds and borders the gate dielectric layer 260 of the second GAA device. Note that work function layer 115 may also be disposed above work function layer 117, but separated from the gate dielectric layer 260 of the second GAA device by work function layer 117. Work function layers 115 and 117 are work function layers of opposite types. For example, work function layer 115 may be a p-type work function layer for a p-type GAA device, and work function layer 117 may be an n-type work function layer for an n-type GAA device, or vice versa. Gate filler 119 is formed above work function layer 115. In this embodiment, the work function layer 115, the work function layer 117, and the gate filler 119 together form the gate electrode 120 disposed above the gate dielectric layer 260. In another embodiment, the gate electrode 120 includes an additional conductive layer.

[0124] This invention provides advantages for GAA devices, but is not limiting. One example advantage is forming a GAA device with more square channels to improve performance. Another example advantage is forming a non-conformal interface layer with selectively thicker portions to mitigate external electric fields at the channel rounded corners. Another example advantage is forming a non-conformal high-dielectric-constant dielectric layer with selectively thicker portions around the interface layer to further mitigate external electric fields at the channel rounded corners. Yet another example advantage is selectively forming a non-conformal gate dielectric layer according to design requirements in the case of a shared gate structure.

[0125] One aspect of this invention relates to a method for forming a semiconductor device. This method includes forming a stack of semiconductor channels over semiconductor fins, wherein each of the semiconductor channels is a square with rounded corners, and the rounded corners intersect between a vertical surface and a horizontal surface of the semiconductor channel; forming a non-conformal interface layer over and surrounding each semiconductor channel of the stack of semiconductor channels, wherein the interface layer has a thicker portion located at the corner portions of the semiconductor channels and a thinner portion located at the non-corner portions of the semiconductor channels; forming a non-conformal high-dielectric-constant dielectric layer over and surrounding the non-conformal interface layer, wherein the high-dielectric-constant dielectric layer has a thicker portion on the thicker portion of the interface layer and a thinner portion on the thinner portion of the interface layer; and forming a gate electrode over the high-dielectric-constant dielectric layer.

[0126] In one embodiment, the semiconductor channel is formed having channel sidewalls having vertical sidewall portions and rounded corner portions, wherein the percentage of the vertical sidewall portions is greater than the percentage of the rounded corner portions. In a further embodiment, the percentage of the rounded corner portions is from about 5% to about 50% of the channel sidewalls.

[0127] In one embodiment, the formation of the non-conformal interface layer involves thermally growing an oxide on each semiconductor channel of the stacked semiconductor channels. In another embodiment, the oxide is grown at a temperature of about 500°C to about 950°C. In yet another embodiment, the oxide is grown by introducing oxygen at a pressure ranging from 0.02% to 100% [O] / N2 in the range of 1 Torr to 25 atm.

[0128] In one embodiment, the formation of a non-conformal high-dielectric-constant dielectric layer comprises depositing a high-dielectric-constant dielectric via atomic layer deposition (ALD). In another embodiment, the high-dielectric-constant dielectric is hafnium oxide deposited by sequentially applying a first precursor and a second precursor, wherein the first precursor is one or more of HfCl4, TEMA-Hf, or TDMA-Hf, and the second precursor is one or more of H2O, H2O2, O3, or O2. In yet another embodiment, the high-dielectric-constant dielectric is deposited according to diffusion-limited rules.

[0129] Another aspect of this invention relates to a method for forming a semiconductor device. This method includes: first thermally grown oxide over and surrounding a semiconductor channel; performing wet chemical cleaning to remove contaminants generated during the first thermal growth; second thermally grown oxide to form an interface layer; depositing a high-k dielectric material over the interface layer by atomic layer deposition (ALD); and thermally annealing the high-k dielectric material to form a high-k dielectric layer. The interface layer and the high-k dielectric layer together form a gate dielectric layer, wherein the gate dielectric layer is formed having a thicker portion located at a corner of the semiconductor channel and a thinner portion located at a non-corner portion of the semiconductor channel.

[0130] In one embodiment, the interface layer is formed having a thicker portion located at the corner of the semiconductor channel and a thinner portion located at the non-corner of the semiconductor channel.

[0131] In one embodiment, the high dielectric constant dielectric layer is formed having a thicker portion around the corner portion of the semiconductor channel and a thinner portion around the non-corner portion of the semiconductor channel.

[0132] In one embodiment, after thermally annealing the high-dielectric-constant dielectric material, the method further includes depositing a second high-dielectric-constant dielectric material over the high-dielectric-constant dielectric material; and thermally annealing the second high-dielectric-constant dielectric material and the high-dielectric-constant dielectric material to form a high-dielectric-constant dielectric layer.

[0133] In one embodiment, the first thermal growth involves growing an oxide at a temperature of about 500°C to about 950°C.

[0134] In one embodiment, depositing a high dielectric constant dielectric material involves depositing a high dielectric constant dielectric material under diffusion-limited rules, such that the Thiele modulus Φ is much greater than 1.

[0135] Another aspect of this invention relates to a semiconductor device. This semiconductor device includes a stack of semiconductor channels located above a substrate, wherein at least one of the stacked semiconductor channels includes a channel sidewall defined by a vertical portion and a rounded corner portion, wherein the vertical portion constitutes a majority of the channel sidewall; an interface layer covering each semiconductor channel of the stack surrounding the semiconductor channels, wherein the interface layer has a thicker portion located at a corner portion of the semiconductor channel and a thinner portion located at a non-corner portion of the semiconductor channel; a high-dielectric-constant dielectric layer located above and covering the interface layer, wherein the high-dielectric-constant dielectric layer has a thicker portion located on the thicker portion of the interface layer and a thinner portion located on the thinner portion of the interface layer; and a gate electrode located above the high-dielectric-constant dielectric layer.

[0136] In one embodiment, the thinner portion of the interface layer is approximately to approximately The range.

[0137] In one embodiment, the thickness difference between the thicker portion and the thinner portion of the interface layer is approximately... to approximately The range.

[0138] In one embodiment, the thinner portion of the high dielectric constant dielectric layer is approximately to approximately The range.

[0139] In one embodiment, the thickness difference between the thicker portion and the thinner portion of the high-dielectric-constant dielectric layer is approximately... to approximately The range.

[0140] The accompanying drawings describe the details of the method and apparatus of this invention. Components of several embodiments are outlined to enable those skilled in the art to better understand the various aspects of this invention. Those skilled in the art will understand that they can easily design or modify other processes and structures based on this invention to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent structures do not depart from the spirit and scope of this invention, and that they can make various changes, substitutions, and adjustments without departing from the spirit and scope of this invention.

Claims

1. A semiconductor device, characterized in that: A stack of multiple semiconductor channels is located above a substrate, wherein at least one semiconductor channel of the stack includes multiple channel sidewalls defined by multiple vertical portions and multiple rounded portions, wherein the multiple vertical portions constitute the majority of the multiple channel sidewalls; An interface layer covers each of the semiconductor channels in the stack surrounding the plurality of said semiconductor channels, wherein the interface layer has a thicker portion located at a plurality of corner portions of the semiconductor channel and a thinner portion located at a plurality of non-corner portions of the semiconductor channel; A high dielectric constant dielectric layer is located above and surrounds the interface layer, wherein the high dielectric constant dielectric layer has a thicker portion on the thicker portion of the interface layer and a thinner portion on the thinner portion of the interface layer; and A gate electrode is located above the high dielectric constant dielectric layer.

2. The semiconductor device as claimed in claim 1, characterized in that, The thinner portion of the interface layer is in the range of to .

3. The semiconductor device as claimed in claim 1, characterized in that, The thickness difference between the thicker portion and the thinner portion of the interface layer is to The range.

4. The semiconductor device as claimed in claim 1, characterized in that, The thinner portion of the high dielectric constant dielectric layer is in to The range.

5. The semiconductor device as claimed in claim 1, characterized in that, The thickness difference between the thicker portion and the thinner portion of the high-dielectric-constant dielectric layer is... to The range.

6. The semiconductor device as claimed in claim 1, characterized in that, The percentage of the plurality of vertical portions is greater than the percentage of the plurality of rounded portions.

7. The semiconductor device as claimed in claim 6, characterized in that, The percentage of the plurality of said rounded corner portions is 5% to 50% of the plurality of said channel sidewalls.

8. The semiconductor device as claimed in claim 1, characterized in that, The ratio of the thicker portion of the interface layer to the thinner portion of the interface layer is in the range of 1.05 to 1.

17.

9. The semiconductor device as claimed in claim 1, characterized in that, The ratio of the thicker portion of the high dielectric constant dielectric layer to the thinner portion of the high dielectric constant dielectric layer is in the range of 1.05 to 1.

17.

10. The semiconductor device as claimed in claim 1, characterized in that, The thicker portion of the interface layer is in to The range, and the thinner portion of the high dielectric constant dielectric layer in to The range.

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