Integrated circuit assembly

Abstract

The utility model provides a kind of integrated circuit assembly.Integrated circuit assembly includes integrated circuit layer, and integrated circuit layer includes substrate.The substrate includes multiple light detectors close to the first side of substrate and multiple floating diffusion regions between light detector and adjacent to the first side of substrate.Integrated circuit layer further includes multiple conductive structures located in dielectric layer.Dielectric layer includes first side positioned on the first side of substrate.The conductive structure includes multiple conductive bonding structures on the second side of dielectric layer.The second side of dielectric layer is opposite the first side of dielectric layer.The conductive structure further includes multiple conductive contact structures.Each conductive contact structure connects corresponding floating diffusion region to corresponding conductive bonding structure.

Description

Technical Field

[0001] This utility model relates to an integrated circuit component. Background Technology

[0002] In some complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) components, multiple circuit chips or circuit layers can be employed to increase pixel density. For example, a first circuit layer may include a photodetector and its associated transmission gate structure, while a second circuit layer may include selection and frequency circuitry for measuring the amount of light received by a selected photodetector. These circuits can be integrated into a single CIS integrated circuit (IC) component to reduce the footprint of the component on a printed circuit board (PCB). Utility Model Content

[0003] Some embodiments of this utility model provide an integrated circuit assembly. The integrated circuit assembly includes a first integrated circuit layer, the integrated circuit layer including a first substrate. The substrate includes a plurality of photodetectors adjacent to a first side of the substrate and a plurality of floating diffusion regions located between the plurality of photodetectors and adjacent to the first side of the substrate. The integrated circuit layer also includes a plurality of first conductive structures located within a dielectric layer, the dielectric layer including a first side located on the first side of the substrate. The plurality of first conductive structures include a plurality of first conductive bonding structures located on a second side of the dielectric layer, the second side of the dielectric layer being opposite to the first side of the dielectric layer. The plurality of first conductive structures also include a plurality of first conductive contact structures. Each of the plurality of first conductive contact structures connects a corresponding one of the plurality of floating diffusion regions to a corresponding one of the plurality of first conductive bonding structures.

[0004] Some embodiments of this utility model provide another integrated circuit assembly. The integrated circuit assembly includes a first integrated circuit layer, the first integrated circuit layer including a first substrate. The first substrate includes a photodetector and a floating diffusion region adjacent to a first side of the first substrate, and a first conductive structure located within a first dielectric layer. The first dielectric layer includes a first side located on the first side of the substrate. The first conductive structure includes a first conductive bonding structure located on a second side of the dielectric layer, the second side of the dielectric layer opposite to the first side of the dielectric layer, and a first conductive contact structure connecting the first side of the substrate to the first conductive bonding structure at the floating diffusion region.

[0005] Some embodiments of this utility model provide a method for forming an integrated circuit assembly. The method includes: forming a photosensitive region in a substrate of a first integrated circuit layer; forming a floating diffusion region adjacent to the photosensitive region in the substrate; forming a transmission gate structure adjacent to the photosensitive region and the floating diffusion region on the substrate; forming a dielectric layer on the substrate and the transmission gate structure; forming a first trench in the dielectric layer extending to the floating diffusion region; forming a second trench in the dielectric layer extending to the transmission gate structure; forming a first conductive contact structure in the first trench and a second conductive contact structure in the second trench; forming a first conductive bonding structure on the dielectric layer above the first conductive contact structure; and forming a second conductive bonding structure on the dielectric layer above the second conductive contact structure.

[0006] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0007] The best understanding of the present invention will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 This is a schematic exploded isometric view illustrating a CIS multi-die (e.g., multilayer) IC component according to some embodiments of the present invention.

[0009] Figure 2A This is a block diagram illustrating pixel cells that can be used in CIS multilayer IC components according to some embodiments of the present invention.

[0010] Figure 2B This is a schematic diagram illustrating pixel cells that can be used in CIS multilayer IC components according to some embodiments of the present invention.

[0011] Figure 3 This is a schematic / block diagram illustrating a pixel cell, including a floating diffusion node, pixel circuits, and in-pixel circuits, which can be used in a multilayer CISIC component according to some embodiments of the present invention.

[0012] Figure 4 This is a block diagram illustrating a multilayer CISIC assembly according to some embodiments of the present invention.

[0013] Figure 5A and Figure 5B These are cross-sectional and plan views of a multilayer CIS IC component employing a floating diffusion node structure with reduced capacitance, as illustrated in some embodiments of the present invention.

[0014] Figure 6A and Figure 6B These are cross-sectional and plan views of another multilayer CISIC component employing a floating diffusion node structure with reduced capacitance, as illustrated in some embodiments of the present invention.

[0015] Figure 7A and Figure 7B These are cross-sectional and plan views of another multilayer CISIC component employing a floating diffusion node structure with reduced capacitance, as illustrated in some embodiments of the present invention.

[0016] Figure 8A and Figure 8B These are cross-sectional and plan views of another multilayer CISIC component employing a floating diffusion node structure with reduced capacitance, as illustrated in some embodiments of the present invention.

[0017] Figures 9A to 9F This is a side cross-sectional view illustrating the upper IC layer of a CIS employing a floating diffusion node structure with reduced capacitance at various stages of manufacturing, according to some embodiments of the present invention.

[0018] Figure 10 The illustrations are based on some embodiments of this utility model. Figure 9F A cross-sectional view of the initial state of the lower IC layer of the CIS before the upper IC layer of the CIS.

[0019] Figure 11 The diagram is drawn according to this utility model before joining. Figure 5A and Figure 5B Cross-sectional views of the lower IC layer and the upper IC layer of the CIS.

[0020] Figure 12 The diagram is drawn according to this utility model before joining. Figure 6A and Figure 6B Cross-sectional views of the lower IC layer and the upper IC layer of the CIS.

[0021] Figure 13 The diagram is drawn according to this utility model before joining. Figure 7A and Figure 7B Cross-sectional views of the lower IC layer and the upper IC layer of the CIS.

[0022] Figure 14 The diagram is drawn according to this utility model before joining. Figure 8A and Figure 8B Cross-sectional views of the lower IC layer and the upper IC layer of the CIS.

[0023] Figure 15 This invention describes a method for forming a CIS polycrystalline IC component employing a floating diffusion node structure with reduced capacitance. Detailed Implementation

[0024] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of the present invention. Such repetition is for the purpose of brevity and clarity, and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0025] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and similar expressions may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein will be interpreted accordingly.

[0026] In complementary metal-oxide-semiconductor (CMOS) image sensors (CIS), a potential area of ​​concern is the capacitance associated with the conductive connections of floating diffusion nodes related to one or more pixels of the sensor. More specifically, the floating diffusion nodes carry a charge related to the amount of light affecting the photodetector, generating a voltage input to the CIS processing circuitry. Therefore, relatively long electrical connections from the floating diffusion nodes to the processing circuitry can correspond to higher capacitance values, which may result in lower pixel performance (e.g., reduced conversion gain from the amount of received light to a representative voltage level).

[0027] To address these issues, embodiments of the present invention provide a polycrystalline CISIC component with a floating diffusion node structure that reduces capacitance. In some embodiments, the first IC layer of the IC component may include a substrate including a photodetector and a floating diffusion region adjacent to a first side of the substrate. The substrate may also include a conductive structure located within a dielectric layer. The dielectric layer may include a first side (e.g., a front side) positioned on the respective first side of the substrate. The conductive structure may include a conductive bonding structure on a second side (e.g., a back side) of the dielectric layer relative to the first side, and a conductive contact structure connecting the side containing the floating diffusion region of the substrate to the conductive bonding structure.

[0028] Furthermore, in some embodiments, the conductive bonding structure of the first IC layer may be bonded to a corresponding bonding structure of the second IC layer (e.g., electrically connecting the floating diffusion region to the associated processing circuitry in the second IC layer).

[0029] Therefore, some embodiments can provide CISIC components in which the capacitance level associated with the floating diffusion node can be significantly reduced, thereby improving the conversion gain of the corresponding pixel cell. Furthermore, employing the above-described floating diffusion node structure (embodiments of which will be described in more detail below) can also lead to a reduction in the overall manufacturing cost of the CISIC component.

[0030] Figure 1 This is a schematic exploded isometric view illustrating a CIS multi-die IC assembly according to some embodiments of the present invention. The CIS multi-die IC assembly (hereinafter also referred to as CISIC assembly 100) includes an upper (or first) IC die (or simply IC layer 102A) and a lower (or second) IC die (or simply IC layer 102B) bonded together. In some embodiments, the CISIC assembly 100 may include an additional lower IC layer to provide additional functionality within a given IC assembly footprint. In some embodiments, the upper IC layer 102A and the lower IC layer 102B are bonded at the wafer level (e.g., bonded to each other before being monomerized into individual ICs). In other embodiments, one or more of the upper IC layer 102A and the lower IC layer 102B are bonded to each other according to a die-to-wafer or flip-chip bonding method.

[0031] In some embodiments, the upper IC layer 102A includes a pixel array 103, which includes a plurality of pixel cells 104 organized into a plurality of pixel cell groups 105. Each pixel cell 104 is capable of sensing light 101 incident on the upper surface (e.g., the back surface) of the upper IC layer 102A. Furthermore, the upper IC layer 102A may include a floating diffusion structure 106 (e.g., a type of floating diffusion structure) to reduce capacitance. Figure 5A , Figure 6A , Figure 7A , Figure 8AThe floating diffusion structures 106A, 106B, 106C, and 106D shown below will be described in more detail in their embodiments. Furthermore, in some embodiments, the upper IC layer 102A may include additional circuitry that can be integrated with the pixel cell 104. Additionally, the lower IC layer 102B may include processing circuitry (not shown in the diagram). Figure 1 (As shown in the figure), these processing circuits can be applied together (e.g., to generate image data representing the light 101 received in pixel cell 104). In some embodiments, pixel cell 104 and other circuits are organized in different IC layers 102A and IC layer 102B as described below, and each such IC layer can be formed using a manufacturing process or technology node suitable for the relevant circuits.

[0032] Figure 2A This is a block diagram illustrating a pixel cell 104 that can be used in a CIS IC component 100 according to some embodiments of the present invention. In these embodiments, the pixel cell 104 may include a photodetector 202 that provides a photodetector value 206 (e.g., charge amount), and a transmission transistor 204 that forwards this value as a transmission output 210 under the control of a transmission input 208. In some embodiments, as described below, the photodetector 202 may include a photodiode 302, such as a PIN diode or a pinned photodiode (PPD). However, in other embodiments, the photodetector 202 may be a phototransistor or other type of photodetector. In some embodiments, the pixel cell 104 may be assigned to detect different wavelength ranges (e.g., grouped into red, blue, and green pixels) by means of positioning on Figure 1 The corresponding color filter is associated with the upper IC layer 102A. Furthermore, while the photodetector 202 may be sensitive to a range or some ranges of a specific visible light band, in other embodiments, the photodetector 202 may be sensitive to non-visible light (e.g., infrared light).

[0033] Figure 2B This is a schematic diagram illustrating pixel cells 104 that can be used in a CIS IC component 100 according to some embodiments of the present invention. Figure 2B As shown, pixel cell 104 may include a photodiode 302, whose anode is connected to ground voltage GND (e.g., connected to source reference voltage (VSS)), and whose cathode provides a photodetector value 206 to a first source / drain region of transfer transistor 204. Furthermore, transfer transistor 204 may respond to a transfer input 208 at its gate input (in... Figure 2BThe signal (also labeled as TX) transmits the photodetector value 206 to the transmission output 210 of the second source / drain region. In some embodiments, the second source / drain region of the transmission transistor 204 may serve as a floating diffusion (FD) region, forming part of a floating diffusion node extending between the upper IC layer 102A and the lower IC layer 102B.

[0034] Figure 3 This describes an embodiment in which pixel cells 104 and associated processing circuitry can be organized or distributed across the three IC layers of a CIS IC component (e.g., to facilitate improved component performance and / or cost). More specifically, Figure 3 This is a schematic / block diagram illustrating a pixel cell 104, pixel circuits 308, and in-pixel circuits 310 that can be employed in a multilayer CIS IC assembly, according to some embodiments of the present invention. As shown, the pixel cell 104, as described above, including a photodetector (e.g., a photodiode 302) and a transmission transistor 204, is contained in an upper IC layer 102A. Furthermore, the pixel circuits 308 and in-pixel circuits 310 are located on a lower IC layer 102B, while additional circuitry is located on one or more additional lower IC layers 102C.

[0035] Although Figure 3 The document depicts a single pixel cell 104 and a single pixel circuit 308, but at least some embodiments described herein include multiple pixel cells 104 (e.g., organized into pixel cell groups 105, which may include, for example,...). Figure 1 The diagram shows multiple columns and rows of pixel cells 104 and multiple pixel circuits 308, wherein each pixel circuit 308 is electrically coupled to a corresponding pixel cell 104. Figure 3 It is also shown that each pixel circuit 308 can be coupled to the pixel-in-pixel circuit 310.

[0036] In some embodiments, each pixel circuit 308 is configured to provide a frequency indication of the charge (e.g., transfer output 210) transferred from the photodiode 302 of the corresponding pixel cell 104 via the transfer transistor 204. For example, in some embodiments, each pixel circuit 308 may include a source follower transistor 304, a row select transistor 306, and / or a reset transistor 307. The source follower transistor 304 may be electrically coupled to the transfer transistor 204 (e.g., connected at the gate of the source follower transistor 304) and is configured to provide a buffer between the transfer transistor 204 (e.g., transfer output 210) and another circuit (e.g., within the pixel-in-circuit 310, such as a column bus). In some embodiments, the source follower transistor 304 may be configured as an amplifier of the transfer output 210. In some examples, the gate connection of the source follower transistor 304 may be considered as a floating diffusion region where charge is provided and then transferred to the pixel-in-circuit 310.

[0037] The reset transistor 307 may also be coupled to the source follower transistor 304 (e.g., at the gate connection of the source follower transistor 304) to reset the charge transferred from the photodiode 302 by the transfer transistor 204 under the control of the reset signal RST (e.g., by raising the gate connection of the source follower transistor to the drain (supply) voltage VDD).

[0038] In some embodiments, the row selection transistor 306 may be configured to transfer charge from pixel cell 104 to in-pixel circuitry 310 via source follower transistor 304 in a timed manner based on a row selection signal RS (e.g., driving the gate connection of row selection transistor 306). Furthermore, in some embodiments, the row selection transistor 306 may couple source follower transistor 304 to the column bus of in-pixel circuitry 310 via a drain / source connection.

[0039] In some embodiments, the in-pixel circuitry 310 may process multiple frequency indications of charge received by the source follower transistor 304 (e.g., processing column-by-column of multiple columns of pixel cells 104) to at least partially generate analog image data represented by the charge stored in the pixel cells 104. In some embodiments, the in-pixel circuitry 310 may generate signals (e.g., signals TX, RST, RS) that control the pixel cells 104 and each pixel circuitry 308 as described above. More broadly, in some embodiments, the in-pixel circuitry 310 may include one or more column-level circuits, column bus signal lines (e.g., one signal line per column), one or more bias transistors (e.g., for applying voltage levels to one or more column bus signal lines), a column controller, and a row controller.

[0040] In some embodiments, the additional lower IC layer 102C may include any additional circuitry (e.g., one or more analog-to-digital (ADC) converters, memory, image signal processors (ISP) processors, communication circuitry, power supply circuitry, and / or similar components) that may be used as part of or associated with the CIS IC component 100.

[0041] Figure 4 This is a block diagram illustrating a multilayer CISIC component 100 according to some embodiments of the present invention. For example, in Figure 4 In the CIS IC component 100A, there is an upper IC layer 102A containing pixel cells 104, and a lower IC layer 102B containing pixel circuits 308 and in-pixel circuits 310 (e.g., as described above in conjunction with the above). Figure 3 (As discussed). Although Figure 4 While not explicitly shown, in some embodiments, the CISIC component 100 may also include one or more additional lower IC layers, which may include power supply circuitry (e.g., for providing, filtering, and / or distributing power to the CMOS image sensor integrated circuit component 100), one or more memories (e.g., for storing digital image data represented in pixel cells 104), and / or column ADCs (for converting frequency indications of the charge of pixel cells 104 into digital image data per column of pixel cells 104). In some embodiments, the CISIC component 100 may include additional lower IC layers ( Figure 4 (Not explicitly shown in the text) These layers contain additional circuitry, such as phased-locked loops (PLLs) (e.g., for generating frequency signals for in-pixel circuitry 310 and other parts of the CIS IC component 100), inter-integrated circuitry (I2C) (e.g., for providing communication between the CIS IC component 100 and other circuitry or systems), and ISPs (e.g., for processing digital image data generated from charges in pixel cells 104).

[0042] In some embodiments, the distinction between the upper IC layer 102A, the lower IC layer 102B, and potentially additional lower IC layers simplifies the manufacturing of each individual IC layer because it reduces the number of different process technologies required to produce each individual IC layer. For example, in Figure 4In this embodiment, the upper IC layer 102A can be fabricated using at least one specialized process specifically designed for creating pixel cells 104 (e.g., to minimize the footprint of each pixel cell 104). Furthermore, in some embodiments, the lower IC layer 102B can be fabricated using at least one low-power technology node (e.g., to implement individual pixel circuitry 308 and in-pixel circuitry 310). In some embodiments, additional lower IC layers can be implemented using at least one high-voltage (e.g., thick oxide) technology (e.g., to accommodate the relatively high voltage levels of power supply circuitry and / or column ADCs). In some embodiments, more than one technology node can be used to form one or more IC layers. However, using more than one IC layer may help prevent the use of three or more process technology nodes to form any single IC layer.

[0043] Figure 5A and Figure 5B , Figure 6A and Figure 6B , Figure 7A and Figure 7B as well as Figure 8A and Figure 8B Each pair of figures is a cross-sectional view and a plan view, respectively, illustrating a multilayer CISIC assembly employing a floating diffusion node structure with reduced capacitance, according to some embodiments of the present invention. In some embodiments, although the floating diffusion node structure may be associated with a single pixel, in the embodiments described below, pixel cells 104 of a particular pixel cell group 105 may share a single floating diffusion region and associated node structure. More specifically, Figure 5A and Figure 5B The pixel cell group 105A is depicted. Figure 6A and Figure 6B The pixel cell group 105B was depicted. Figure 7A and Figure 7B The pixel cell group 105C was depicted. Figure 8A and Figure 8B Pixel cell groups 105D are depicted, each employing a floating diffuse node structure extending within and between the upper IC layer 102A and the lower IC layer 102B. Furthermore, each pair of figures depicts a single pixel cell group 105 in the upper IC layer 102A, comprising a two-by-two configuration of four pixel cells 104.

[0044] Figure 5A , Figure 6A , Figure 7A and Figure 8AThe diagram further illustrates a lens 520 (e.g., a microlens) and a filter 518, wherein a lens 520 and an associated filter 518 may be configured above a corresponding pixel cell 104 to focus and subsequently filter light supplied to that pixel cell 104. In some embodiments, each pixel cell group 105 may include filters of different colors (e.g., red, green, and blue). Furthermore, in some embodiments, one or more pixel cell groups 105 may include one red, two green, and one blue filter. However, in other embodiments, the filter 518 may be associated with combinations of other colors or wavelength bands.

[0045] exist Figure 5A , Figure 6A , Figure 7A and Figure 8A In this configuration, the upper IC layer 102A may include a substrate 502 and a dielectric layer 504. In some embodiments, the substrate 502 of the upper IC layer 102A and the substrate 502 of the first lower IC layer 102B may be semiconductor substrates, which may include silicon (Si) and / or other semiconductor materials. Furthermore, in some embodiments, the dielectric layer 504 of the upper IC layer 102A and the dielectric layer 504 of the lower IC layer 102B may include one or more dielectric materials, including but not limited to silicon oxide (SiO2). x (e.g., silicon dioxide (SiO2)), silicon nitride (SiN), silicon carbide (SiC), carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphorus silicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), porous dielectric materials or the like.

[0046] Regarding these identical diagrams, the substrate 502 of the upper IC layer 102A may provide a photosensitive region 506 for each pixel cell 104 of the pixel cell groups 105A, 105B, 105C, and 105D. Each photosensitive region 506 may form a corresponding photodetector with the surrounding area of ​​the substrate 502 (e.g., Figure 3 (Photodiode 302). In some embodiments, a photosensitive region 506 is formed near the lower side or surface (e.g., the first or front surface) of the substrate 502, and the dielectric layer 504 of the upper IC layer 102A is disposed adjacent to that surface.

[0047] like Figure 5A , Figure 6A , Figure 7Aand Figure 8A As shown, the substrate 502 also includes a floating diffusion region 501 disposed on or near the lower surface (e.g., the first or front side) of the substrate 502, and adjacent to at least one pixel cell 104. In some embodiments, such as Figure 5B , Figure 6B , Figure 7B and Figure 8B As depicted in the plan view, the floating diffusion region 501 is located between individual pixel cells 104 (e.g., approximately at the center of pixel cell groups 105A, 105B, 105C, 105D). Therefore, in some embodiments, the floating diffusion region 501 is shared by the pixel cells 104 of each pixel cell group 105A, 105B, 105C, and 105D (e.g., shared on a time-division basis). The function of the floating diffusion region 501 is described above in conjunction with... Figure 2B and Figure 3 It has been described in detail.

[0048] Furthermore, in some embodiments, within the dielectric layer 504, on the upper side (e.g., the first side) or surface near the first side or surface of the substrate 502, the transfer gate structures 508A, 508B, 508C, 508D (e.g., gate oxide materials having connecting conductive structures (e.g., polysilicon, metal conductors, or other conductive materials), possibly also having spacer wall structures) may be adjacent to the photosensitive region 506 and the floating diffusion region 501 to form corresponding pixel cells 104. Additionally, as... Figure 5B , Figure 6B , Figure 7B and Figure 8B As depicted in the plan view, each transmission gate structure 508A, 508B, 508C, 508D may be located at or near the corner of the corresponding pixel cell 104 closest to the central region of the associated pixel cell group 105A, 105B, 105C, 105D. Meanwhile, in some embodiments, each transmission gate structure 508A, 508B, 508C, 508D is located in... Figure 5B , Figure 6B , Figure 7B and Figure 8B The planar diagram may be triangular (e.g., in the form of a right triangle, with its right angle closest to the central region of the corresponding pixel cell group 105A, 105B, 105C, 105D). However, in other embodiments, the transmission gate structures 508A, 508B, 508C, 508D may have other positions, arrangements, and shapes.

[0049] In some embodiments, the dielectric layer 504 of the upper IC layer 102A may include multiple conductive bonding structures on its underside (e.g., the second side) or surface (opposite to the substrate 502). Furthermore, the dielectric layer 504 of the upper IC layer 102A may include conductive contact structures that electrically connect portions of the pixel cell 104 to the conductive bonding structures of the upper IC layer 102A. More specifically, in some embodiments, such as... Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A and Figure 8B As shown, conductive contact structure 517 may connect the floating diffusion region 501 on the first surface of dielectric layer 504 to the conductive bonding structure 522 on the second surface of dielectric layer 504. Additionally, in some embodiments, conductive contact structures 515A, 515B, 515C, and 515D may connect corresponding transmission gate structures 508A, 508B, 508C, and 508D to associated conductive bonding structures 513A, 513B, 513C, and 513D, respectively. In some embodiments, conductive bonding structures 513A, 513B, 513C, and 513D may extend parallel to each other in the lateral direction in a planar view within pixel cell groups 105A, 105B, 105C, and 105D, and may further extend into associated pixel cell group columns containing pixel cell groups 105A, 105B, 105C, and 105D.

[0050] In addition, such as Figure 5B , Figure 6B , Figure 7B and Figure 8B As shown (but in Figure 5A , Figure 6A , Figure 7A and Figure 8A (Not explicitly depicted), the conductive contact structure 542 may connect the first surface of the substrate 502 to the conductive bonding structure 544 on the second surface of the dielectric layer 504. In some embodiments, the conductive contact structure 542 and the conductive bonding structure 544 constitute at least a portion of the reference voltage (e.g., ground) connection path of the photodetector for each pixel cell 104 in the corresponding pixel cell groups 105A, 105B, 105C, 105D.

[0051] In some embodiments, the conductive structure disposed in the dielectric layer 504 may include a metal (e.g., copper (Cu) or aluminum (Al)) or other conductive materials.

[0052] Furthermore, in some embodiments, additional dielectric structures may be configured in the upper IC layer 102A to at least partially isolate each pixel cell 104 from other pixel cells 104, and possibly from other portions of the upper IC layer 102A. These dielectric structures will not be described or discussed further herein.

[0053] like Figure 5A , Figure 6A , Figure 7A and Figure 8A The lower IC layer 102B depicted includes its own substrate 502 (e.g., a silicon substrate or other semiconductor substrate) and dielectric layer 504. In the lower IC layer 102B, the substrate 502 may include at least a portion of one or more processing circuits. In some embodiments, these processing circuits may include… Figure 3 Multiple pixel circuits 308 are included, such as source follower transistors 304, row selection transistors 306, and / or reset transistors 307. Furthermore, in some embodiments, the processing circuitry may include polysilicon capacitors 530, conversion gain circuitry 532 (e.g., high / medium / low conversion gain), voltage domain global shutter circuitry 534, and / or other circuitry.

[0054] In the dielectric layer 504 of the lower IC layer 102B, multiple conductive structures or groups of conductive components may be configured to connect various processing circuits (e.g., including source follower transistor 304, row select transistor 306, reset transistor 307, polysilicon capacitor 530, conversion gain circuit 532, and / or voltage domain global shutter circuit 534) to the conductive bonding structures 522, 513A, 513B, 513C, 513D, and / or other conductive structures of the upper IC layer 102A, or to each other. In some embodiments, such as Figure 5A , Figure 6A , Figure 7A and Figure 8A As shown, the conductive component assembly may include one or more conductive layers 524 and one or more conductive vias 525 arranged in an alternating pattern. Furthermore, in some embodiments, these conductive structures may include metals (e.g., copper (Cu) or aluminum (Al)) or other conductive materials.

[0055] In the dielectric layer 504 of the lower IC layer 102B, one or more conductive bonding structures may be located on the second surface of the dielectric layer 504. These conductive bonding structures may be arranged to connect the conductive structures in the dielectric layer 504 of the lower IC layer 102B to the conductive bonding structures 522, 513A, 513B, 513C, and 513D of the dielectric layer 504 of the upper IC layer 102A.

[0056] More specifically, in Figure 5A , Figure 6A , Figure 7A and Figure 8A In this embodiment, the dielectric layer 504 of the lower IC layer 102B includes a conductive bonding structure 523, which is bonded to the conductive bonding structure 522 on the second surface of the dielectric layer 504 of the upper IC layer 102A. Therefore, as... Figure 5A and Figure 7A As shown in the embodiment, the conductive path starts from the floating diffusion region 501, passes through the conductive contact structure 517 and conductive bonding structure 522 in the dielectric layer 504 of the upper IC layer 102A, then passes through the conductive bonding structure 523, one or more conductive layers 524 and one or more conductive vias 525 in the dielectric layer 504 of the lower IC layer 102B, and finally connects to the conversion gain circuit 532.

[0057] In addition, Figure 6A and Figure 8A In, not in Figure 5A and Figure 5B The additional conductive contact structure 617 shown is positioned between the conductive bonding structure 523 and the top conductive layer 524 of the dielectric layer 504 of the lower IC layer 102B. Therefore, the additional conductive contact structure 617 is used as part of a floating diffusion node, which is consistent with... Figure 5A and Figure 7A The corresponding structures differ. In some embodiments, the additional conductive contact structure 617 may help increase the flexibility of metal layer wiring in the dielectric layer 504 of the lower IC layer 102B and enable the use of smaller pixel cells 104 in the upper IC layer 102A.

[0058] Furthermore, in some embodiments, such as Figure 7A and Figure 8A As shown, in addition to the conductive bonding structure 523 of the dielectric layer 504 of the lower IC layer 102B, additional conductive bonding structures are provided, including conductive bonding structures 713A and 713B. As shown, conductive bonding structures 713A and 713B are bonded to conductive bonding structures 513A and 513B in the dielectric layer 504 of the upper IC layer 102A. Furthermore, in other embodiments, the additional conductive bonding structures of the lower IC layer 102B (not shown in the figure) Figure 7A and Figure 8A (As shown in the diagram) may be bonded to conductive bonding structures 513C, 513D. Meanwhile, in some embodiments, the conductive bonding structures 513A, 513B, 513C, 513D of the upper IC layer 102A may match the size and / or shape of the corresponding conductive bonding structures 713A, 713B, etc., of the upper IC layer 102B. Therefore, in some embodiments, using these additional conductive bonding structures in the lower IC layer 102B may enhance the robustness of the conductive (e.g., metal) bonding regions of the upper IC layer 102A and the lower IC layer 102B to mitigate electromigration of the associated conductive structures, potentially leading to improved reliability of the integrated circuit assembly.

[0059] Figure 5A , Figure 6A , Figure 7A and Figure 8A The diagram also shows that a three-dimensional metal-insulator-metal (3D-MIM) capacitor 526 is present in the conductive structure of the dielectric layer 504 of the lower IC layer 102B. In other embodiments, this capacitor may be omitted from the dielectric layer 504 of the lower IC layer 102B.

[0060] Figures 9A to 9F This illustration depicts the upper IC layer of a CMOS image sensor employing a reduced capacitance floating diffusion node structure, according to some embodiments of the present invention. Figure 5A , Figure 6A , Figure 7A and Figure 8A Cross-sectional side views of the upper IC layer 102A of the middle pixel cell groups 105A, 105B, 105C, and 105D at various stages of manufacturing. Although Figures 9A to 9F The operations are described as a series, but it should be understood that these operations are not limited, as the order of operations may be changed in other embodiments, and the disclosed methods are applicable to other structures. In other embodiments, some illustrated and / or described operations may be omitted in whole or in part.

[0061] Figure 9A A plurality of photosensitive regions 506 are illustrated formed (e.g., implanted or doped) on a first side or surface of a substrate 502. The substrate 502 may be a semiconductor substrate (e.g., a silicon (Si) substrate) serving as the base structure of an upper IC layer 102A of pixel cell groups 105A, 105B, 105C, or 105D of a CIS IC component 100. Each photosensitive region 506 may include a light-absorbing region that, in conjunction with the substrate 502, forms a photodetector (e.g., a photodiode) sensitive to a specific wavelength band. In some embodiments, the semiconductor substrate 502 may be p-type doped silicon, and the photosensitive region 506 may be a portion of the substrate 502 that has been ion implanted or doped to create an n-type doped region. In some embodiments, the photodiode generated by forming the photosensitive region 506 may be a PN photodiode (e.g., a "clamped" photodiode) sensitive to visible light photons. In addition, other doped regions, such as n-type doped floating diffusion regions 501 of the transfer transistors associated with the transfer gate structures 508A, 508B, 508C and 508D of each pixel cell group 105A, 105B, 105C or 105D, may be formed in the vicinity of the photosensitive region 506.

[0062] Figure 9BThe diagram illustrates transfer gate structures 508A, 508B, 508C, and 508D formed on substrate 502 (e.g., by deposition and photolithography, and / or similar methods) and coupled to a photodetector associated with each pixel cell 104. In some embodiments, the transfer gate structures 508A, 508B, 508C, and 508D may comprise polysilicon, metal, or other conductive materials.

[0063] Figure 9C A dielectric layer 504 is illustrated, formed (e.g., deposited) on at least a portion of a substrate 502 and transmission gate structures 508A, 508B, 508C, and 508D. In some embodiments, as described above, the dielectric layer 504 may comprise silicon oxide (SiO2). x ), such as silicon dioxide (SiO2), and / or one or more other dielectric materials.

[0064] Figure 9D The diagram illustrates trench 902 transmission gate structures formed by removing portions of dielectric layer 504, for example, through etching or other methods, to each transmission gate structure 508A, 508B, 508C, and 508D and the floating diffusion region 501.

[0065] Figure 9E The diagram illustrates conductive contact structures 515A, 515B, 515C, 515D and 517 formed (e.g., deposited and / or photolithographically lithographically), which are connected to transmission gate structures 508A, 508B, 508C and 508D and floating diffusion region 501, respectively.

[0066] Figure 9F The diagram illustrates the formation (e.g., by photolithography) of conductive bonding structures 513A, 513B, 513C, 513D, and 522 to connect to conductive contact structures 515A, 515B, 515C, 515D, and 517. In some embodiments, an additional dielectric material layer may be formed (e.g., deposited) to fill the gaps between conductive bonding structures 513A, 513B, 513C, 513D, and 522. Furthermore, in some embodiments, a planarization operation (e.g., using a chemical-mechanical planarization (CMP) process) may be performed on the top side of dielectric layer 504 to form an upper IC layer 102A.

[0067] Figure 10 The illustration is based on the present invention and is located in the adjacent area. Figure 9F A cross-sectional view of the initial state of the lower IC layer 102B before the upper IC layer 102A. More specifically, Figure 10The lower IC layer 102B, showing its state prior to the formation of any conductive bonding structures, includes a substrate 502 and processing circuitry therein (including a source follower transistor 304, a row select transistor 306, a reset transistor 307, a polysilicon capacitor 530, a conversion gain circuit 532, and a voltage domain global shutter circuit 534), and an associated dielectric layer 504 (containing multiple conductive layers 524 and conductive vias 525). Therefore, this initial state of the lower IC layer 102B is shared with… Figure 5A , Figure 6A , Figure 7A and Figure 8A Each embodiment is shown.

[0068] Starting from this initial state Figures 11 to 14 Depicted respectively Figure 5A , Figure 6A , Figure 7A and Figure 8A Each embodiment is bonded to the upper IC layer 102A (e.g., as shown in the figure). Figure 9F The lower IC layer 102B follows (as shown). In these figures, the upper IC layer 102A is relative to its... Figure 9F The orientation in the middle is described as "flipped" or inverted to facilitate bonding with the lower IC layer 102B.

[0069] For example, Figure 11 It is illustrated in accordance with this utility model. Figure 5A and Figure 5B A cross-sectional view of the lower IC layer 102B and the upper IC layer 102A before they are joined together. In some embodiments, a conductive bonding structure 523 has been formed on... Figure 10 The initial state of the lower IC layer 102B is shown on the top conductive layer 524 (e.g., a metal layer) (e.g., using photolithography or other methods). Then, the upper (e.g., second) sides or surfaces of the dielectric layers 504 of the upper IC layer 102A and the lower IC layer 102B are bonded together (e.g., using thermal bonding or other bonding processes), such that the conductive bonding structure 522 of the upper IC layer 102A and the conductive bonding structure 523 of the lower IC layer 102B are electrically connected. This bonding is formed... Figure 5A and Figure 5B The pixel cell group 105A.

[0070] Figure 12 It is illustrated in accordance with this utility model. Figure 6A and Figure 6B The image shows a cross-sectional view of the lower IC layer 102B and the upper IC layer 102A before they are joined together. In some embodiments, conductive contact structure 617 and conductive bonding structure 523 have been formed on... Figure 10The initial state of the lower IC layer 102B is shown on the top conductive layer 524 (e.g., a metal layer) (e.g., using photolithography or other methods). Then, the upper (e.g., second) surfaces of the dielectric layers 504 of the upper IC layer 102A and the lower IC layer 102B are bonded together (e.g., using thermal bonding or other bonding processes), such that the conductive bonding structure 522 of the upper IC layer 102A and the conductive bonding structure 523 of the lower IC layer 102B are electrically connected. This bonding forms... Figure 6A and Figure 6B The pixel cell group 105B.

[0071] Figure 13 It is illustrated in accordance with this utility model. Figure 7A and Figure 7B The image shows a cross-sectional view of the lower IC layer 102B and the upper IC layer 102C before they are joined together. In some embodiments, a conductive bonding structure 523 has been formed on... Figure 10 The initial state of the lower IC layer 102B is shown on the top conductive layer 524 (e.g., a metal layer) (e.g., using photolithography or other methods). Furthermore, conductive bonding structures 713A, 713B, and other structures corresponding to the conductive bonding structures 513A, 513B, 513C, and 513D of the upper IC layer 102A have been formed in the dielectric layer 504. Then, the upper (e.g., second) surfaces of the dielectric layers 504 of the upper IC layer 102A and the lower IC layer 102B are bonded together (e.g., using thermal bonding or other bonding processes), such that the conductive bonding structure 522 of the upper IC layer 102A and the conductive bonding structure 523 of the lower IC layer 102B are electrically connected, and the conductive bonding structures 513A, 513B, 513C, and 513D of the upper IC layer 102A are electrically connected to the conductive bonding structures 713A, 713B, etc., of the lower IC layer 102B. This bonding formation... Figure 7A and Figure 7B The pixel cell group 105C.

[0072] Figure 14 It is illustrated in accordance with this utility model. Figure 8A and Figure 8B The image shows a cross-sectional view of the lower IC layer 102B and the upper IC layer 102A before they are joined together. In some embodiments, conductive contact structure 617 and conductive bonding structure 523 have been formed on... Figure 10The initial state of the lower IC layer 102B is shown on the top conductive layer 524 (e.g., a metal layer) (e.g., using photolithography or other methods). Furthermore, conductive bonding structures 713A, 713B, and other structures corresponding to the conductive bonding structures 513A, 513B, 513C, and 513D of the upper IC layer 102A have been formed in the dielectric layer 504. Then, the upper (e.g., second) surfaces of the dielectric layers 504 of the upper IC layer 102A and the lower IC layer 102B are bonded together (e.g., using thermal bonding or other bonding processes), such that the conductive bonding structure 522 of the upper IC layer 102A and the conductive bonding structure 523 of the lower IC layer 102B are electrically connected, and the conductive bonding structures 513A, 513B, 513C, and 513D of the upper IC layer 102A are electrically connected to the conductive bonding structures 713A, 713B, etc., of the lower IC layer 102B. This bonding formation... Figure 8A and Figure 8B The pixel cell group is 105D.

[0073] Figure 15 The present invention illustrates a method 1500 for forming a CIS multi-die IC component (e.g., a CIS IC component 100A including pixel cell groups 105A, 105B, 105C, and 105D) employing a floating diffusion node structure with reduced capacitance. While this method and other methods illustrated and / or described herein are illustrated as a series of operations or events, it should be understood that the present invention is not limited to the illustrated order or operations. Therefore, in some embodiments, operations may be performed in a different order than illustrated, and / or may be performed simultaneously. Furthermore, in some embodiments, the illustrated operations or events may be subdivided into multiple operations or events that may be performed at different times or simultaneously with other operations or sub-operations. In some embodiments, some illustrated operations or events may be omitted, while other undescribed operations or events may be included.

[0074] For example, in operation 1502, in the first integrated circuit layer (e.g., Figure 5A , Figure 6A , Figure 7A and Figure 8A The substrate of the upper IC layer 102A (e.g., Figure 9A A photosensitive region (e.g., in the substrate 502) is formed. Figure 9A Photosensitive region 506). In operation 1504, a floating diffusion region is formed in the substrate adjacent to the photosensitive region (e.g., Figure 9A (Floating diffusion area 501). Figure 9A Cross-sectional views corresponding to some embodiments of operations 1502 and 1504 are shown.

[0075] In operation 1506, a transmission gate structure is formed on the substrate adjacent to the photosensitive region and the floating diffusion region (e.g., ...). Figure 9B (Transmission gate structure 508A or 508B). Figure 9B The illustration shows cross-sectional views corresponding to some embodiments of operation 1506.

[0076] In operation 1508, a dielectric layer is formed on the substrate and the transmission gate structure (e.g., Figure 9C Dielectric layer 504). Figure 9C Cross-sectional views corresponding to some embodiments of operation 1508 are shown.

[0077] In operation 1510, a first trench extending into the floating diffusion region is formed in the dielectric layer (e.g., Figure 9D Trench 902). Simultaneously, in operation 1512, a second trench extending into the transmission gate structure is formed in the dielectric layer (e.g., trench 902). Figure 9D (groove 902). Figure 9D Cross-sectional views corresponding to some embodiments of operations 1510 and 1512 are shown.

[0078] In operation 1514, a first conductive contact structure is formed in the first trench (e.g., Figure 9E The conductive contact structure 517), and a second conductive contact structure is formed in the second trench (e.g., Figure 9E (Conductive contact structure 515A or 515B). Figure 9E The illustration shows cross-sectional views corresponding to some embodiments of operation 1514.

[0079] In operation 1516, a first conductive bonding structure is formed on the dielectric layer above the first conductive contact structure (e.g., Figure 9F The conductive bonding structure 522). In operation 1518, a second conductive bonding structure is formed on the dielectric layer above the second conductive contact structure (e.g., the conductive bonding structure 522). Figure 9F (Conductive bonding structure 513A or 513B). Figure 9F Cross-sectional views are shown corresponding to some embodiments of operations 1516 and 1518.

[0080] Some embodiments relate to an integrated circuit assembly. The integrated circuit assembly includes a first integrated circuit layer, the integrated circuit layer including a first substrate. The substrate includes a plurality of photodetectors adjacent to a first side of the substrate and a plurality of floating diffusion regions located between the plurality of photodetectors and adjacent to the first side of the substrate. The integrated circuit layer also includes a plurality of first conductive structures located within a dielectric layer, the dielectric layer including a first side located on the first side of the substrate. The plurality of first conductive structures include a plurality of first conductive bonding structures located on a second side of the dielectric layer, the second side of the dielectric layer opposite to the first side of the dielectric layer. The plurality of first conductive structures also include a plurality of first conductive contact structures. Each of the plurality of first conductive contact structures connects a corresponding one of the plurality of floating diffusion regions to a corresponding one of the plurality of first conductive bonding structures.

[0081] In some embodiments, each of the plurality of photodetectors is associated with a corresponding one of the plurality of pixel cells; the plurality of pixel cells are organized into a plurality of pixel cell groups, each of the plurality of pixel cell groups comprising four of the plurality of pixel cells in a 2x2 configuration in the plan view of the integrated circuit assembly; and each of the plurality of floating diffusion regions, each of the plurality of first conductive structures, and each of the plurality of first conductive contact structures is located at a central position between the four pixel cells of the corresponding one of the plurality of pixel cell groups in the plan view of the integrated circuit assembly. In some embodiments, the plurality of first conductive structures further include: a plurality of transmission gate structures adjacent to the first side of the first dielectric layer, each of the plurality of transmission gate structures being adjacent to a corresponding one of the plurality of photodetectors; a plurality of second conductive bonding structures located on the second side of the first dielectric layer; and a plurality of second conductive contact structures, each of the plurality of second conductive contact structures connecting a corresponding one of the plurality of transmission gate structures to a corresponding one of the plurality of second conductive bonding structures. In some embodiments, each of the plurality of transport gate structures associated with one of the plurality of pixel cell groups is adjacent to one of the plurality of floating diffusion regions associated with the one of the plurality of pixel cell groups in a plan view of the integrated circuit assembly. In some embodiments, each of the plurality of transport gate structures associated with one of the plurality of pixel cell groups is triangular in a plan view of the integrated circuit assembly. In some embodiments, each of the plurality of transport gate structures associated with one of the plurality of pixel cell groups includes a right angle adjacent to the one of the plurality of floating diffusion regions associated with the one of the plurality of pixel cell groups. In some embodiments, each of the plurality of second conductive bonding structures associated with one of the plurality of pixel cell groups extends laterally in a plan view of the integrated circuit assembly. In some embodiments, each of the plurality of second conductive bonding structures associated with one of the plurality of pixel cell groups passes through one or more additional pixel cell groups in the lateral direction in a plan view of the integrated circuit assembly.In some embodiments, the integrated circuit assembly further includes a second integrated circuit layer, the second integrated circuit layer including: a second substrate; and a plurality of second conductive structures located within a second dielectric layer, the second dielectric layer including a first side disposed on a first side of the second substrate, the plurality of second conductive structures including: a plurality of third conductive bonding structures located on a second side of the second dielectric layer, the second side of the second dielectric layer being opposite to the first side of the second dielectric layer, each of the plurality of third conductive bonding structures being connected to a corresponding one of the plurality of first conductive bonding structures; and a plurality of conductive component groups, each of the plurality of conductive component groups electrically coupling a corresponding one of the plurality of third conductive bonding structures to the second substrate. In some embodiments, each of the plurality of third conductive bonding structures matches the size and shape of a corresponding one of the plurality of first conductive bonding structures in a plan view of the integrated circuit assembly. In some embodiments, each of the plurality of conductive component groups includes a plurality of conductive layers and a plurality of conductive vias. In some embodiments, the plurality of second conductive structures further includes a plurality of third conductive contact structures, each of the plurality of third conductive contact structures connecting a one of the plurality of third conductive bonding structures to a one of the plurality of conductive layers of a corresponding one of the plurality of conductive component groups. In some embodiments, the plurality of second conductive structures further include a plurality of fourth conductive bonding structures located on the second side of the second dielectric layer, each of the plurality of second conductive structures being connected to a corresponding one of the plurality of second conductive bonding structures. In some embodiments, each of the plurality of fourth conductive bonding structures matches the size and shape of a corresponding one of the plurality of second conductive bonding structures in a plan view of the integrated circuit assembly.

[0082] Some embodiments relate to another integrated circuit assembly. The integrated circuit assembly includes a first integrated circuit layer, the first integrated circuit layer including a first substrate. The first substrate includes a photodetector and a floating diffusion region adjacent to a first side of the first substrate, and a first conductive structure located within a first dielectric layer. The first dielectric layer includes a first side located on the first side of the substrate. The first conductive structure includes a first conductive bonding structure located on a second side of the dielectric layer, the second side of the dielectric layer opposite to the first side of the dielectric layer, and a first conductive contact structure connecting the first side of the substrate to the first conductive bonding structure at the floating diffusion region.

[0083] In some embodiments, the integrated circuit assembly further includes a second conductive structure comprising: a transmission gate structure adjacent to the first side of the first dielectric layer and the photodetector; a second conductive bonding structure located on the second side of the first dielectric layer; and a second conductive contact structure connecting the transmission gate structure to the second conductive bonding structure. In some embodiments, the integrated circuit assembly further includes a second integrated circuit layer comprising: a second substrate; and a plurality of third conductive structures located within the second dielectric layer, the second dielectric layer including a first side disposed on a first side of the second substrate, the plurality of third conductive structures including: a third conductive bonding structure located on a second side of the second dielectric layer, the second side of the second dielectric layer being opposite to the first side of the second dielectric layer, the third conductive bonding structure being connected to the first conductive bonding structure; and a conductive component group electrically coupling the third conductive bonding structure to the second substrate.

[0084] Some embodiments relate to a method of forming an integrated circuit assembly. The method includes: forming a photosensitive region in a substrate of a first integrated circuit layer; forming a floating diffusion region adjacent to the photosensitive region in the substrate; forming a transmission gate structure adjacent to the photosensitive region and the floating diffusion region on the substrate; forming a dielectric layer on the substrate and the transmission gate structure; forming a first trench in the dielectric layer extending to the floating diffusion region; forming a second trench in the dielectric layer extending to the transmission gate structure; forming a first conductive contact structure in the first trench and a second conductive contact structure in the second trench; forming a first conductive bonding structure on the dielectric layer above the first conductive contact structure; and forming a second conductive bonding structure on the dielectric layer above the second conductive contact structure.

[0085] In some embodiments, the method of forming an integrated circuit assembly further includes: bonding the upper side of the first integrated circuit layer to the upper side of a second integrated circuit layer, the second integrated circuit layer including a third conductive bonding structure and a fourth conductive bonding structure, wherein the first conductive bonding structure is electrically connected to the third conductive bonding structure, and the second conductive bonding structure is electrically connected to the fourth conductive bonding structure. In some embodiments, the bonding includes thermal bonding.

[0086] It should be understood that the terms "first," "second," "third," etc., used in this written description and in the following claims are merely general identifiers for ease of explanation to distinguish different components of a figure or series of figures. In themselves, these terms do not imply any temporal order or structural proximity of these components, and are not intended to describe corresponding components in different illustrated embodiments and / or embodiments not shown. For example, "first dielectric layer" illustrated in one figure may not necessarily correspond to "first dielectric layer" illustrated in another figure, and may not necessarily correspond to "first dielectric layer" in embodiments not shown.

[0087] The foregoing has outlined the features of several embodiments to enable those skilled in the art to better understand the nature of this invention. Those skilled in the art should understand that they can readily use this invention as the basis for designing or modifying other processes and structures to achieve the same purposes and / or attain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this invention, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of this invention.

Claims

1. An integrated circuit assembly, comprising: include: The first integrated circuit layer includes: The first substrate includes: Multiple photodetectors are located adjacent to a first side of the first substrate; and Multiple floating diffusion regions are located between the multiple photodetectors and adjacent to the first side of the first substrate; and A plurality of first conductive structures are located within a first dielectric layer, the first dielectric layer including a first side positioned on a first side of the first substrate, the plurality of first conductive structures including: Multiple first conductive bonding structures are located on a second side of the first dielectric layer, the second side of the first dielectric layer being opposite to the first side of the first dielectric layer; and A plurality of first conductive contact structures, each of the plurality of first conductive contact structures connecting a corresponding one of the plurality of floating diffusion regions to a corresponding one of the plurality of first conductive bonding structures.

2. The integrated circuit component according to claim 1, characterized in that: Each of the plurality of photodetectors is associated with a corresponding one of the plurality of pixel cells; The plurality of pixel cells are organized into a plurality of pixel cell groups, each of the plurality of pixel cell groups comprising four of the plurality of pixel cells in a 2x2 configuration in the plan view of the integrated circuit assembly; and Each of the plurality of floating diffusion regions, each of the plurality of first conductive structures, and each of the plurality of first conductive contact structures is located at the center between the four pixel cells corresponding to one of the plurality of pixel cell groups in the plan view of the integrated circuit assembly.

3. The integrated circuit assembly of claim 2, wherein, The plurality of first conductive structures further include: Multiple transmission gate structures are adjacent to the first side of the first dielectric layer, and each of the multiple transmission gate structures is adjacent to a corresponding one of the multiple photodetectors. Multiple second conductive bonding structures are located on the second side of the first dielectric layer; and A plurality of second conductive contact structures, each of the plurality of second conductive contact structures connecting a corresponding one of the plurality of transmission gate structures to a corresponding one of the plurality of second conductive junction structures.

4. The integrated circuit package of claim 3, wherein Each of the plurality of transmission gate structures associated with one of the plurality of pixel cell groups is adjacent to one of the plurality of floating diffusion regions associated with one of the plurality of pixel cell groups in the plan view of the integrated circuit assembly.

5. The integrated circuit package of claim 3, wherein, Each of the plurality of second conductive bonding structures associated with one of the plurality of pixel cell groups extends laterally in the plan view of the integrated circuit assembly.

6. The integrated circuit package of claim 3, wherein, It also includes a second integrated circuit layer, which includes: Second substrate; and A plurality of second conductive structures are located within a second dielectric layer, the second dielectric layer including a first side disposed on a first side of the second substrate, the plurality of second conductive structures including: A plurality of third conductive bonding structures are located on a second side of the second dielectric layer, the second side of the second dielectric layer being opposite to a first side of the second dielectric layer, each of the plurality of third conductive bonding structures being connected to a corresponding one of the plurality of first conductive bonding structures; and A plurality of conductive component groups, each of the plurality of conductive component groups electrically coupling a corresponding one of the plurality of third conductive bonding structures to the second substrate.

7. The integrated circuit assembly of claim 6, wherein, Each of the plurality of conductive component groups includes a plurality of conductive layers and a plurality of conductive vias.

8. The integrated circuit assembly of claim 7, wherein, The plurality of second conductive structures further include a plurality of third conductive contact structures, each of the plurality of third conductive contact structures connecting one of the plurality of third conductive bonding structures to one of the plurality of conductive layers of a corresponding one of the plurality of conductive component groups.

9. The integrated circuit assembly of claim 6, wherein, The plurality of second conductive structures further include a plurality of fourth conductive bonding structures located on the second side of the second dielectric layer, each of the plurality of second conductive structures being connected to a corresponding one of the plurality of second conductive bonding structures.

10. An integrated circuit assembly, comprising: include: The first integrated circuit layer includes: A first substrate, including a photodetector and a floating diffusion region, is adjacent to a first side of the first substrate; and A first conductive structure is located within a first dielectric layer, the first dielectric layer including a first side disposed on a first side of the first substrate, the first conductive structure comprising: A first conductive bonding structure is located on a second side of the first dielectric layer, wherein the second side of the first dielectric layer is opposite to the first side of the first dielectric layer; and A first conductive contact structure connects the first side of the first substrate to the first conductive bonding structure at the floating diffusion region.

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