SOP4 optical relay package structure

Abstract

The utility model relates to the technical field of optical relay, especially SOP4 optical relay packaging structure, due to the width setting of connecting rib between 0.09mm to 0.11mm, make plastic seal material fill gap increase 66.7%, ensure that the high light transmission epoxy resin plastic seal material in the molten state can flow fully and fill the small gap of TIEBAR and support edge in plastic sealing process, greatly reduced the probability of'leak support', the design guarantees the stability of electrical performance, and need not change standard packaging size 4.4mm*4.3mm*2mm, keep connecting rib thickness 0.2mm to maintain structural strength, and ensure that the light path coupling efficiency between LED and PVG is not affected, thereby realizing the packaging structure of high reliability and high yield under compact layout, solve the technical problem that the compact layout of the device in the existing SOP4 optical relay packaging causes two TIEBAR plastic seal leak support.

Description

Technical Field

[0001] This utility model relates to the field of optical relay technology, and in particular to an SOP4 optical relay packaging structure. Background Technology

[0002] SOP4 packaging has become the mainstream packaging form for this type of opto-relay due to its suitability for automated placement and compact size. Its standard dimensions must be strictly controlled at 4.4mm (length) × 4.3mm (width) × 2mm (thickness). In the SOP4 opto-relay package, the core functional components need to integrate four key devices: one LED (providing the trigger light source, wavelength 850nm / 940nm), one PVG (converting light energy into electrical energy to provide the gate drive voltage for the MOSFET), and two N-channel MOSFETs (to realize the main circuit's on / off state, requiring symmetrical layout to ensure current balance). Limited by the 4.4×4.3×2mm package space, the four devices must be arranged compactly—the LED and PVG must be adjacent (to ensure optical path coupling efficiency), and the two MOSFETs must be distributed on both sides (to accommodate the 4-pin electrode leads), resulting in extremely tight space in the "two-tier TIEBAR" area (the lateral support ribs in the bracket connecting the pins on both sides and supporting the PVG and MOSFETs).

[0003] In the existing technology, the width of the second TIEBAR is designed to be 0.15mm, and the thickness is fixed at 0.2mm (to match the strength of the bracket structure and avoid obstructing the light path of the LED and PVG). When this width is superimposed on the space of the LED (typical size 0.6×0.4×0.5mm), PVG (typical size 0.8×0.6×0.5mm), and MOS tube (typical size 1.0×0.8×0.5mm), it will cause the molten high-transmittance epoxy resin molding compound in the molding process to be unable to fully fill the gap between the TIEBAR and the edge of the bracket (the original gap is only 0.06mm), thus forming a "missing bracket" defect - the metal bracket is exposed. Utility Model Content

[0004] To address the shortcomings of existing technologies, this utility model provides an SOP4 opto-relay package structure, which solves the technical problem of leakage of the support bracket due to the compact layout of components in the existing SOP4 opto-relay package.

[0005] To solve the above-mentioned technical problems, this utility model provides the following technical solution: an SOP4 opto-relay package structure, including an IR bracket for mounting LEDs and an IP bracket for mounting PVG and MOSFETs, and a package body for encapsulating the IR bracket and IP bracket. The IR bracket and IP bracket are respectively provided with a plurality of IR pins and IP pins extending out of the package body. The IP bracket includes a PVG base island for mounting PVG and a MOSFET base island for mounting MOSFETs, and the PVG and LED are arranged opposite each other. Connecting ribs for cutting off before finishing are respectively provided between the plurality of IP pins and between the plurality of IR pins, and the left and right widths of the connecting ribs are between 0.09mm and 0.11mm.

[0006] Preferably, the resistivity of the connecting rib is ≤1.7μΩ・cm and the tensile strength is ≥300MPa.

[0007] Preferably, the IP bracket, IR bracket, IR pin and IP pin surfaces are provided with a nickel layer, and a silver layer is provided at the location where the PVG is installed on the PVG base island.

[0008] Preferably, the package has a light transmittance of 92%@850nm, a glass transition temperature of not less than 150℃, and a curing shrinkage rate of ≤0.5%.

[0009] Preferably, there are two MOS base islands, located on the upper and lower sides of the PVG base island respectively, and on the same plane as the PVG base island.

[0010] By employing the above technical solution, this utility model provides an SOP4 opto-relay packaging structure, which has at least the following beneficial effects: 1. This utility model, by setting the width of the connecting rib between 0.09mm and 0.11mm, increases the gap of the molding compound filling by 66.7%, ensuring that the molten high-transmittance epoxy molding compound can fully flow and fill the tiny gap between the TIEBAR and the edge of the bracket during the molding process, greatly reducing the probability of "bracket leakage". At the same time, this design ensures the stability of electrical performance, such as MOSFET gate leakage current ≤1nA, isolation voltage ≥6000Vrms and service life ≥100,000 hours, which fully complies with the IEC60747-5-5 photorelay standard. Moreover, it does not require changing the standard package size of 4.4mm×4.3mm×2mm, maintaining the connecting rib thickness of 0.2mm to maintain structural strength, and ensuring that the optical path coupling efficiency between the LED and PVG is not affected. Thus, a high-reliability and high-yield packaging structure is achieved in a compact layout.

[0011] 2. Due to the design of the connecting ribs with a resistivity ≤1.7μΩ・cm and tensile strength ≥300MPa, this utility model uses C194 copper alloy as the support material and employs photolithography positioning and precision etching processes (such as directional etching using 5% ferric chloride solution at 50℃±2℃) to achieve precise forming of the connecting ribs. This ensures that the connecting ribs maintain low resistance and high strength even when the width is reduced to 0.09~0.11mm. The low resistivity (≤1.7μΩ・cm) guarantees efficient transmission of electrical signals and minimizes conduction losses, while the high tensile strength (≥300MPa) allows the connecting ribs to reliably withstand the ≤20N pressure applied during the MOS transistor die bonding process, avoiding deformation or breakage caused by mechanical stress. This ensures the dimensional accuracy and structural stability of the support during packaging. At the same time, the excellent thermal conductivity helps dissipate heat from the device, improving the reliability and overall performance of the opto-relay in high-temperature environments and extending the device lifespan.

[0012] 3. This utility model, with its package having a light transmittance of 92%@850nm, a glass transition temperature of not less than 150℃, and a curing shrinkage rate of ≤0.5%, ensures that the 850nm infrared light emitted by the LED can be efficiently transmitted to the PVG by using a high-transmittance epoxy resin molding compound. This improves photoelectric conversion efficiency and ensures reliable driving of the MOSFET. At the same time, the high glass transition temperature makes the package less prone to softening and deformation in high-temperature environments (such as welding or high-temperature operation), maintaining structural stability and avoiding device failure caused by thermal stress. The low curing shrinkage rate reduces internal stress during the molding process, preventing bond wire breakage or device displacement. This ensures that the package dimensions are precisely controlled within the standard range of 4.4mm×4.3mm×2mm. As a result, the overall optical performance, thermal stability, and dimensional accuracy of the photorelay are improved, the risk of missing support is reduced, and the service life is extended, meeting the stringent requirements of industrial applications. Attached Figure Description

[0013] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of the packaged body before secondary encapsulation in existing technology. Figure 2 This is a schematic diagram of the present invention before secondary encapsulation and the encapsulation body; Figure 3 This is a top view of the finished product of this utility model; Figure 4 This is a side view of the finished product of this utility model.

[0014] In the diagram: 1. IR bracket; 2. IP bracket; 21. PVG base island; 22. MOS base island; 23. Connecting rib; 3. Package; 4. IR pin; 5. IP pin. Detailed Implementation

[0015] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0016] like Figure 1 As shown in the figure, the vertically distributed connecting ribs 23 indicated by the arrow are the second TIEBAR. In the existing technology, the cut surface is likely to be exposed to the air after packaging, which is called lead leakage. Lead leakage defects will cause three core problems: 1) poor appearance, the exposed metal is easy to oxidize, which does not meet the RoHS appearance standard for electronic components; 2) electrical failure, the exposed area is easily corroded by moisture, which leads to leakage current of the MOSFET gate and affects the reliability of the switch. At present, there is no effective solution in the industry for the lead leakage problem of the second TIEBAR in the "4.4×4.3×2mm SOP4 package + LED / PVG / dual MOSFET" structure. The technical bottleneck needs to be overcome.

[0017] Therefore, to address the technical problem of the compact device layout in existing SOP4 opto-relay packages leading to a two-stage TIEBAR encapsulation and lead frame, this invention provides an SOP4 opto-relay package structure, such as... Figures 2-4As shown, the solution addresses the issue of missing lead frames without altering the package size, adjusting the thickness of the second TIEBAR (maintaining 0.2mm to prevent deformation of the inner and outer leads, which could lead to high-voltage failures and SMT assembly issues), or affecting the LED-PVG optical path coupling and MOSFET conduction performance. This solution includes an IR bracket 1 for mounting the LED, which can be divided into two parts: an IP bracket 2 for mounting the PVG and MOSFET, and a package 3 for encapsulating the IR bracket 1 and IP bracket 2. The IR bracket 1 and IP bracket 2 each have several IR pins 4 and IP pins extending beyond the package 3. The IP bracket 2 includes a PVG base island 21 for mounting the PVG and a MOSFET base island 22 for mounting the MOSFET, with the PVG and LED arranged opposite each other. Connecting ribs 23, which are cut off before final product assembly, are provided between the IP pins 5 and between the IR pins 4. The width of the connecting ribs 23 is between 0.09mm and 0.11mm, and their thickness can be maintained. The width of the connecting rib 23 is typically 0.2mm. This size ensures the support strength of the IP bracket 2 for the MOSFET while preventing obstruction of the LED's light rays towards the PVG. Experiments show that this width setting increases the molding compound filling gap by 66.7%, eliminating bubbles and exposed areas. The defect rate of the leaky bracket has decreased from 15% to below 0.1%, while ensuring the MOSFET gate leakage current is ≤1nA, the isolation voltage is ≥6000Vrms, and the service life is ≥100,000 hours, conforming to IEC6000 standards. According to the 747-5-5 photorelay standard, for the above-mentioned devices, the LED model that can be selected is IR28-21C / TR8, with a size of 0.6×0.4×0.5mm and an emission wavelength of 850nm; the PVG model that can be selected is PDV-850, with a size of 0.8×0.6×0.5mm and an open-circuit voltage ≥4V; and the MOSFET model that can be selected is Si4432, with a size of 1.0×0.8×0.5mm and an on-resistance ≤45mΩ. Gold wire can be used for wiring connections.

[0018] exist Figures 2-4 In the diagram, the green line represents the overall structure of IR bracket 1 and IR pin 4 before cutting, and the gray line represents the overall structure of IP bracket 2 and IP pin 5 before cutting. They are stacked opposite each other. The finished packaged product is shown below. Figure 3 and Figure 4 As shown, the purple and blue lines represent the boundaries between the primary and secondary packages of package 3.

[0019] To ensure electrical and thermal conductivity requirements are met, the resistivity of the connecting rib 23 can be ≤1.7μΩ・cm. Furthermore, since the IR bracket 1 and IR pin 4 are typically mounted on a single integrated bracket before processing, and the IP bracket 2, package 3, and IP pin 5 are typically mounted on another integrated bracket, their materials can be identical. Experiments have shown that C194 copper alloy can be used, and the width of the connecting rib 23 can be reduced through a "photolithography positioning + precision etching" process—using a 5% ferric chloride solution (temperature 50℃±2℃) for directional etching. After etching, the tensile strength of the connecting rib 23 is ≥300MPa, ensuring it can withstand the pressure (≤20N) during MOSFET die bonding. To further improve the photoelectric conversion efficiency of this product, a nickel layer can be provided on the surface of IP bracket 2, IR bracket 1, IR pin 4 and IP pin, and an additional silver layer can be provided at the position where the PVG is installed on the PVG base island 21.

[0020] To ensure efficient optical path transmission and improve the thermal stability of the packaging structure, thereby increasing dimensional accuracy and reducing the probability of lead leakage, the light transmittance of package 3 reaches 92%@850nm. This molding compound has high transmittance to the 850nm infrared light emitted by the LED, ensuring efficient light energy transfer to the PVG (photodiode array), improving photoelectric conversion efficiency, and ensuring reliable driving of the MOSFET. The glass transition temperature is not lower than 150℃. A higher glass transition temperature (Tg) means that the package is less likely to soften and deform in high-temperature environments (such as welding, high-temperature operation), maintaining structural stability and avoiding device failure due to thermal stress. The curing shrinkage rate is ≤0.5%, which can reduce internal stress caused by uneven shrinkage during molding, avoiding bond wire breakage or device displacement caused by excessive shrinkage. This ensures that the package dimensions are precisely controlled within the standard range of 4.4×4.3×2mm, thereby ensuring processing accuracy and reducing lead leakage problems caused by low processing accuracy.

[0021] To meet the "light path priority, electrode symmetry" principle of layout within the package cavity: the LED and PVG are centered and symmetrical vertically (spacing > 0.2mm to ensure light path coverage ≥ 100%), and two MOS transistors are symmetrically distributed on both sides of the PVG (0.2mm spacing from the PVG, adapted to the drains of two 3 / 4 pin MOS transistors), so that there are two MOS base islands 22, located on the upper and lower sides of the PVG base island 21 respectively, and on the same plane as the PVG base island 21.

[0022] It should be noted that, in this document, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0023] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An SOP4 opto-relay package structure, comprising an IR bracket (1) for mounting an LED, and an IP bracket (2) for mounting a PVG and a MOSFET, and further comprising a package (3) for encapsulating the IR bracket (1) and the IP bracket (2), wherein the IR bracket (1) and the IP bracket (2) are respectively provided with a plurality of IR pins (4) and IP pins (5) extending outside the package (3), characterized in that, The IP bracket (2) includes a PVG base island (21) for mounting PVG and a MOS base island (22) for mounting MOS. The PVG and LED are arranged opposite each other. Connecting ribs (23) for cutting off before the finished product are provided between several IP pins (5) and between several IR pins (4). The left and right widths of the connecting ribs (23) are between 0.09 mm and 0.11 mm.

2. The SOP4 opto-relay package structure according to claim 1, characterized in that, The resistivity of the connecting rib (23) is ≤1.7μΩ・cm and the tensile strength is ≥300MPa.

3. The SOP4 opto-relay package structure according to claim 1, characterized in that, The IP bracket (2), IR bracket (1), IR pin (4) and IP pin are provided with a nickel layer, and a silver layer is provided at the position where the PVG is installed on the PVG base island (21).

4. The SOP4 opto-relay package structure according to claim 1, characterized in that, The light transmittance of the encapsulation (3) reaches 92%@850nm, the glass transition temperature is not lower than 150℃, and the curing shrinkage rate is ≤0.5%.

5. The SOP4 opto-relay package structure according to claim 1, characterized in that, The MOS base island (22) consists of two islands, which are located on the upper and lower sides of the PVG base island (21) and are on the same plane as the PVG base island (21).

Images