Light emitting light source

Abstract

The utility model discloses a light emitting source, including light source substrate, chip array, a plurality of conductive pads and a plurality of conductive pads, the first surface of light source substrate is equipped with chip area and the connecting area of being located chip area outside, chip array sets up in chip area, a plurality of conductive pads interval arrangement is in the connecting area, conductive pad sets up the second surface of light source substrate, be equipped with at least one first conductive via and at least one second conductive via on light source substrate, in chip array, at least one chip passes through first conductive via, conductive pad and second conductive via of connecting in proper order and corresponding conductive pad conductive connection, make all chips of chip array can be controlled individually. The utility model passes through the conductive via of light source substrate setting conductive pad and the wiring of light source substrate second surface, set up all conductive pads connected with the chip on the first surface of light source substrate, benefit chip high density arrangement and realize single core control.

Description

Technical Field

[0001] This utility model relates to the field of light-emitting device technology, and in particular to a light-emitting light source. Background Technology

[0002] In some existing light sources, such as high-power light sources, when chips are densely interconnected on a substrate, there is insufficient space around the chip located in the middle for wiring. Control between chips is mainly achieved through series connection, making single-chip control impossible. Using a multi-layer substrate instead of a single-layer substrate for high-density chip interconnection not only increases costs but also results in poor heat dissipation and low manufacturing yield. Utility Model Content

[0003] The technical problem to be solved by this utility model is to provide an improved light source.

[0004] The technical solution adopted by this utility model to solve its technical problem is: to provide a light source, including a light source substrate having a first surface and a second surface with opposite sides, a chip array formed by several chips, several conductive pads and several conductive solder pads; The first surface of the light source substrate is provided with a chip area and a connection area located outside the chip area. The chip array is disposed in the chip area, and a plurality of conductive pads are arranged at intervals in the connection area. The conductive pads are disposed on the second surface of the light source substrate. The light source substrate is provided with at least one first conductive via and at least one second conductive via; in the chip array, at least one chip is electrically connected to the corresponding conductive pad through a first conductive via, a conductive pad, and a second conductive via connected in sequence, so that all chips in the chip array can be controlled individually.

[0005] Preferably, in the chip array, at least the chip located in the middle of the chip array is electrically connected to the corresponding conductive pad through the first conductive via, the conductive pad, and the second conductive via.

[0006] Preferably, in the chip array, the chip located at the outermost edge of the chip array is electrically connected to the corresponding conductive pad through conductive lines arranged on the first surface of the light source substrate.

[0007] Preferably, for all chips in the chip array, chips located in the same column or row have one pole connected to the same conductive pad, and the other pole connected to different conductive pads.

[0008] Preferably, the two poles of all chips in the chip array are connected to different conductive pads.

[0009] Preferably, the light source substrate comprises a ceramic substrate.

[0010] Preferably, the light source further includes an insulating heat dissipation substrate disposed on the second surface of the light source substrate, and the insulating heat dissipation substrate is thermally connected to the second surface of the light source substrate.

[0011] Preferably, the light source further includes a high thermal conductivity material layer disposed between the second surface of the light source substrate and the insulating heat dissipation substrate, wherein the insulating heat dissipation substrate is connected to the second surface through the high thermal conductivity material layer and is thermally connected.

[0012] Preferably, the light source further includes a heat dissipation unit; the heat dissipation unit is in contact with and thermally connected to the insulating heat dissipation substrate.

[0013] Preferably, the light source further includes a circuit board having opposing first and second surfaces, the circuit board having a window penetrating through its first and second surfaces, and the second surface of the circuit board having a plurality of external pads. The circuit board is stacked on the first surface of the light source substrate with its second surface facing the light source substrate, the chip array is exposed from the window, and each of the external pads is electrically connected to the corresponding conductive pad.

[0014] The beneficial effects of this utility model are as follows: By setting conductive vias on the light source substrate and connecting them with conductive pads on the second surface of the light source substrate, all conductive pads connected to the chip are placed on the first surface of the light source substrate, which is conducive to high-density chip arrangement and single-chip control; the heat generated by the chip during operation is promptly dissipated from one side of the second surface of the light source substrate, resulting in good heat dissipation. Attached Figure Description

[0015] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings: Figure 1 This is a front structural schematic diagram of a light-emitting light source according to an embodiment of the present invention; Figure 2 yes Figure 1 A longitudinal cross-sectional view of the light source shown; Figure 3 yes Figure 1 A schematic diagram showing the connection between the chip and the conductive pad in the light-emitting source. Figure 4 This is a schematic diagram of the circuit board structure of a light source according to an embodiment of the present invention; Figure 5 This is a front structural schematic diagram of a light source according to an embodiment of the present invention. Detailed Implementation

[0016] To provide a clearer understanding of the technical features, objectives, and effects of this utility model, the specific embodiments of this utility model will now be described in detail with reference to the accompanying drawings.

[0017] like Figure 1 , Figure 2 As shown, the light source of this utility model includes a light source substrate 10, a chip array 20, a plurality of conductive pads 30 and a plurality of conductive pads 40.

[0018] The light source substrate 10 has a first surface and a second surface facing each other. A chip region and a connection region located outside the chip region are provided on the first surface of the light source substrate 10. A chip array 20 is disposed within the chip region, and a plurality of conductive pads 30 are spaced apart within the connection region. Conductive pads 40 are disposed on the second surface of the light source substrate 10. The chip array 20 is formed by arranging a plurality of chips 21, which are electrically connected to the conductive pads 30 and / or electrically connected to the conductive pads 30 through the conductive pads 40.

[0019] The light source substrate 10 may include, but is not limited to, a ceramic substrate.

[0020] The light source substrate 10 is provided with at least one first conductive via 11 and at least one second conductive via 12. The first conductive via 11 penetrates through the first surface and the second surface of the light source substrate 10 and conductively connects the chip 21 and the corresponding conductive pad 40. The second conductive via 12 penetrates through the first surface and the second surface of the light source substrate 10 and conductively connects the conductive pad 40 and the corresponding conductive pad 30.

[0021] The above-mentioned arrangement of the first conductive through-hole 11 and the second conductive through-hole 12 enables the first conductive through-hole 11 to form a sequential connection (conductive connection) with the corresponding conductive pad 40, the second conductive through-hole 12 and the conductive pad 30.

[0022] In the chip array 20, at least one chip 21 is electrically connected to a corresponding conductive pad 30 via a first conductive via 11, a conductive pad 40, and a second conductive via 12 connected in sequence, so that all chips 21 in the chip array 20 can be controlled individually. According to the positive and negative polarity connection, the conductive pad 30 includes a plurality of positive conductive pads and a plurality of negative conductive pads.

[0023] Chip 21 includes LED chips.

[0024] In some embodiments, in the chip array 20, at least the chip 21 located in the middle of the chip array 20 is electrically connected to the conductive pad 40 on the second surface of the light source substrate 10 through a first conductive via 11. The conductive pad 40 is electrically connected to the corresponding conductive pad 30 on the first surface of the light source substrate 10 through a second conductive via 12. Thus, the chip 21 is electrically connected to the corresponding conductive pad 30 through the first conductive via 11, the conductive pad 40, and the second conductive via 12. The chip 21 located at the outermost edge of the chip array 20 is electrically connected to the corresponding conductive pad 30 through conductive lines arranged on the first surface of the light source substrate 10. Alternatively, the chip 21 located at the outermost edge of the chip array 20 is also electrically connected to the corresponding conductive pad 30 through the corresponding first conductive via 11, the conductive pad 40, and the second conductive via 12.

[0025] In some embodiments, all chips 21 in the chip array 20 have one pole (positive or negative) of chips 21 located in the same column or row connected to the same conductive pad 30 to achieve common pole; the other pole (negative or positive) of chips 21 located in the same column or row is connected to different conductive pads 30, thereby achieving individual control of each chip 21.

[0026] Alternatively, the two poles of all the chips 21 in the chip array 20 are connected to different conductive pads 30. For example, the number of conductive pads 30 is set according to the number of chips 21, so that the positive pole of each chip 21 is conductively connected to one conductive pad 30, and the negative pole is conductively connected to another conductive pad 30.

[0027] by Figure 1 The chip array 20 shown includes six chips 21, which will be used as an example for illustration. (Combined with...) Figure 1 and Figure 3 The six chips 21 are numbered 1 to 9 respectively. Twelve conductive pads 30 are arranged in the connection area. Three conductive pads 30 are arranged on the outer side of each chip area. The horizontally arranged conductive pads 30 are numbered X1 to X6 from top to bottom, and the vertically arranged conductive pads 30 are numbered Y1 to Y6 from left to right. The connections between chips 1 to 9 and conductive pads X1 to X6 and Y1 to Y6 are as follows: Chip 5 is a chip located at the center of chip array 20, with its two poles (positive and negative) electrically connected to conductive pads Y2 and Y5, respectively. Three chips 1, 4, and 7 in the left column of chip array 20 have one pole electrically connected to the same conductive pad Y3, and the other poles of these three chips 1, 4, and 7 are electrically connected to three other different conductive pads, such as conductive pads X1, Y1, and X4, respectively. Three chips 3, 6, and 9 in the right column of chip array 20 have one pole electrically connected to the same conductive pad X6, and the other poles of these three chips 3, 6, and 9 are electrically connected to three other different conductive pads, such as conductive pads X3, Y4, and Y6, respectively. One pole of chip 2 is electrically connected to conductive pad X2, and the other pole is electrically connected to conductive pad X5 (or X3). One pole of chip 8 is electrically connected to conductive pad X4, and the other pole is electrically connected to conductive pad X5.

[0028] Understandably, the above is only one example of a conductive connection between chip 21 and conductive pad 30, and the conductive connection between chip 21 and conductive pad 30 is not limited to this. For example, one pole of three chips 1, 2, and 3 in the same row can be connected to the same conductive pad, and the other pole can be connected to three different conductive pads, with the remaining chips adjusted accordingly.

[0029] By setting the conductive connection between chip 21 and conductive pad 30, it is avoided that two or more chips 21 are conductively connected to the same two conductive pads 30, so that each chip 21 has an independent conduction circuit for individual control.

[0030] In some embodiments, such as Figure 2 As shown, the light source also includes an insulating heat dissipation substrate 50. The insulating heat dissipation substrate 50 is disposed on the second surface of the light source substrate 10 and is thermally connected to the second surface of the light source substrate 10. The heat generated by the chip array 20 can be transferred to the insulating heat dissipation substrate 50 in a timely manner and dissipated from the insulating heat dissipation substrate 50.

[0031] Preferably, the outer periphery of the insulating heat dissipation substrate 50 is equal to or greater than the outer periphery of the light source substrate 10, so that the entire second surface of the light source substrate 10 is attached to the insulating heat dissipation substrate 50, thereby achieving heat dissipation of the entire surface of the light source substrate 10.

[0032] To facilitate connection and improve thermal conductivity, the light source may also include a high thermal conductivity material layer (not shown) disposed between the second surface of the light source substrate 10 and the insulating heat dissipation substrate 50. The insulating heat dissipation substrate 50 is connected to the second surface of the light source substrate 10 through the high thermal conductivity material layer and is thermally connected.

[0033] The high thermal conductivity material layer also covers the conductive pads 40 on the second surface of the light source substrate 10, thus protecting the conductive pads 40. The thickness of the high thermal conductivity material layer between the second surface of the light source substrate 10 and the insulating heat dissipation substrate 50 is preferably greater than the thickness of the conductive pads 40 on the second surface of the light source substrate 10, so as to have excess thickness to bond the insulating heat dissipation substrate 50 to the conductive pads 40.

[0034] High thermal conductivity material layers include, but are not limited to, thermal grease.

[0035] In some embodiments, such as Figures 4-5 As shown, the light source also includes a circuit board 60. The circuit board 60 has a first surface and a second surface opposite to each other. The circuit board 60 is provided with a window 61 that penetrates through its first surface and second surface. The second surface of the circuit board 60 is provided with a plurality of external pads 62.

[0036] Window 61 and external pad 62 are respectively positioned to correspond to the chip area and connection area on the light source substrate 10. When the circuit board 60 is stacked on the first surface of the light source substrate 10 with its second surface facing the light source substrate 10, the chip array 20 in the chip area is aligned with window 61 and exposed from the window, i.e., from the side where the first surface of the circuit board 60 is located. Each external pad 62 is electrically connected to the corresponding conductive pad 30 on the connection area.

[0037] In some embodiments, the light source further includes a heat dissipation unit (not shown); the heat dissipation unit is connected to and thermally connected to the insulating heat dissipation substrate 50.

[0038] Specifically, the heat dissipation unit is disposed on the side of the insulating heat dissipation substrate 50 that is away from the light source substrate 10. That is, the insulating heat dissipation substrate 50 is attached to the heat dissipation unit with the surface of the insulating heat dissipation substrate 50 away from the light source substrate 10, so that the entire surface of the insulating heat dissipation substrate 50 is in contact with the mounting surface of the heat dissipation unit, thereby ensuring the heat dissipation area and thus ensuring the heat dissipation effect.

[0039] The heat dissipation unit can be, but is not limited to, a heat sink or a device with a heat dissipation structure.

[0040] The above description is merely an embodiment of this utility model and does not limit the patent scope of this utility model. Any equivalent structural or procedural transformations made based on the description and drawings of this utility model, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this utility model.

Claims

1. A light emitting light source, characterized in that It includes a light source substrate having opposing first and second surfaces, a chip array formed by several chips, several conductive pads, and several conductive solder pads; The first surface of the light source substrate is provided with a chip area and a connection area located outside the chip area. The chip array is disposed in the chip area, and a plurality of conductive pads are arranged at intervals in the connection area. The conductive pads are disposed on the second surface of the light source substrate. The light source substrate is provided with at least one first conductive via and at least one second conductive via; in the chip array, at least one chip is electrically connected to the corresponding conductive pad through a first conductive via, a conductive pad, and a second conductive via connected in sequence, so that all chips in the chip array can be controlled individually.

2. A light emitting source according to claim 1, characterized in that In the chip array, at least the chip located in the middle of the chip array is electrically connected to the corresponding conductive pad through the first conductive via, the conductive pad, and the second conductive via.

3. A light emitting source according to claim 1, characterized in that In the chip array, the chip located at the outermost edge of the chip array is electrically connected to the corresponding conductive pad through conductive lines arranged on the first surface of the light source substrate.

4. The light source according to claim 1, characterized in that, All chips in the chip array, located in the same column or row, have one pole connected to the same conductive pad and the other pole connected to different conductive pads.

5. The light source according to claim 1, characterized in that, Each of the chips in the chip array is connected to a different conductive pad at its two poles.

6. The light source according to claim 1, characterized in that, The light source substrate includes a ceramic substrate.

7. The light source according to any one of claims 1-6, characterized in that, The light source also includes an insulating heat dissipation substrate disposed on the second surface of the light source substrate, and the insulating heat dissipation substrate is thermally connected to the second surface of the light source substrate.

8. The light source according to claim 7, characterized in that, The light source further includes a high thermal conductivity material layer disposed between the second surface of the light source substrate and the insulating heat dissipation substrate, wherein the insulating heat dissipation substrate is connected to the second surface through the high thermal conductivity material layer and is thermally connected.

9. The light source according to claim 8, characterized in that, The light source also includes a heat dissipation unit; the heat dissipation unit is in contact with and thermally connected to the insulating heat dissipation substrate.

10. The light source according to claim 8, characterized in that, The light source also includes a circuit board having a first surface and a second surface opposite to each other. The circuit board has a window penetrating through its first surface and second surface, and the second surface of the circuit board has a plurality of external pads. The circuit board is stacked on the first surface of the light source substrate with its second surface facing the light source substrate, the chip array is exposed from the window, and each of the external pads is electrically connected to the corresponding conductive pad.

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