A power module

Abstract

The utility model discloses a kind of power module, it is related to power semiconductor field, comprising: electrical metal layer, heat dissipation metal layer and the insulating substrate being set between electrical metal layer and heat dissipation metal layer;Electrical metal layer is provided with shunt area corresponding with phase current one-to-one, the size of each shunt area is equal, the edge of electrical metal layer of any one shunt area is uniformly provided with multiple power pins;For any one shunt area, control end, power transmission end and sampling end are one-to-one corresponding connection with each power pin.Electrical metal layer is divided into multiple shunt areas according to phase, realizes different phase voltage independent control while excluding interference between each other.Power chip in shunt area is respectively output through power transmission end, avoid the power chip overcurrent uneven and failure caused by flow resistance interference and magnetic distribution interference etc. between each other, improve the current sharing capability of power module, improve the reliability of power module.

Description

Technical Field

[0001] This utility model relates to the field of power semiconductors, and in particular to a power module. Background Technology

[0002] As a key component in the electronics and electrical field, power semiconductor modules have stringent requirements regarding reliability, safety, and heat dissipation. Especially in the fields of new energy key components and photovoltaic energy storage, the reliability and performance of power semiconductor modules have a crucial impact on the safety of end-applications. Existing power semiconductor modules come in various packaging forms, generally consisting of an upper-bridge power chip and a lower-bridge power chip mounted on an electrical metal layer. The upper-bridge power chip serves as the current input terminal, while the lower-bridge power chip serves as the current output terminal. The upper-bridge power chip transmits three-phase AC current across the transition electrical metal layer via bonding wires to the lower-bridge power chip. Due to the magnetic field generated by the bonding wires, there is significant EMC interference between the two, resulting in reduced overall power module performance, high stray inductance, low reliability, and high heat generation. Furthermore, in high-power multi-chip (at least two power chips) parallel applications, the lower-bridge power chips are typically connected in a series-parallel configuration (referred to as "series-parallel"). When the phase current flows between the chips, it does not achieve uniform current flow, leading to uneven current distribution across the chips (due to the impedance differences in the three-phase current paths caused by the asymmetrical layout, resulting in dynamic current sharing deviation). In practical applications, the lower-bridge power chip is prone to failure, resulting in low power module reliability and high application costs. Utility Model Content

[0003] The purpose of this invention is to provide a power module in which the power chips in the current sharing zone output power through the power transmission terminal, thereby avoiding the failure of the power chips due to uneven current distribution caused by current resistance interference and magnetic distribution interference between the power chips, improving the current sharing capability of the power module and improving the reliability of the power module.

[0004] To solve the above-mentioned technical problems, this utility model provides a power module, including: an electrical metal layer, a heat dissipation metal layer, and an insulating substrate disposed between the electrical metal layer and the heat dissipation metal layer;

[0005] The electrical metal layer is provided with shunt regions corresponding to the phase currents one by one. Each shunt region is of equal size. Multiple power pins are provided near the edge of the electrical metal layer in any shunt region. The power pins are used for electrical connection with external devices.

[0006] For any given shunt zone, the control terminal, power transmission terminal, and sampling terminal of the shunt zone are all connected to corresponding power pins, so that the power chip in the shunt zone can rectify or invert the current input to the power transmission terminal based on the control of the control terminal, output the current through the power transmission terminal respectively, and feed the current back through the sampling terminal respectively.

[0007] On the other hand, each of the shunt zones includes an electrical connector, a first power chip set, and a second power chip set. The electrical connector includes a bonding wire. The control terminal of the shunt zone includes a first control terminal and a second control terminal. The power transmission terminal includes a power input terminal, a power output terminal, and a three-phase AC terminal.

[0008] The control terminal of the first power chip group is used as the first control terminal, the first terminal of the first power chip group is used as the power input terminal, the second terminal of the first power chip group and the first terminal of the second power chip group are used as the three-phase AC terminal, the control terminal of the second power chip group is used as the second control terminal, and the second terminal of the second power chip group is used as the power output terminal.

[0009] The first power chip group is used to invert the DC power input to the power transmission terminal and output it, while the second power chip group is used to rectify the three-phase AC power input to the power transmission terminal and output it.

[0010] On the other hand, any shunt region on the electrical metal layer includes a power input sub-region, a first control sub-region, and a three-phase AC sub-region;

[0011] The power input sub-region's power pins are connected to the DC terminal of the external device, the power pins of the first control sub-region are connected to the control signal of the external device, and the three-phase AC sub-region is connected to the three-phase AC terminal of the external device.

[0012] The power input sub-region is used to convert the DC power input from the external device into three-phase AC power based on the control signal input from the first control sub-region.

[0013] On the other hand, the first power chip group is disposed on the power input sub-region, the first end of the first power chip group is electrically connected to the power pin of the power input sub-region through solder, the control end of the first power chip group is electrically connected to the power pin of the first control sub-region through bonding wire, and the second end of the first power chip group is electrically connected to the power pin of the three-phase AC sub-region through bonding wire.

[0014] On the other hand, any shunt region on the electrical metal layer also includes a second control sub-region and a power output sub-region;

[0015] The power pins of the second control sub-region are connected to the control signals of the external device, and the power output sub-region is connected to the DC terminal of the external device;

[0016] The power input sub-region is used to convert the three-phase AC power input from the external device into DC power based on the control signal input from the second control sub-region.

[0017] On the other hand, the second power chip group is disposed on the three-phase AC sub-region. The control terminal of the second power chip group is electrically connected to the power pin of the second control sub-region through a bonding wire. The first end of the second power chip group is electrically connected to the power pin of the three-phase AC sub-region through solder. The second end of the second power chip group is electrically connected to the power pin of the power output through a bonding wire.

[0018] On the other hand, both the first power chipset and the second power chipset include at least two power chips connected in parallel.

[0019] In each of the first power chipsets, the gate of the power chip serves as the control terminal of the first power chipset and is electrically connected to the power pins of the first control sub-region via bonding wires. In each of the first power chipsets, the drain of the power chip serves as the first terminal of the first power chipset and is electrically connected to the power pins of the power input sub-region via solder. In each of the first power chipsets, the source of the power chip serves as the second terminal of the first power chipset and is electrically connected to the power pins of the three-phase AC sub-region via bonding wires.

[0020] The gate of the power chip in each of the second power chipsets serves as the control terminal of the second power chipset and is electrically connected to the power pins of the second control sub-region via bonding wires. The drain of the power chip in each of the second power chipsets serves as the first terminal of the second power chipset and is electrically connected to the power pins of the three-phase AC sub-region via solder. The source of the power chip in each of the second power chipsets serves as the second terminal of the second power chipset and is electrically connected to the power pins of the power output sub-region via bonding wires.

[0021] On the other hand, for any shunt region on the electrical metal layer, there are also a first sampling sub-region and a second sampling sub-region, and the sampling end includes a first sampling end and a second sampling end;

[0022] In each of the first power chipsets, the source of the power chip serves as the first sampling terminal of the first power chipset and is electrically connected to the power pins of the first sampling sub-region via bonding wires. In each of the second power chipsets, the source of the power chip serves as the second sampling terminal of the second power chipset and is electrically connected to the power pins of the second sampling sub-region via bonding wires.

[0023] On the other hand, any shunt region on the electrical metal layer also includes a temperature acquisition sub-region;

[0024] The temperature acquisition sub-area is equipped with a thermistor for acquiring the temperature of the shunt zone.

[0025] On the other hand, it also includes power packages;

[0026] The length and width of the power package are equal to those of the power substrate, and the height of the power package is lower than the height of the power pin.

[0027] This application provides a power module, relating to the field of power semiconductors, comprising: an electrical metal layer, a heat dissipation metal layer, and an insulating substrate disposed between the electrical metal layer and the heat dissipation metal layer; the electrical metal layer is provided with shunt regions corresponding one-to-one with the phase current, each shunt region having an equal size, and multiple power pins disposed near the edge of each shunt region near the electrical metal layer; for each shunt region, a control terminal, a power transmission terminal, and a sampling terminal are connected one-to-one with each power pin. The electrical metal layer is divided into multiple shunt regions according to phase, with adjacent shunt regions not interfering with each other, achieving independent control of different phase voltages while eliminating mutual interference, further reducing stray current. The shunt regions are set to the same or similar size, ensuring the uniformity of heat dissipation of the subsequent power module. Simultaneously, through a split-parallel connection, the shunt capability of each individual power chip unit is ensured, avoiding the power chip failure caused by uneven current distribution due to current resistance interference and magnetic distribution interference between power chips caused by series-parallel methods, significantly improving the current sharing capability of the power module and significantly improving the reliability of the power module. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 A schematic diagram of the structure of a power module provided by this utility model;

[0030] Figure 2 A schematic diagram of the structure of a diversion zone provided by this utility model;

[0031] Figure 3 This is a schematic diagram of another diversion zone provided by the present invention;

[0032] Figure 4A schematic diagram of the current flow direction in a current shunt zone provided by this utility model;

[0033] Figure 5 A schematic diagram of the structure of a diversion zone provided by this utility model;

[0034] Figure 6 This is a schematic diagram of the packaging structure of a power module provided by this utility model. Detailed Implementation

[0035] The core of this utility model is to provide a power module in which the power chips in the current sharing area output through the power transmission terminal, thereby avoiding the failure of the power chips due to uneven current distribution caused by current resistance interference and magnetic distribution interference between the power chips, improving the current sharing capability of the power module and improving the reliability of the power module.

[0036] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0037] Figure 1 This utility model provides a structural schematic diagram of a power module, which includes: an electrical metal layer, a heat dissipation metal layer, and an insulating substrate disposed between the electrical metal layer and the heat dissipation metal layer;

[0038] The electrical metal layer is provided with shunt regions that correspond one-to-one with the phase current. Each shunt region is of equal size. Multiple power pins are provided near the edge of the electrical metal layer in any shunt region. The power pins are used for electrical connection with external devices.

[0039] For any given shunt zone, the control terminal, power transmission terminal, and sampling terminal of the shunt zone are all connected to corresponding power pins, so that the power chip in the shunt zone can rectify or invert the current input to the power transmission terminal based on the control of the control terminal, output the current through the power transmission terminal respectively, and feed the current back through the sampling terminal respectively.

[0040] As a key component in the electronics and electrical field, power semiconductor modules have stringent requirements regarding reliability, safety, and heat dissipation. Especially in the field of key components for new energy, the reliability and performance of power semiconductor modules have a crucial impact on the safety of end-applications.

[0041] The power module includes a power substrate, power chips in the shunt area, power connectors, and several power pins. The power substrate is DBC (Direct Bonded Copper) or other types of ceramic substrates such as AMB (Active Metal Brazing), used to realize electrical functions and electrical heat dissipation isolation. One side of the power substrate is an electrical metal layer, and the other side is a heat dissipation metal layer. Several power chips are set on the electrical metal layer, and power pins are set at any two opposite edges of the metal layer. The power pins are the internal and external electrical connections of the module, and the power connectors are the electrical functional connections formed between the chips. The power chips realize and control internal and external electrical functions through the power connectors.

[0042] Taking three-phase alternating current as an example, three-phase alternating current includes three phases: U, V, and W. Therefore, the electrical metal layer includes U-phase shunt regions, V-phase shunt regions, and W-phase shunt regions, which are arranged horizontally along the shunt ceramic substrate and correspond to the voltage of each phase. Each of the U-phase, V-phase, and W-phase shunt regions has multiple power components arranged in the same or similar structure. When there is a demand for multi-phase current input or output, this application will provide a corresponding number of shunt regions to meet the demand for multi-phase current.

[0043] Along the vertical direction of the shunt ceramic substrate, each shunt zone has a corresponding control terminal, power transmission terminal, and sampling terminal at one end and the other end, respectively. The power component is located in its corresponding shunt zone. The power output terminal of each shunt zone is connected to an external application load, circuit, or device.

[0044] The shunt ceramic substrate achieves current distribution by regularly designing the electrical metal layer and dividing it into shunt zones of the same size. Each shunt zone is connected to a corresponding drive control terminal, enabling independent control and operation of the power components within each shunt zone. Adjacent shunt zones do not interfere with each other, further reducing stray current. At the same time, setting the shunt zones to be of the same or similar size ensures the uniformity of heat dissipation of the subsequent power modules, further improving the heat dissipation capacity of the power modules and enhancing reliability. Furthermore, the shunt zone design can significantly reduce the electrical wiring (bonding wire wiring) of the subsequent power components, reducing stray inductance and electromagnetic interference between the bonding wires and the electrical metal layer, further improving the reliability of the power modules.

[0045] based on Figure 1As shown, each power chip in the lower bridge is the power chip located on the left side of each shunt zone, and its output terminal is connected to the area corresponding to the S6 pin. Compared with the series-parallel connection method in the prior art, the outputs of each power chip in this application do not interfere with each other, and the temperature is more uniform during the current transmission process. This avoids the problem of uneven current shunting and easy failure of the lower bridge power chip, reduces the current resistance interference of any parallel power chips, and thus improves the reliability of the power chip and the current sharing capability.

[0046] This application provides a power module, relating to the field of power semiconductors, comprising: an electrical metal layer, a heat dissipation metal layer, and an insulating substrate disposed between the electrical metal layer and the heat dissipation metal layer; the electrical metal layer is provided with shunt regions corresponding one-to-one with the phase current, each shunt region having an equal size, and multiple power pins disposed near the edge of each shunt region near the electrical metal layer; for each shunt region, a control terminal, a power transmission terminal, and a sampling terminal are connected one-to-one with each power pin. The electrical metal layer is divided into multiple shunt regions according to phase, with adjacent shunt regions not interfering with each other, achieving independent control of different phase voltages while eliminating mutual interference, further reducing stray current. The shunt regions are set to the same or similar size, ensuring the uniformity of heat dissipation of the subsequent power module. Simultaneously, through a split-parallel connection, the shunt capability of each individual power chip unit is ensured, avoiding the power chip failure caused by uneven current distribution due to current resistance interference and magnetic distribution interference between power chips caused by series-parallel methods, significantly improving the current sharing capability of the power module and significantly improving the reliability of the power module.

[0047] Based on the above embodiments:

[0048] Figure 2 A schematic diagram of the structure of a diversion zone provided by this utility model;

[0049] Figure 3 This is a schematic diagram of another diversion zone provided by the present invention;

[0050] Figure 4 A schematic diagram of the current flow direction in a current shunt zone provided by this utility model;

[0051] In some embodiments, each shunt zone includes an electrical connector, a first power chipset, and a second power chipset. The electrical connector includes a bonding wire. The control terminal of the shunt zone includes a first control terminal and a second control terminal. The power transmission terminal includes a power input terminal, a power output terminal, and a three-phase AC terminal.

[0052] The control terminal of the first power chip group is used as the first control terminal, the first terminal of the first power chip group is used as the power input terminal, the second terminal of the first power chip group and the first terminal of the second power chip group are used as three-phase AC terminals, the control terminal of the second power chip group is used as the second control terminal, and the second terminal of the second power chip group is used as the power output terminal.

[0053] The first power chipset is used to invert the DC power input to the power transmission terminal and output it, while the second power chipset is used to rectify the three-phase AC power input to the power transmission terminal and output it.

[0054] This application divides the shunt into an upper bridge and a lower bridge, with the upper bridge being a first power chipset and the lower bridge being a second power chipset. The first power chipset is configured to perform inversion, and the second power chipset is configured to perform rectification.

[0055] By connecting the two power chipsets with electrical connectors, heat dissipation is facilitated.

[0056] In some embodiments, any shunt region on the electrical metal layer includes a power input sub-region 1, a first control sub-region 2, and a three-phase AC sub-region 3;

[0057] The power pins of the power input sub-area 1 are connected to the DC terminal of the external device, the power pins of the first control sub-area 2 are connected to the control signals of the external device, and the three-phase AC sub-area 3 is connected to the three-phase AC terminal of the external device.

[0058] The power input sub-region 1 is used to convert the DC power input from the external device into three-phase AC power based on the control signal input from the first control sub-region 2.

[0059] Furthermore, the power input and power output areas within the multiple shunt zones on the electrical metal layer can be arranged in the same or different ways.

[0060] In some embodiments, a first power chipset is disposed on a power input sub-region 1. A first end of the first power chipset is electrically connected to the power pins of the power input sub-region 1 via solder. A control end of the first power chipset is electrically connected to the power pins of a first control sub-region 2 via bonding wires. A second end of the first power chipset is electrically connected to the power pins of a three-phase AC sub-region 3 via bonding wires.

[0061] by Figure 1Taking the U-phase shunt region as an example, the power component includes a first power chip group, a second power chip group, and electrical connectors arranged in parallel and interleaved manner. The electrical connectors are bonding wires, such as copper wires, aluminum wires, etc., or bonding metal strips, such as copper strips, aluminum strips, etc. In this application, bonding wires are preferred. The first power chip group is located in the power input region, and the second power chip group is located in the power output region. The first power chip group is electrically connected to the power output region and the power pin G1 of the first control sub-region 2 through bonding wires, respectively. The second power chip group is electrically connected to the power pin G2 of the second control sub-region 4 and the power pin S2 of the power output sub-region 5 through bonding wires, respectively.

[0062] To reduce interference, the power pin U of the three-phase AC terminal, the power pin S1 of the first sampling sub-region 6 and the power pin G1 of the first control sub-region 2 are located at the top, while the power pin D1 of the power input sub-region 1, the power pin S2' of the second acquisition sub-region, the power pin G2 of the second control sub-region 4 and the power pin S2 of the power output sub-region 5 are located at the bottom.

[0063] In some embodiments, for any shunt region on the electrical metal layer, a second control sub-region 4 and a power output sub-region 5 are also included;

[0064] The power pin of the second control sub-area 4 is connected to the control signal of the external device, and the power output sub-area 5 is connected to the DC terminal of the external device.

[0065] Power input sub-region 1 is used to convert three-phase AC power input from external devices into DC power based on the control signal input from the second control sub-region 4.

[0066] In some embodiments, the second power chipset is disposed on the three-phase AC sub-region 3. The control terminal of the second power chipset is electrically connected to the power pin of the second control sub-region 4 via a bonding wire. The first terminal of the second power chipset is electrically connected to the power pin of the three-phase AC sub-region 3 via solder. The second terminal of the second power chipset is electrically connected to the power pin of the power output via a bonding wire.

[0067] by Figure 1 Taking the U-phase shunt zone as an example, the power component includes a first power chip group, a second power chip group, and electrical connectors arranged in parallel and interleaved manner. The electrical connectors are bonding wires, such as copper wires, aluminum wires, etc., or bonding metal strips, such as copper strips, aluminum strips, etc. In this application, bonding wires are preferred. The second power chip group is set in the three-phase AC sub-region 3. The second power chip group is electrically connected to the power pin S2' of the second acquisition sub-region, the power pin G2 of the second control sub-region 4, and the power pin S2 of the power output sub-region 5 through bonding wires.

[0068] In some embodiments, both the first power chipset and the second power chipset include at least two power chips connected in parallel.

[0069] In each first power chipset, the gate of the power chip serves as the control terminal of the first power chipset and is electrically connected to the power pins of the first control sub-region 2 via bonding wires. In each first power chipset, the drain of the power chip serves as the first terminal of the first power chipset and is electrically connected to the power pins of the power input sub-region 1 via solder. In each first power chipset, the source of the power chip serves as the second terminal of the first power chipset and is electrically connected to the power pins of the three-phase AC sub-region 3 via bonding wires.

[0070] In each second power chipset, the gate of the power chip serves as the control terminal of the second power chipset and is electrically connected to the power pins of the second control sub-region 4 via bonding wires. In each second power chipset, the drain of the power chip serves as the first terminal of the second power chipset and is electrically connected to the power pins of the three-phase AC sub-region 3 via solder. In each second power chipset, the source of the power chip serves as the second terminal of the second power chipset and is electrically connected to the power pins of the power output sub-region 5 via bonding wires.

[0071] The first power chipset is used as the upper bridge, and the second power chipset is used as the lower bridge.

[0072] The power chips are arranged in a bridge circuit on the electrical metal layer. The upper bridge and the lower bridge each include at least two power chips with the same function. The upper bridge power chips are connected in parallel with the lower bridge electrical metal layer through power connectors. This parallel connection ensures the current sharing capability of each individual power chip unit and avoids the current resistance interference and magnetic distribution interference between power chips caused by series and parallel methods, which can lead to uneven current distribution and failure of the power chips. This significantly improves the current sharing capability of the power module and greatly enhances the reliability of the power module.

[0073] Furthermore, the lower-bridge power chips are connected to the lower-bridge power metal layer via power connectors, the power chip control electrodes are connected to the control metal copper layer, and the lower-bridge power chips are connected to the lower-bridge sampling metal layer via power connectors. This optimizes loop noise, reduces flow impedance and internal interference, and makes the power chip control and sampling accurate and timely, thereby improving the reliability of the power module.

[0074] In some embodiments, for any shunt region on the electrical metal layer, a first sampling sub-region 6 and a second sampling sub-region 7 are further included, and the sampling end includes a first sampling end and a second sampling end;

[0075] In each first power chipset, the source of the power chip serves as the first sampling terminal of the first power chipset and is electrically connected to the power pins of the first sampling sub-region 6 via bonding wires. In each second power chipset, the source of the power chip serves as the second sampling terminal of the second power chipset and is electrically connected to the power pins of the second sampling sub-region 7 via bonding wires.

[0076] To facilitate the determination of the power module's working effect, a first sampling sub-region 6 and a second sampling sub-region 7 were set up to collect the current converted by the first power chip combination and the second power chip group.

[0077] Figure 5 A schematic diagram of the structure of a diversion zone provided by this utility model;

[0078] In some embodiments, for any shunt region on the electrical metal layer, a temperature acquisition sub-region 8 is also included;

[0079] A thermistor is installed on temperature acquisition sub-area 8 to acquire the temperature of the shunt zone.

[0080] An NTC thermistor is installed on either side of the power module to sample and provide feedback on the power unit's operating heat generation in real time. The lower bridge power detection terminal is separated from the main current path to avoid current-carrying interference. The upper bridge control circuit is also separated from the main current path (i.e., the lower bridge power detection is located to the right of the G pin, away from the S pin and away from the main current flow direction), which reduces the interference or crosstalk of the source current to the upper bridge power chip, making its power control more accurate and reliable.

[0081] In conclusion, Figure 1 The pin descriptions are as follows:

[0082] T1 and T2 are the power pins of the temperature acquisition sub-region of the U-phase shunt zone, U is the power pin of the three-phase AC sub-region of the U-phase shunt zone, S1 is the power pin of the first sampling sub-region of the U-phase shunt zone, G1 is the power pin of the first control sub-region of the U-phase shunt zone, D1 is the power pin of the power input sub-region of the U-phase shunt zone, S2' is the power pin of the second sampling sub-region of the U-phase shunt zone, G2 is the control pin of the second control sub-region of the U-phase shunt zone, and S2 is the power pin of the second sampling sub-region of the U-phase shunt zone.

[0083] Similarly, T3 and T4 are the power pins of the temperature acquisition sub-region of the V-phase shunt, V is the power pin of the three-phase AC sub-region of the V-phase shunt, S3 is the power pin of the first sampling sub-region of the V-phase shunt, G3 is the power pin of the first control sub-region of the V-phase shunt, D2 is the power pin of the power input sub-region of the V-phase shunt, S4' is the power pin of the second sampling sub-region of the V-phase shunt, G4 is the control pin of the second control sub-region of the V-phase shunt, and S4 is the power pin of the second sampling sub-region of the V-phase shunt.

[0084] W is the power pin of the three-phase AC sub-region of the W-phase shunt zone, S5 is the power pin of the first sampling sub-region of the W-phase shunt zone, G5 is the power pin of the first control sub-region of the W-phase shunt zone, D3 is the power pin of the power input sub-region of the W-phase shunt zone, S6' is the power pin of the second sampling sub-region of the W-phase shunt zone, G6 is the control pin of the second control sub-region of the W-phase shunt zone, and S6 is the power pin of the second sampling sub-region of the W-phase shunt zone.

[0085] Figure 6 A schematic diagram of the packaging structure of a power module provided by this utility model;

[0086] Specifically, in some embodiments, the power module further includes a power package;

[0087] The length and width of the power package are equal to those of the power substrate, and the height of the power package is lower than the height of the power pins.

[0088] This embodiment will include at least two of the aforementioned power modules in its packaging, with multiple power modules arranged side by side on the DBC ceramic substrate. This is suitable for application scenarios with more complex conditions, stricter control requirements, and higher voltage platforms. At the same time, thermistors and current sensing resistors can be added as needed to make the temperature control of the power modules more sensitive and rapid, thereby improving the safety and reliability of the power module applications.

[0089] For example, the power chip in this application is any one of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), IGBT & FRD (Insulated Gate Bipolar Transistor & Fast Recovery Diode), SiC (Silicon Carbide), and GaN (Gallium Nitride); the power package includes insulating and thermally conductive colloids such as silicon gel and epoxy resin.

[0090] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, article, or apparatus that includes said element.

[0091] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power module, characterized in that, include: An electrical metal layer, a heat dissipation metal layer, and an insulating substrate disposed between the electrical metal layer and the heat dissipation metal layer; The electrical metal layer is provided with shunt regions corresponding to the phase currents one by one. Each shunt region is of equal size. Multiple power pins are provided near the edge of the electrical metal layer in any shunt region. The power pins are used for electrical connection with external devices. For any given shunt zone, the control terminal, power transmission terminal, and sampling terminal of the shunt zone are all connected to corresponding power pins, so that the power chip in the shunt zone can rectify or invert the current input to the power transmission terminal based on the control of the control terminal, output the current through the power transmission terminal respectively, and feed the current back through the sampling terminal respectively.

2. The power module as described in claim 1, characterized in that, Each of the shunt zones includes an electrical connector, a first power chipset, and a second power chipset. The electrical connector includes a bonding wire. The control terminal of the shunt zone includes a first control terminal and a second control terminal. The power transmission terminal includes a power input terminal, a power output terminal, and a three-phase AC terminal. The control terminal of the first power chip group is used as the first control terminal, the first terminal of the first power chip group is used as the power input terminal, the second terminal of the first power chip group and the first terminal of the second power chip group are used as the three-phase AC terminal, the control terminal of the second power chip group is used as the second control terminal, and the second terminal of the second power chip group is used as the power output terminal. The first power chip group is used to invert the DC power input to the power transmission terminal and output it, while the second power chip group is used to rectify the three-phase AC power input to the power transmission terminal and output it.

3. The power module as described in claim 2, characterized in that, For any shunt region on the electrical metal layer, there are power input sub-regions, first control sub-regions and three-phase AC sub-regions; The power input sub-region's power pins are connected to the DC terminal of the external device, the power pins of the first control sub-region are connected to the control signal of the external device, and the three-phase AC sub-region is connected to the three-phase AC terminal of the external device. The power input sub-region is used to convert the DC power input from the external device into three-phase AC power based on the control signal input from the first control sub-region.

4. The power module as described in claim 3, characterized in that, The first power chip group is disposed on the power input sub-region. The first end of the first power chip group is electrically connected to the power pin of the power input sub-region via solder. The control end of the first power chip group is electrically connected to the power pin of the first control sub-region via bonding wire. The second end of the first power chip group is electrically connected to the power pin of the three-phase AC sub-region via bonding wire.

5. The power module as described in claim 3, characterized in that, For any shunt region on the electrical metal layer, a second control sub-region and a power output sub-region are also included; The power pins of the second control sub-region are connected to the control signals of the external device, and the power output sub-region is connected to the DC terminal of the external device; The power input sub-region is used to convert the three-phase AC power input from the external device into DC power based on the control signal input from the second control sub-region.

6. The power module as described in claim 5, characterized in that, The second power chip group is disposed on the three-phase AC sub-region. The control terminal of the second power chip group is electrically connected to the power pin of the second control sub-region via a bonding wire. The first terminal of the second power chip group is electrically connected to the power pin of the three-phase AC sub-region via solder. The second terminal of the second power chip group is electrically connected to the power pin of the power output via a bonding wire.

7. The power module as described in claim 6, characterized in that, Both the first power chipset and the second power chipset include at least two power chips connected in parallel; In each of the first power chipsets, the gate of the power chip serves as the control terminal of the first power chipset and is electrically connected to the power pins of the first control sub-region via bonding wires. In each of the first power chipsets, the drain of the power chip serves as the first terminal of the first power chipset and is electrically connected to the power pins of the power input sub-region via solder. In each of the first power chipsets, the source of the power chip serves as the second terminal of the first power chipset and is electrically connected to the power pins of the three-phase AC sub-region via bonding wires. The gate of the power chip in each of the second power chipsets serves as the control terminal of the second power chipset and is electrically connected to the power pins of the second control sub-region via bonding wires. The drain of the power chip in each of the second power chipsets serves as the first terminal of the second power chipset and is electrically connected to the power pins of the three-phase AC sub-region via solder. The source of the power chip in each of the second power chipsets serves as the second terminal of the second power chipset and is electrically connected to the power pins of the power output sub-region via bonding wires.

8. The power module as described in claim 7, characterized in that, For any shunt region on the electrical metal layer, there are also a first sampling sub-region and a second sampling sub-region, and the sampling end includes a first sampling end and a second sampling end; In each of the first power chipsets, the source of the power chip serves as the first sampling terminal of the first power chipset and is electrically connected to the power pins of the first sampling sub-region via bonding wires. In each of the second power chipsets, the source of the power chip serves as the second sampling terminal of the second power chipset and is electrically connected to the power pins of the second sampling sub-region via bonding wires.

9. The power module as described in claim 7, characterized in that, For any shunt region on the electrical metal layer, a temperature acquisition sub-region is also included; The temperature acquisition sub-area is equipped with a thermistor for acquiring the temperature of the shunt zone.

10. The power module according to any one of claims 1 to 9, characterized in that, The power module also includes a power package; The length and width of the power package are equal to those of the power substrate, and the height of the power package is lower than the height of the power pin.

Images