Semiconductor package

Abstract

A semiconductor package includes a substrate with a metal conductor, an integrated circuit (IC) die disposed on the substrate and electrically connected to the metal conductor of the substrate, a thermoelectric cooler (TEC) die electrically connected to the integrated circuit die and having a thermoelectric cooler disposed to cool respective regions of the semiconductor package, a temperature sensor arranged to measure a temperature of the respective regions of the semiconductor package, and a control circuit to operate the thermoelectric cooler to cool the respective regions based on the measured temperatures of the respective regions. The control can include determining whether a temperature indication signal satisfies a thermal management action criterion, and a thermal management action is performed in response to the determination that the temperature indication signal satisfies the thermal management action criterion.

Description

Technical Field

[0001] This disclosure relates to a semiconductor package and a method for manufacturing a semiconductor package. Background Technology

[0002] Thermal management is a challenge for semiconductor packages. Some of these packages contain integrated circuit (IC) chips that generate significant amounts of heat. For example, IC chips, such as high-level central processing units (CPUs) or graphics processing units (GPUs) for high-performance computing (HPC) or artificial intelligence (AI) applications, can output approximately 400-600 watts of total chip power or higher. Some semiconductor package designs aim to reduce package contact configuration by densely packing multiple IC chips (some or all of which may be high-power IC chips), thus creating a concentrated high-power heat source. Radiative and / or convective cooling can be provided through heat transfer via heat sinks and / or the substrate. However, the heat load that can be transferred through these heat transfer paths is limited. Furthermore, these heat transfer paths are uncontrolled and therefore designed to ensure adequate cooling under the “worst-case” conditions where the semiconductor package generates the most heat.

[0003] Another thermal management challenge is that heating can be localized. For example, a semiconductor package may include a central processing unit or graphics processing unit that generates a high amount of heat, connected to other integrated circuit chips, such as memory chips that generate less heat. Furthermore, heat generation varies over time, for example, during computationally complex tasks such as training artificial intelligence models, but at other times it may present a low thermal load. Utility Model Content

[0004] Some embodiments disclosed herein provide a semiconductor package for addressing prior art issues related to thermal management.

[0005] A semiconductor package includes a substrate, at least one integrated circuit wafer, and at least one thermoelectric cooler wafer. The substrate includes a metal conductor, the at least one integrated circuit wafer includes an integrated circuit, at least one integrated circuit wafer disposed on the substrate and electrically connected to the metal conductor of the substrate, and at least one thermoelectric cooler wafer includes at least one thermoelectric cooler wafer thermally connected to at least one integrated circuit wafer.

[0006] A semiconductor package is characterized by comprising a substrate, at least one integrated circuit wafer, and at least one thermoelectric cooler wafer. The substrate includes a plurality of metal conductors. The at least one integrated circuit wafer includes an integrated circuit, at least one integrated circuit wafer disposed on the substrate, and electrically connected to the plurality of metal conductors of the substrate. The at least one thermoelectric cooler wafer includes at least one thermoelectric cooler and a thermoelectric cooler wafer, wherein the at least one thermoelectric cooler wafer is disposed on the at least one integrated circuit wafer.

[0007] A semiconductor package includes a substrate, a plurality of integrated circuit wafers, a plurality of thermoelectric cooler wafers, and a temperature sensor. The substrate includes a plurality of conductors; the integrated circuit wafers are disposed on the substrate and electrically connected to the conductors of the substrate; the thermoelectric cooler wafers are thermally connected to the integrated circuit wafers and include a plurality of thermoelectric coolers configured to cool a plurality of respective regions of the semiconductor package; and the temperature sensor is arranged to measure the temperature of a respective region of the semiconductor package, wherein the integrated circuit wafers are configured to control the thermoelectric coolers.

[0008] Improved thermal management is achieved through the aforementioned semiconductor package. The thermoelectric cooler wafer of the semiconductor package can be advantageously placed at locations of high heat generation and can operate advantageously at time intervals corresponding to the generation of high heat loads. The thermoelectric cooler wafer actively draws heat from the package toward the air (or other environment) surrounding the semiconductor package. Attached Figure Description

[0009] The various features disclosed herein can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0010] Figure 1A and Figure 1B According to one embodiment, a side sectional view and a top view are schematically illustrated, the side sectional view and the top view including semiconductor packages of integrated circuit (IC) wafers and thermoelectric cooler (TEC) wafers;

[0011] Figure 2 According to one embodiment, a side cross-sectional view of a thermoelectric cooler wafer is schematically illustrated.

[0012] Figure 3 A schematic side cross-sectional view of a semiconductor package comprising an integrated circuit wafer and a thermoelectric cooler wafer is shown, wherein a metal conductor of a substrate is connected to the thermoelectric cooler wafer to deliver operating power to the thermoelectric cooler wafer.

[0013] Figure 4 A schematic side cross-sectional view of a semiconductor package is shown, which includes an integrated circuit wafer and a thermoelectric cooler wafer and power lines away from the substrate, the power lines being connected to deliver operating power to the thermoelectric cooler wafer.

[0014] Figure 5 A schematic side cross-sectional view of a semiconductor package is shown. According to one embodiment, the semiconductor package includes an integrated circuit wafer and a thermoelectric cooler wafer.

[0015] Figure 6and Figure 7 According to another embodiment, a side cross-sectional view of a semiconductor package including an integrated circuit wafer and a thermoelectric cooler wafer is schematically illustrated. Figure 6 ) and top view ( Figure 7 );

[0016] Figure 8 and Figure 9 According to another embodiment, a schematic side cross-sectional view of a semiconductor package including an integrated circuit wafer and a thermoelectric cooler wafer is shown. Figure 8 ) and top view ( Figure 9 );

[0017] Figure 10 and Figure 11 According to another embodiment, a side cross-sectional view of a semiconductor package including a thermoelectric cooler wafer that cools two integrated circuit wafers is schematically illustrated. Figure 10 ) and top view ( Figure 11 );

[0018] Figure 12 and Figure 13 According to another embodiment, a side cross-sectional view of a semiconductor package including two thermoelectric cooler wafers for cooling an integrated circuit wafer is schematically illustrated. Figure 12 ) and top view ( Figure 13 );

[0019] Figure 14 According to another embodiment, a side cross-sectional view of a semiconductor package including an integrated circuit wafer, a thermoelectric cooler wafer, and an interposer layer is schematically illustrated.

[0020] Figure 15 According to another embodiment, a side cross-sectional view of a semiconductor package including an integrated circuit wafer, a thermoelectric cooler wafer, and an interposer layer is schematically illustrated.

[0021] Figure 16 The thermoelectric cooler of the thermoelectric cooler wafer is schematically illustrated to output a thermoelectric signal indication of the temperature of the semiconductor package.

[0022] [Symbol Explanation]

[0023] 10, 80, 90, 100, 110, 120, 130, 140: Semiconductor package

[0024] 12, 121,122:Substrate

[0025] 14,14 tc ,14 tc1 ,14 tc2 ,154, 154 tc Conductor, metallic conductor, electrical conductor

[0026] 16,161,162,16 B ,16 T Integrated circuit (IC) chip

[0027] 18: Conductive joint

[0028] 20,201,202: Thermoelectric Cooler (TEC) chip, thermoelectric cooler chip

[0029] 22,221,222: Thermoelectric cooler

[0030] 24: p-type region

[0031] 26: n-type region

[0032] 28: Electrical conductor

[0033] 30: Support

[0034] 32: Electrical insulation

[0035] 34: First board

[0036] 36: Second board

[0037] 40: DC voltage source, voltage source

[0038] 42: Current

[0039] 50: Thermal interface materials

[0040] 52: Cover

[0041] 54: Filling material, filler

[0042] 56: Cooling plate

[0043] 58: Empty (DMY) socket, Empty socket

[0044] 60, 601, 602: Temperature sensors

[0045] 70: Electrical conductor

[0046] 72, 73: Electrical leads

[0047] 74, 75: Power leads, leads

[0048] 76, 84: Molding materials

[0049] 82: Intermediary Layer

[0050] 86,92: Conductive bumps

[0051] 94: Electricity

[0052] 96, 961, 962: Switches

[0053] 98,152: Redistribution Layer (RDL), Redistribution Layer

[0054] 150: Intermediary layer

[0055] 151: Electrical Conductive Block Detailed Implementation

[0056] The following disclosure provides many different implementations or examples of the various features of the subject matter provided. Specific examples of components and arrangements are described below to simplify this disclosure. These are merely examples and are not intended to be limiting. For example, in the following description, a first feature formed on or over a second feature may include implementations where the first and second features are formed in direct contact, and may also include implementations where an additional feature is formed between the first and second features. Furthermore, the figures and / or letters may be repeated in various examples of this disclosure. This repetition is for simplicity and clarity and does not in itself define the relationship between the various implementations and / or configurations discussed.

[0057] Furthermore, for ease of description, spatially related terms such as "below," "under," "lower part," "above," and "upper part" may be used to describe an element or feature relative to another element or feature as shown in the figure. In addition to the orientations depicted in the figure, spatially related terms are intended to include different orientations of the device in use or operation. The instrument may be otherwise oriented (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein may also be interpreted accordingly.

[0058] A semiconductor package includes one or more integrated circuit (IC) wafers fabricated on and / or in silicon or another semiconductor. The IC wafers are disposed on a substrate. The IC wafers may be directly attached to the substrate on which they are disposed, or may be arranged in a stacked manner (e.g., the bottommost IC wafer is directly attached to the substrate and one or more additional IC wafers are attached to the bottommost IC wafer). In another arrangement, the one or more IC wafers disposed on the substrate may be attached to an interposer, which is attached to the substrate. The interposer may, for example, include a silicon wafer with through-holes. The substrate and / or the interposer (if included) may optionally include one or more redistribution layers (RDLs) to provide electrical wiring for electrical signals and / or power to and / or from the one or more IC wafers.

[0059] Thermal management is a challenge for semiconductor packages. Some of these packages contain integrated circuit (IC) chips that generate significant amounts of heat. For example, IC chips, such as high-level central processing units (CPUs) or graphics processing units (GPUs) for high-performance computing (HPC) or artificial intelligence (AI) applications, can output approximately 400-600 watts of total chip power or higher. Some semiconductor package designs aim to reduce package contact configuration by densely packing multiple IC chips (some or all of which may be high-power IC chips), thus creating a concentrated high-power heat source. Radiative and / or convective cooling can be provided through heat transfer via heat sinks and / or the substrate. However, the heat load that can be transferred through these heat transfer paths is limited. Furthermore, these heat transfer paths are uncontrolled and therefore designed to ensure adequate cooling under the “worst-case” conditions where the semiconductor package generates the most heat.

[0060] Another thermal management challenge is that heating can be localized. For example, a semiconductor package may include a central processing unit or graphics processing unit that generates a high amount of heat, connected to other integrated circuit chips, such as memory chips that generate less heat. Furthermore, heat generation varies over time, for example, during computationally complex tasks such as training artificial intelligence models, but at other times it may present a low thermal load.

[0061] This disclosure discloses a semiconductor package with improved thermal management by including one or more thermoelectric cooler (TEC) wafers, the thermoelectric cooler wafers being housed within one or more integrated circuit wafers thermally connected to the semiconductor package. The thermoelectric cooler wafers can be advantageously positioned at locations of high heat generation and can operate advantageously at time intervals corresponding to periods of high heat load generation. The thermoelectric cooler of the thermoelectric cooler wafer actively draws heat from the package toward the air (or other environment) surrounding the semiconductor package. In some embodiments, the semiconductor package also includes one or more temperature sensors to provide feedback control of the thermoelectric cooler of the thermoelectric cooler wafer. For example, the thermoelectric cooler is only operable when its region is at a temperature higher than a threshold temperature. In some embodiments, the thermoelectric cooler can function as a temperature sensor, acting as a temperature-dependent thermoelectric signal readout.

[0062] Now refer to Figure 1A and Figure 1B The two views, a side sectional view and a top view, schematically depict the semiconductor package 10. Figure 1A The cross-sectional view along the marked Figure 1BThe tangent CC. The semiconductor package 10 includes a substrate 12 with a metal conductor 14. The substrate 12 can be of different types. In some embodiments, the substrate 12 may be a silicon wafer having through-silicon vias (TSVs) and redistribution layers on one or both sides of the conductor 14 (details not shown). In other embodiments, the substrate 12 may include a resin material housing a matrix of copper foil layers interconnected through vias forming the conductor 14 (details not shown). These are merely non-limiting illustrative examples of suitable embodiments of the substrate 12 with the metal conductor 14.

[0063] One or more (three exemplary) integrated circuit wafers 16 are disposed on a substrate 12 and electrically connected to metal conductors 14 via electrically conductive connections 18, such as bonding bump microarrays, ball grid arrays (BGAs), etc. An underfill material (not shown) such as epoxy resin (as a non-limiting illustrative example) may selectively fill the space around the conductive connections 18 to provide improved structural robustness and / or facilitate heat transfer from the one or more integrated circuit wafers 16 to the substrate 12. The electrically conductive connections 18 also provide electrical connections between the conductors 14 of the one or more integrated circuit wafers 16 and the substrate 12. By way of some non-limiting illustrative examples, the integrated circuit wafers may be: System-on-a-Chip (SoIC), monolithic wafers, static random access memory (SRAM) wafers, or combinations thereof. More generally, the one or more integrated circuit wafers 16 may be any type of integrated circuit wafer. As some further non-limiting examples, each integrated circuit chip 16 may be: a central processing unit; a graphics processing unit; a dynamic random access memory (DRAM) or other electronic memory chip; an integrated circuit chip carrying similar integrated circuits, such as similar radio frequency (RF) signal processing; various combinations, and / or so on. Again, only some non-limiting illustrative examples exist.

[0064] exist Figure 1A In the example, each integrated circuit wafer 16 is directly bonded to the substrate 12 via a conductive bonding portion 18. However, this is merely a non-limiting illustrative example. Various arrangements of two or more integrated circuit wafers can be used, such as using vias with through-silicon vias (TSVs) and having a semiconductor die mounted on an interposer, which in turn is mounted on the substrate 12 (the TSVs in the interposer provide electrical connection between the semiconductor die and the electrical conductors 14 of the substrate 12); a stack of two or more integrated circuit wafers, wherein only the bottom wafer is directly bonded to the substrate (or the interposer), etc. Furthermore, in another embodiment, it is contemplated that one or more integrated circuit wafers 16 are composed of a single integrated circuit wafer, which may be directly attached to the substrate 12 or may have a silicon interposer disposed between the single integrated circuit wafer and the substrate 12.

[0065] Continued reference Figure 1A and 1BAnd more reference Figure 2 , Figure 1A and 1B The semiconductor package 10 also includes at least one thermoelectric cooler chip 20, which includes at least one thermoelectric cooler 22 (schematically shown in...). Figure 2 One or more thermoelectric cooler wafers 20 are thermally connected to at least one integrated circuit wafer 16.

[0066] Continued specific reference Figure 2 This diagram shows a side cross-sectional view of a thermoelectric cooler 22. The illustrative thermoelectric cooler 22 operates in the Peltier effect and includes a p-type doped region 24 (i.e., p-type region 24) and a n-type doped region 26 (i.e., n-type region 26). The p-type region 24 and n-type region 26 are electrically connected in series via an electrical conductor 28. The illustrative p-type region 24 and n-type region 26 are embedded in a support 30, which may be, for example, silicon, resin, etc. If the support 30 is electrically conductive, then an electrical insulator 32 may surround the p-type region 24 and n-type region 26 to electrically insulate them from the support 30.

[0067] like Figure 2 As shown in the example, the first plate 34 and the second plate 36 are positioned at opposite ends of the p-type region 24 and the n-type region 26. The first plate 34 and the second plate 36 can be heat-conducting plates (such as heat-conducting but thermally insulating ceramic discs). A DC voltage source 40 applies a voltage to the series-connected p-type region 24 and n-type region 26, generating a current 42 flowing through the series-connected p-type region 24 and n-type region 26. Figure 2 As shown, this generates hole transport in the p-type region 24 and electron transport in the n-type region 26, where both holes and electrons move away from the first plate 34 and toward the second plate 36. Hole and electron transport thus operate via the Piltover effect to actively transfer heat from the first plate 34 to the second plate 36. Therefore, the thermoelectric cooler 22 operates to cool the block in thermal contact with the first plate 34 by discharging heat from the first block to the second plate 36. It is worth noting that, for simplicity, Figure 2 Only some interconnected p-type regions 24 and n-type regions 26 are shown. However, each thermoelectric cooler 22 may typically include any number of interconnected p-type regions 24 and n-type regions 26, which may be selectively arranged in a two-dimensional array, etc., to provide cooling on the respective two-dimensional regions.

[0068] Return to reference Figure 1A and 1B The thermoelectric cooler wafer 20 is disposed on the integrated circuit wafer 16 and is thermally connected to the integrated circuit wafer 16 through a thermal interface material 50 disposed between the thermoelectric cooler wafer 20 and the integrated circuit wafer 16. Figure 1A and1B In this example, thermoelectric cooler wafers 20 are arranged in a two-dimensional array, and a cover 52 is disposed on the thermoelectric cooler wafers 20. A filler material 54, such as epoxy resin, fills the cover 52. In this example, the cover 52, the filler material 54, and the thermoelectric cooler wafers 20 form a cooling plate 56 disposed on the integrated circuit wafer 16. (It is worth noting that in...) Figure 1B (The cover 52 and filler 54 are omitted to show the layout of the thermoelectric cooler wafer 20 and the underlying IC wafer 16). The cover 52 can be, for example, a metal (iron, nickel, chromium, tin, zinc, their alloys, etc.), carbon fiber material, glass, ceramic, etc. The thermal interface material 50 can be a thermal adhesive or other material that provides good thermal conductivity and adhesion to the integrated circuit wafer 16. (Alternatively, if the cover 52 is fastened to the substrate 12 by fasteners, etc., a non-adhesive material can be used as the thermal interface material 50).

[0069] Figure 1B The example layout also shows a blank (DMY) socket 58 for additional integrated circuit chips not included in the semiconductor package 10. Such a blank socket 58 (or multiple such sockets) can be selectively presented, for example, the substrate 12 is standardized and designed to support different chip arrangements for different modules or tasks (e.g., blank socket 58 can be used in some products to receive additional SRAM chips to provide modules with larger memory capacity).

[0070] like Figure 1B As shown in the top view, thermoelectric cooler wafers 20 are distributed across three (illustrated) integrated circuit wafers 16 to provide targeted cooling to the integrated circuit wafers 16. In some embodiments, thermoelectric cooler wafers 20 can operate continuously to provide continuous cooling of the integrated circuit wafers 16 via the Pittle effect. However, the illustrated semiconductor package 10 includes temperature sensors 60 (or, generally, at least one temperature sensor) to provide a temperature signal or a signal for controlling the use of thermoelectric cooler wafers 20. For example, the thermoelectric cooler wafers 20 disposed on the integrated circuit wafers 16 may only be activated when temperature signals from one or more temperature sensors 60 in the region including the integrated circuit wafers 16 indicate that the temperature has risen to approximately a threshold temperature. Advantageously, the cooling provided by the thermoelectric cooler wafers 20 can be activated both spatially (e.g., only in the region including the integrated circuit wafer where the temperature is too high) and temporally (e.g., only when the temperature is too high in the region). Temperature sensors 60 can be any suitable type of device that generates a temperature-dependent electrical output, such as thermocouples, thermal resistors, semiconductor-based temperature sensors, etc.

[0071] Reference Figure 3 and Figure 4 Two non-limiting illustrative configurations for electrical connection to thermoelectric cooler chip 20 are shown. Figure 3 and Figure 4 Each one is drawn Figure 1A A side cross-sectional view of a semiconductor package 10 includes a substrate 12 having a metal conductor 14, one or more integrated circuit wafers 16 bonded to the substrate via conductive joints 18, and a cooling plate 56. The cooling plate 56 includes a thermoelectric cooler wafer 20, a cover 52, and a filler material 54, and is in thermal contact with the integrated circuit wafers 16 via a thermal interface material 50. Figure 3 and Figure 4 In both cases, the thermoelectric cooler wafers 20 are electrically connected to each other via electrical conductors 70.

[0072] exist Figure 3 In an example of an electrical connection configuration, the metal conductor 14 of the substrate 12 is connected to at least one thermoelectric cooler wafer 20 to transmit operating power in Figure 3 At least one thermoelectric cooler of at least one thermoelectric cooler chip 20 in the substrate 12 has electrical leads passing through the metal conductor 14 of the substrate 12. Although not shown, similar leads can connect a temperature sensor 60 to the substrate 12 to read temperature signals from it via the metal conductor 14 of the substrate 12. In some embodiments, the electrical power for operating the thermoelectric cooler chip 20 can be provided externally from the semiconductor package 10.

[0073] In other embodiments, the electrical power for operating the thermoelectric cooler wafer 20 can be provided by one or more integrated circuit wafers 16 through the metal conductors 14 of the substrate 12. Specifically, the integrated circuit wafer 16 or a subset thereof (possibly a single integrated circuit wafer 16) includes the voltage of a voltage source applied to the electrical leads 72 and 73 of the cooling plate 56 by which the integrated circuits are implemented. This advantageously provides a separate semiconductor package 10, provided that a separate power supply for operating the thermoelectric cooler wafer 20 is not used.

[0074] exist Figure 4 In an example of electrical connection configuration, the semiconductor package 10 also includes power leads 74 and 75 remote from the substrate 12, connected to transmit operating power to at least one thermoelectric cooler wafer 20. In the illustrated example, selected epoxy resin or other molding material 76 is disposed on a cooling plate 56 to secure the connection between the leads 74 and 75 and the cooling plate 56.

[0075] It should be understood that Figure 3 and Figure 4 The exemplary electrical connection configuration is a non-limiting illustrative example, and other methods may be used to connect power to the thermoelectric cooler wafer 20 of the semiconductor package 10.

[0076] refer to Figure 5 Another non-limiting illustrative example of a semiconductor package 80 is illustrated, which has the same characteristics as... Figure 1A , Figure 1B and Figure 4 Similar configurations, with some modifications to illustrate some non-limiting examples of the variability expected in the configuration of semiconductor packages. Semiconductor package 80 includes two substrates 121 and 122, and includes a plurality of integrated circuit wafers 16, wherein the integrated circuit wafers 16 include two examples of stacked integrated circuit wafers 161 and 162, wherein the two integrated circuit wafers are stacked one on top of the other, demonstrating... Figure 5 The example shows a non-planar arrangement of the integrated circuit wafer 16. In a non-limiting illustrative example, the stacked integrated circuit wafer 161 may include a top integrated circuit wafer with an electrical integrated circuit (E-die) mounted on a bottom integrated circuit wafer with a photonic integrated circuit (P-die), in which case the semiconductor package may be an optoelectronic semiconductor package. Furthermore, the semiconductor package 80 includes an interposer 82 disposed between the integrated circuit wafer 16 and the substrate 12, and a molding material 84 disposed around the integrated circuit wafer 16 to provide structural robustness. The interposer 82 suitably includes a redistribution layer, through-silicon vias, or other electrical connections for transmitting electrical signals and / or power between the integrated circuit wafer 16 and the substrate 12. Silicon, sapphire, or other suitable materials may be used.

[0077] Figure 5 Examples include a cooling plate 56, which includes a thermoelectric cooler wafer 20 and a cover 52, as well as a filler material 54 that is in thermal contact with the integrated circuit wafer 16 via a thermal interface material 50 (and, in this example, via a molding material 84). Figure 4 In the example, Figure 5 In the example, the thermoelectric cooler wafer 20 is electrically interconnected via electrical conductors 70, and also includes power leads 74 and 75 located away from the substrate 12, and a selected epoxy resin or other molding material 76 disposed above the cooling plate 56 to secure the connection between the leads 74 and 75 and the cooling plate 56. Consideration should be given to combining... Figure 5 The semiconductor package 80 (variant not shown) is used to... Figure 3 Electrical connection configuration.

[0078] Figure 5 The bottoms of substrates 121 and 122 are also described as having conductive bumps 86, through which semiconductor packages 80 can be mechanically and electrically connected to printed circuit boards (PCBs, not shown) or other electronic systems, devices, or components. The conductive bumps 86 may be ball grid arrays, etc. Although... Figure 1A , Figure 3 and Figure 4 Not shown in the figure, such a back-side ball grid array, etc., can also be included on the back side of the substrate 12 of the semiconductor package 10 shown in those embodiments.

[0079] In the currently described example, the thermoelectric cooler wafer 20 is thermally connected to the integrated circuit wafer 16 via an arrangement in which the thermoelectric cooler wafer 20 is disposed on the integrated circuit wafer 16 and via a thermal interface material 50 disposed between the thermoelectric cooler wafer 20 and the integrated circuit wafer 16. These embodiments advantageously maximize the usable footprint of the integrated circuit wafer 16 because the thermoelectric cooler wafer 20 is disposed in a layer (or cooling plate 56) disposed on top of the integrated circuit wafer 16.

[0080] In a further embodiment described below, the thermoelectric cooler wafer 20 is disposed on the substrate 12, adjacent to and / or interposed between the integrated circuit wafers 16. In these embodiments, the metal conductors 14 of the substrate 12 provide thermal connection between the thermoelectric cooler of the thermoelectric cooler wafer 20 and the integrated circuit wafers 16. These embodiments advantageously provide connection of operating power to the thermoelectric cooler wafer 20 via the metal conductors 14 of the substrate 12, and the use of the metal conductors 14 to provide thermal connection with the cooled integrated circuit wafers 16 also advantageously allows for flexibility in the placement of the thermoelectric cooler wafer 20 relative to the integrated circuit wafers 16.

[0081] refer to Figure 6 and 7 A schematic side cross-sectional view of the semiconductor package 90 is shown. Figure 6 ) and the top view ( Figure 7 ).like Figure 6 As best seen in the image, the semiconductor package 90 includes a substrate 12 having metal conductors 14 and conductive bumps 86, an integrated circuit wafer 16, and an integrated circuit wafer 16. The semiconductor package 90 is mechanically and electrically connected to a printed circuit board, etc., via the conductive bumps 86. A thermoelectric cooler wafer 20 has a thermoelectric cooler 22. These components are as described above. Figure 6 and Figure 7 In this embodiment, the thermoelectric cooler wafer 20 is directly mounted to the substrate 12 via conductive bumps 92 (e.g., Figure 6 As shown), the conductive bump 92 also connects the thermoelectric cooler wafer 20 to the metal conductor 14 of the substrate 12 to receive power 94 for operating the thermoelectric cooler 22. The conductive bump 92 is also thermally conductive. Figure 6 As shown in the diagram, power 94 is applied as voltage source 40 to the p-type region 24 and n-type region 26 of the thermoelectric cooler 22 of the thermoelectric cooler wafer 20.

[0082] The portion of the metal conductor 14 of the substrate 12 also provides thermal connection to the thermoelectric cooler 22 and the integrated circuit wafer 16 of the thermoelectric cooler wafer 20 for cooling – indicated in Figure 6 Metal conductor 14 in tcProvides thermal connection between the thermoelectric cooler 22 of the thermoelectric cooler chip 20 and the integrated circuit chip 16. For example... Figure 7 As shown in the top view, metal conductor 14 tc The operating circuit of the thermoelectric cooler 22 is executed, therefore through the metal conductor 14 tc Thermal conduction and carrier transfer provide heat transfer from integrated circuit wafer 16 to thermoelectric cooler wafer 20, metal conductor 14 tc Optionally, a serpentine or other tortuous path can be formed under the integrated circuit wafer 16 to further facilitate thermal coupling.

[0083] exist Figure 6 and Figure 7 In this illustrative example, temperature sensor 60 provides a temperature signal indication to measure the temperature of integrated circuit 16, and integrated circuit chip 16 further executes switch 96, for example, a metal-oxide-semiconductor (MOS) transistor-based switch if the integrated circuit of integrated circuit chip 16 uses MOS technology. Switch 96 allows the operating circuitry of thermoelectric cooler 22 to pass through metal conductor 14. tc The thermoelectric cooler 22 of the thermoelectric cooler chip 20 can be turned off (e.g., by switching the metal-oxide-semiconductor switch 96 to a non-conductive state) or on (e.g., by switching the metal-oxide-semiconductor switch 96 to a conductive state) by using the temperature measurement of the temperature sensor 60 as a control input (e.g., a feedback signal). This allows the integrated circuit chip 16 to perform feedback control of the thermoelectric cooler 22 and operate the switch 96 to turn on the thermoelectric cooler 22 when the measured temperature exceeds the off and on thresholds, or to turn it off when the measured temperature drops below the off and on thresholds. The temperature sensor 60 can be integrated with the integrated circuit chip 16 (e.g., within the integrated circuit integration of the integrated circuit chip 16) or can be an external temperature sensor (e.g., thermally coupled), electrically connected to the integrated circuit chip 16 for reading by the integrated circuit chip 16.

[0084] Special reference Figure 6 In an example of integrated circuit wafer 16, a redistribution layer (RDL) 98 is included to facilitate the routing of electrical signals and / or power between integrated circuit wafer 16 and substrate 12. The redistribution layer may, for example, include a stack of patterned metallization layers embedded in an inner metal dielectric (IMD) material with vias connecting the patterned metallization layers. It will be understood that any integrated circuit wafer 16 may optionally include a redistribution layer 98, even if not shown in a particular embodiment.

[0085] Reference Figure 8 and Figure 9 A side cross-sectional view of the semiconductor package 100. Figure 8 ) and the top view ( Figure 9 (Illustrative illustration.) This implementation is similar to... Figure 6 and Figure 7 The implementation methods and corresponding components are indicated by the corresponding reference numerals. Figure 8 and Figure 9 The implementation method is different Figure 6 and Figure 7 The implementation method is in Figure 8 and Figure 9 In the embodiment, the thermoelectric cooler 22 of the thermoelectric cooler wafer 20 includes two illustrated p-type regions 24 and two illustrated n-type regions 26. This can be summarized as follows: the thermoelectric cooler 22 of the thermoelectric cooler wafer 20 can more generally include N p-type regions 24 and N n-type regions 26, where N can be 1 (e.g., ...). Figure 6 and Figure 7 ), 2 (such as) Figure 8 and Figure 9 ), 3, 4, 5, 6, 7, 8 or more. N p-type regions 24 and N n-type regions 26 are electrically connected in series, and the thermal conductor 14 of the substrate 12 is connected in series. tc A connection can be made, acting as a series interconnection, by running between selected p-type regions 24 and selected n-type regions 26. In a variant embodiment (not shown), this can be implemented as two (or more) independent thermoelectric coolers 22 on a separate thermoelectric cooler wafer 20 and a thermally conductive metal conductor 14 having a substrate 12. tc Each thermoelectric cooler 22 is thermally connected to the integrated circuit 16 for cooling.

[0086] exist Figures 6-9 In the example, a separate thermoelectric cooler chip 20 provides active cooling for a separate integrated circuit chip 16.

[0087] Reference Figure 10 and Figure 11 An example semiconductor package 110, demonstrating a separate thermoelectric cooler 22 on a separate thermoelectric cooler wafer 20, provides cooling for two integrated circuit wafers 161 and 162. In this example, the thermoelectric cooler wafer 20 is interposed between integrated circuit wafers 161 and 162, both of which are cooled by the thermoelectric cooler wafer 20. The thermally conductive metal conductor 14 of the substrate 12... tc1 Extending from the thermoelectric cooler 22 beneath the integrated circuit wafer 161, and the thermally conductive metal conductor 14 of the substrate 12 tc2 It extends from the thermoelectric cooler 22 beneath the integrated circuit chip 162. (See also: Special Reference) Figure 11 In some embodiments, the thermoelectric cooler wafer 20 functions as two independent thermoelectric coolers 221 and 222, with the first thermoelectric cooler 221 connected by a thermally conductive metal conductor 14 extending from the first thermoelectric cooler 221 to the substrate 12 beneath the first integrated circuit wafer 161. tc1The second thermoelectric cooler 222 is thermally connected to the first integrated circuit wafer 161; and similarly, the second thermoelectric cooler 222 is connected via a thermally conductive metal conductor 14 extending from the second thermoelectric cooler 222 to the substrate 12 beneath the second integrated circuit wafer 162. tc2 The first integrated circuit chip 162 is thermally connected. A first temperature sensor 601 monitors the temperature of the first integrated circuit chip 161, and based on a temperature measurement comparison between the off-to-on and on-to-off thresholds obtained through the first temperature sensor 601, it executes a first metal-oxide-semiconductor switch 961 on the integrated circuit of the first integrated circuit chip 161 to switch the first thermoelectric cooler 221 on and off. Similarly, a first temperature sensor 602 monitors the temperature of the first integrated circuit chip 162, and based on a temperature measurement comparison between the off-to-on and on-to-off thresholds obtained through the first temperature sensor 602, it executes a first metal-oxide-semiconductor switch 962 on the integrated circuit of the first integrated circuit chip 162 to switch the first thermoelectric cooler 222 on and off. In this way, a separate thermoelectric cooler chip 20 provides independent feedback control active cooling for both the first integrated circuit chip 161 and the second integrated circuit chip 162.

[0088] refer to Figure 12 and 13 An example semiconductor package 120 is shown providing cooling for a separate integrated circuit wafer 16, with two thermoelectric cooler wafers 201 and 202. In this example, the separate integrated circuit 16 is situated between two thermoelectric cooler wafers 201 and 202 that provide active cooling for the integrated circuit wafer 16. Thermally conductive metal conductor 14 of substrate 12... tc1 Extending from the first thermoelectric cooler wafer 20 beneath the first portion (e.g., the left side) of the integrated circuit wafer 16, and the thermally conductive metal conductor 14 of the substrate 12 tc2 The second thermoelectric cooler wafer 20 extends beneath a second portion (e.g., the right side) of the integrated circuit wafer 16. A first temperature sensor 601 measures the temperature of the first portion (e.g., the left side) of the integrated circuit wafer 16 and provides feedback to a first metal-oxide-semiconductor switch 961 that controls the switching of the thermoelectric cooler 22 of the first thermoelectric cooler wafer 201 on and off. Similarly, a second temperature sensor 602 measures the temperature of the second portion (e.g., the right side) of the integrated circuit wafer 16 and provides feedback to a second metal-oxide-semiconductor switch 962 that controls the switching of the thermoelectric cooler 22 of the second thermoelectric cooler wafer 202 on and off. This arrangement facilitates the independent active cooling of high-power integrated circuit wafers, such as integrated system wafers where non-uniform heat generation may occur in specific portions. However, Figure 12 and 13This illustration of implementation on two wafer portions (e.g., left and right portions) will be understood to extend to provide independent active cooling for three or more portions of an integrated circuit wafer. It will also be understood that, in a variant implementation (not illustrated), two thermoelectric coolers are implemented in a separate thermoelectric cooler wafer (e.g., Figure 11 (As shown) It can be used to provide independent active cooling for different parts of a single integrated circuit chip.

[0089] refer to Figure 14 and Figure 15 Further demonstrating example semiconductor package 130 ( Figure 14 ) and 140 ( Figure 15 These examples illustrate the inclusion of an interposer 150 disposed between at least one integrated circuit wafer 16 and a substrate 12. At least one integrated circuit wafer 16 is disposed on the interposer 150 disposed on the substrate 12 via an electrically conductive block 151. Figure 14 and Figure 15 As illustrated in the example, thermoelectric cooler wafer 20 is also disposed on the interposer layer 150. The interposer layer 150 includes a redistribution layer 152 with metal conductors 154 that transmit operating power to the thermoelectric cooler wafer 20, and at least one thermoelectric cooler 22 metal conductor 154 that thermally connects to at least one thermoelectric cooler wafer 20. tc At least one integrated circuit chip 16. Therefore, the metal conductor 154 of the interposer 150... tc The metal conductor 14 of the substrate 12 in the previous embodiment performs a similar function. tc .

[0090] Figure 15 Semiconductor package 140 and Figure 14 The semiconductor package 130 is different. Figure 14 The semiconductor package 130 includes a separate integrated circuit chip 16; however Figure 15 The semiconductor package 140 includes two integrated circuit wafers: a bottom integrated circuit wafer 16. B There are integrated circuit chips stacked on top 16 T This illustrates that two (or approximately three or more) integrated circuit wafers can be stacked in a semiconductor package.

[0091] In the current implementation, temperature sensor 60 can be used to measure temperature signals to provide feedback based on at least one integrated circuit chip 16 which can be configured (e.g., via appropriate integrated circuits such as an operational amplifier-based comparator and the described metal-oxide-semiconductor switch 96) to operate at least one thermoelectric cooler based on temperature signals measured by at least one temperature sensor 60 from at least one thermoelectric cooler chip.

[0092] refer to Figure 16 In some alternative embodiments, the thermoelectric cooler 22 can also function as a temperature sensor. (See illustration.) Figure 16 As shown, the voltage difference 160 between p-type region 24 and n-type region 26 indicates the temperature. Therefore, the temperature indication signal is measured (via, as shown in the diagram). Figure 16 The thermoelectric cooler 22 shown, or via thermal coupling or other dedicated temperature sensors 60 in other embodiments). The temperature indication signal is a temperature indication of the semiconductor package. Using the integrated circuit of the integrated circuit wafer 16 of the semiconductor package, this determines whether the temperature indication signal meets the thermal management action criteria. Thermal management action is performed relative to the thermal management action criteria in a decision response to determine whether the temperature indication signal meets the thermal management action criteria. Figure 16 In the examples, thermal management action guidelines may include: Guideline 1; Guideline 2; Guideline 3; and Guideline 4. In some implementations, Guideline 1; Guideline 2; Guideline 3; and Guideline 4 are each a higher temperature threshold in sequence. Figure 16 In this non-limiting illustrative example, when criterion 1 is met, the fan (not shown) configured to cool the semiconductor package is turned on. When criterion 2 is met (e.g., a temperature threshold higher than criterion 1), the fan speeds up (e.g., switching from low to high speed). When criterion 3 is met (e.g., a temperature threshold higher than criterion 2), the thermoelectric cooler 22 starts. When criterion 4 is met (e.g., a temperature threshold higher than criterion 3), the operating frequency of the integrated circuit wafer 16 is reduced (to reduce the power consumption of the integrated circuit wafer). This is merely an illustrative example of a non-limiting automatic temperature management workflow.

[0093] The following describes some implementation methods.

[0094] In a non-limiting embodiment, the semiconductor package includes: a substrate having a metal conductor; at least one integrated circuit wafer having an integrated circuit disposed on the substrate and electrically connected to the metal conductor of the substrate; and a thermoelectric cooler wafer having at least one thermoelectric cooler thermally connected to the at least one integrated circuit wafer.

[0095] In some embodiments, at least one thermoelectric cooler wafer is disposed on at least one integrated circuit wafer and thermally connected to at least one integrated circuit wafer via a thermal interface material disposed between the at least one thermoelectric cooler wafer and the at least one integrated circuit wafer. In some embodiments, a metal conductor of a substrate is connected to at least one thermoelectric cooler wafer to transmit operating power to at least one thermoelectric cooler of the at least one thermoelectric cooler wafer. In some embodiments, a plurality of power wires distal to the substrate are also included, connected to transmit operating power to at least one thermoelectric cooler of the at least one thermoelectric cooler wafer. In some embodiments, a cover and a filler material are also included. The cover is disposed on at least one thermoelectric cooler wafer, and the filler material fills the cover, wherein the cover, the filler material, and at least one thermoelectric cooler wafer form a cooling tray disposed on at least one integrated circuit wafer. In some embodiments, at least one thermoelectric cooler wafer is disposed on a substrate, and at least one thermoelectric cooler wafer is adjacent to and / or interposed between at least one integrated circuit wafer. In some embodiments, a metal conductor on the substrate is thermally connected to at least one thermoelectric cooler of at least one thermoelectric cooler wafer, and at least one integrated circuit wafer is thermally connected to at least one thermoelectric cooler wafer. In some embodiments, a metal conductor on the substrate conducts operating current through a plurality of p-type regions of at least one thermoelectric cooler wafer, and the metal conductor on the substrate is thermally connected to at least one integrated circuit wafer. In some embodiments, an interposer is also included. The interposer is disposed between at least one integrated circuit wafer and the substrate, and a plurality of metal conductors in the interposer are connected to at least one integrated circuit wafer and at least one thermoelectric cooler wafer. In some embodiments, at least one temperature sensor is also included, and at least one integrated circuit wafer is configured to operate at least one thermoelectric cooler wafer based on a temperature signal measured by the at least one temperature sensor. In some embodiments, at least one integrated circuit wafer is configured to measure a thermoelectric signal, which is generated by at least one thermoelectric cooler wafer and operated for control based on the measured thermoelectric signal.

[0096] In a non-limiting embodiment, the method of manufacturing a semiconductor package includes at least one integrated circuit wafer disposed on a substrate, providing thermal connections to at least one integrated circuit wafer, and providing at least one thermoelectric cooler for thermal contact with at least one integrated circuit wafer via thermal connection points.

[0097] In some embodiments, providing a thermal connection point on at least one integrated circuit chip includes disposing a thermal interface material on the at least one integrated circuit chip and, through the thermal connection point, thermally contacting at least one thermoelectric cooler on the at least one integrated circuit chip includes disposing at least one thermoelectric cooler on the thermal interface material. In some embodiments, the thermal connection point on at least one integrated circuit chip includes a plurality of metal conductors disposed on a substrate, and thermally contacting at least one thermoelectric cooler on at least one integrated circuit chip includes disposing at least one thermoelectric cooler on the substrate, the substrate being thermally connected to the at least one integrated circuit chip through metal conductors disposed in the substrate.

[0098] In a non-limiting embodiment, the method of manufacturing a semiconductor package includes setting at least one integrated circuit wafer on a substrate, setting a thermal interface material on at least one integrated circuit wafer, and setting at least one thermoelectric cooler on the thermal interface material to thermally contact at least one integrated circuit wafer through the thermal interface material.

[0099] In a non-limiting embodiment, the method of manufacturing a semiconductor package includes setting at least one integrated circuit wafer on a substrate, providing a metal conductor disposed in the substrate, and setting at least one thermoelectric cooler on the substrate and thermally connecting it to at least one integrated circuit via the metal conductor disposed in the substrate.

[0100] In a non-limiting embodiment, a method of operating the disclosed semiconductor package is described. This method includes: measuring a temperature indication signal, the temperature indication signal being a temperature indication of the semiconductor package; using an integrated circuit wafer of the semiconductor package, determining whether the temperature indication signal meets thermal management action criteria; and performing thermal management actions corresponding to the determination of the thermal management action criteria, the determination being that the temperature indication signal meets the thermal management action criteria. In some embodiments, the temperature indication signal may be a thermoelectric signal generated by a thermoelectric cooler of the semiconductor package. Thermal management action criteria may include the temperature indication signal indicating that the temperature of the semiconductor package is above a threshold temperature, and thermal management actions may include operating the thermoelectric cooler to cool the semiconductor package.

[0101] In a non-limiting embodiment, the semiconductor package includes: a substrate having a metal conductor; an integrated circuit wafer disposed on the substrate and electrically connected to the metal conductor of the substrate; a thermoelectric cooler wafer thermally connected to the integrated circuit wafer and including a thermoelectric cooler arranged to cool separate regions of the semiconductor package; and a temperature sensor arranged to measure the temperature of the thermoelectric cooler in the separate regions of the semiconductor package; wherein the integrated circuit wafer is configured to control the thermoelectric cooler.

[0102] In some embodiments, a thermoelectric cooler wafer and a thermal interface material are disposed on an integrated circuit wafer, with the thermal interface material disposed between the thermoelectric cooler wafer and the integrated circuit wafer. In some embodiments, a cover and epoxy resin are also included; the cover is disposed on the thermoelectric cooler wafer, and the epoxy resin fills the cover, wherein the cover, epoxy resin, and thermoelectric cooler wafer form a cooling pad, which is disposed on the integrated circuit wafer. In some embodiments, the thermoelectric cooler wafer is disposed on a substrate, adjacent to and / or interposed between integrated circuit wafers. In some embodiments, a conductor of the substrate is thermally connected to the thermoelectric cooler wafer of the integrated circuit wafer. In some embodiments, an interposer layer is also included, with the integrated circuit wafer and the thermoelectric cooler wafer disposed on the interposer layer, which is disposed on the substrate, wherein a conductor of the interposer layer is thermally connected to the thermoelectric cooler wafer of the integrated circuit wafer.

[0103] In a non-limiting embodiment, the semiconductor package includes a substrate with a metal conductor, an integrated circuit wafer disposed on the substrate and electrically connected to the metal conductor of the substrate, a thermoelectric cooler wafer thermally connected to the integrated circuit wafer, and a thermoelectric cooler having separate regions configured to cool the semiconductor package, a temperature sensor arranged to measure the temperature of the separate regions of the semiconductor package, and control circuitry to operate the thermoelectric cooler to cool the separate regions based on the measured temperature of the separate regions. Control may include determining whether a temperature indication signal satisfies thermal management action criteria, and performing a thermal management action in response to the determination that the temperature indication signal satisfies the thermal management action criteria.

[0104] The foregoing outline features of most embodiments enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that their various modifications, equivalents, and substitutions do not depart from the spirit and scope of this disclosure.

Claims

1. A semiconductor package, characterized by, include: A substrate comprising multiple metal conductors; At least one integrated circuit chip includes an integrated circuit, at least one integrated circuit chip disposed on the substrate and electrically connected to the plurality of metal conductors of the substrate; and At least one thermoelectric cooler wafer, including at least one thermoelectric cooler, wherein the thermoelectric cooler wafer is thermally connected to the at least one integrated circuit wafer.

2. The semiconductor package of claim 1, wherein, The at least one thermoelectric cooler wafer is disposed on the at least one integrated circuit wafer and is thermally connected to the at least one integrated circuit wafer through a thermal interface material, the thermal interface material being disposed between the at least one thermoelectric cooler wafer and the at least one integrated circuit wafer.

3. The semiconductor package of claim 2, wherein, Also includes: A cover body is disposed on the at least one thermoelectric cooler wafer; and A filling material is used to fill the cover. The cover, the filling material, and the at least one thermoelectric cooler wafer form a cooling tray, which is disposed on at least one integrated circuit wafer.

4. The semiconductor package of claim 1, wherein, The at least one thermoelectric cooler chip is disposed on the substrate, and the at least one thermoelectric cooler chip is adjacent to and / or interposed between the at least one integrated circuit chip.

5. The semiconductor package of claim 4, wherein, The metal conductor of the substrate is thermally connected to the at least one integrated circuit wafer and the at least one thermoelectric cooler of the at least one thermoelectric cooler wafer.

6. The semiconductor package of claim 5, wherein, The metal conductor of the substrate conducts an operating current through a plurality of p-type regions and a plurality of n-type regions of the at least one thermoelectric cooler wafer.

7. The semiconductor package of claim 4, wherein, Also includes: An interposer layer is disposed between the at least one integrated circuit chip and the substrate; The plurality of metal conductors in the interposer layer are connected to the at least one integrated circuit wafer and the at least one thermoelectric cooler of the at least one thermoelectric cooler wafer.

8. The semiconductor package of claim 1, wherein, in: The at least one integrated circuit chip is configured to measure a thermoelectric signal, the thermoelectric signal being generated by the at least one thermoelectric cooler of the at least one thermoelectric cooler chip and the at least one package cooler being operated for control based on the measured thermoelectric signal.

9. A semiconductor package, characterized by, include: A substrate comprising multiple metal conductors; At least one integrated circuit chip includes an integrated circuit, at least one integrated circuit chip disposed on the substrate and electrically connected to the plurality of metal conductors of the substrate; and At least one thermoelectric cooler chip, including at least one thermoelectric cooler and the thermoelectric cooler chip, wherein the at least one thermoelectric cooler chip is disposed on the at least one integrated circuit chip.

10. A semiconductor package, characterized by, include: A substrate comprising multiple conductors; Multiple integrated circuit chips are disposed on the substrate and electrically connected to the multiple conductors of the substrate; Multiple thermoelectric cooler wafers are thermally connected to the multiple integrated circuit wafers and include multiple thermoelectric coolers configured to cool multiple respective regions of the semiconductor package; as well as Temperature sensors are arranged to measure the temperature of the plurality of respective regions of the semiconductor package; The integrated circuit chip is configured to control the thermoelectric cooler.

Images