A chip package structure

Abstract

This disclosure provides a chip packaging structure including a substrate, a chip, a heat dissipation metal layer, multiple passive components, a heat sink, and an insulating protective cover. The chip is disposed in the central region of the substrate; the heat dissipation metal layer is disposed on the side of the chip facing away from the substrate; multiple passive components are disposed around the outer side of the chip in the edge region of the substrate; the heat sink is fixed to the edge region of the substrate and connected to the side of the heat dissipation metal layer facing away from the chip, the heat sink and the substrate together defining a cavity for accommodating the chip and passive components; an insulating protective cover has a receiving groove on the side facing the substrate, and the insulating protective cover is fixed to the edge region of the substrate to form a closed space between the receiving groove and the substrate, the closed space containing the multiple passive components. The use of an insulating protective cover improves the reliability of the packaging structure, saves packaging space, and reduces process costs.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductor packaging technology, specifically relating to a chip packaging structure. Background Technology

[0002] In existing chip packaging structures, the protection structure for passive components such as capacitors mainly adopts protective coatings and capacitor cap films to achieve the protection of passive components.

[0003] The technical problems with using protective coatings are as follows: due to the limitations of the chemical properties of the protective coating material, a phase transition will occur when the temperature exceeds 180°C, making the protective coating unsuitable for high-temperature reliability requirements; forming the protective coating requires two processes, spraying and curing, which increases the process cost.

[0004] Technical problems with using capacitor cover film: High temperature (above 150℃) and high pressure (above 10kg) are required to completely wrap the capacitor with tape, which is a harsh process and may damage the components; Under high temperature and high pressure, gaps are easily generated between the tape and the capacitor (such as the tape not being fully adhered or air bubbles remaining), resulting in poor sealing performance and affecting moisture / dust protection performance; Tape edges are prone to overflow, requiring the chip / tape and tape / heat sink spacing to be increased, occupying extra space and making it difficult to adapt to small package designs.

[0005] To address the aforementioned issues, it is necessary to propose a reasonably designed chip packaging structure that can effectively improve these problems. Utility Model Content

[0006] The present disclosure aims to at least solve one of the technical problems existing in the prior art and provide a chip packaging structure.

[0007] This disclosure provides a chip packaging structure, including:

[0008] substrate;

[0009] The chip is disposed in the central region of the substrate;

[0010] A heat dissipation metal layer is disposed on the side of the chip away from the substrate;

[0011] Multiple passive components are disposed around the outer side of the chip in the edge region of the substrate;

[0012] A heat sink is fixed to the edge region of the substrate and connected to the side of the heat dissipation metal layer opposite to the chip. The heat sink and the substrate together define a cavity for accommodating the chip and the passive component.

[0013] An insulating protective cover has a receiving groove on one side facing the substrate, so that a closed space is formed between the receiving groove and the substrate, and a plurality of the passive elements are placed in the closed space.

[0014] Optionally, the insulating protective cover is integrally molded.

[0015] Optionally, the insulating protective cover is capable of withstanding temperatures of at least 300°C.

[0016] Optionally, there is a preset gap between the insulating protective cover and the passive element.

[0017] Optionally, the receiving tank is provided with a first sidewall and a second sidewall that are relatively distributed, and a top wall that is respectively connected to the top of the first sidewall and the second sidewall;

[0018] The first sidewall is disposed between the passive component and the chip;

[0019] The second sidewall is disposed on the outside of the passive element;

[0020] The top wall is positioned above the passive element.

[0021] Optionally, the top wall is made of polyimide material.

[0022] Optionally, both the first sidewall and the second sidewall are made of silicone material.

[0023] Optionally, the thickness of the first sidewall and the second sidewall ranges from 100 μm to 3000 μm;

[0024] The distance between the first sidewall and the second sidewall is at least 600 μm.

[0025] Optionally, the thickness of the top wall ranges from 50 μm to 75 μm.

[0026] Optionally, an adhesive layer may also be included;

[0027] The insulating protective cover is fixed to the edge region of the substrate by the adhesive layer.

[0028] The chip packaging structure of this disclosure protects passive components by providing an insulating protective cover. A receiving groove is provided on the side of the insulating protective cover facing the substrate. The insulating protective cover is fixed to the edge area of ​​the substrate, forming a closed space between the receiving groove and the substrate. Multiple passive components are housed within this closed space. The insulating protective cover uses insulating material that does not interfere with the electrical signal transmission of the passive components. Multiple passive components are completely housed within the closed receiving groove, avoiding voids and providing comprehensive protection for the passive components. This prevents molten metal from splashing from the heat dissipation metal layer during high-temperature reflow from falling onto the passive components and causing short circuits, increasing the long-term reliability of the chip packaging structure. The size of the insulating protective cover can be set according to the size of the passive components, saving packaging space and meeting the packaging requirements of small packaging structures. Only a pick-and-place process is needed to mount the insulating protective cover onto the substrate, eliminating the need for additional packaging processes, saving process costs, and avoiding risks caused by thermal / mechanical stress. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of a chip packaging structure according to one embodiment of the present disclosure;

[0030] Figure 2 This is a schematic diagram of the assembly of an insulating protective cover and a substrate according to another embodiment of this disclosure;

[0031] Figure 3 This is a schematic diagram of the structure of an insulating protective cover according to another embodiment of this disclosure. Detailed Implementation

[0032] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0033] like Figure 1 As shown, this embodiment of the present disclosure provides a chip packaging structure 100, including a substrate 110, a chip 120, a heat dissipation metal layer 130, a plurality of passive components 140, a heat dissipation cover 150, and an insulating protective cover 160.

[0034] Chip 120 is disposed in the central region of substrate 110. Specifically, in this embodiment, the front side of chip 120 is flip-chip disposed in the central region of substrate 110 via conductive bumps. An underfill layer is provided between chip 120 and substrate 110, which allows chip 120 to be more securely fixed to substrate 110.

[0035] A heat dissipation metal layer 130 is disposed on the side of the chip 120 opposite to the substrate 110. That is, the heat dissipation metal layer 130 is disposed on the back side of the chip 120.

[0036] It should be noted that in this embodiment, the heat dissipation metal layer 130 is a thermal interface material layer, such as an indium foil. The heat dissipation metal layer 130 is used to solder the metal layer on the chip 120 to the metal layer on the heat sink 150 with flux, thereby achieving the function of heat dissipation for the chip 120.

[0037] like Figure 2 As shown, a plurality of passive components 140 are disposed around the outer side of the chip 120 on the edge region of the substrate 110. Specifically, the passive components 140 can be capacitors or inductors, etc., and the type of passive components 140 is not specifically limited in this embodiment. In addition, the number of passive components 140 is not limited and can be limited according to actual needs.

[0038] The heat sink 150 is fixed to the edge region of the substrate 110 and connected to the side of the heat dissipation metal layer 130 away from the chip 120. The heat sink 150 and the substrate 110 together define a cavity for accommodating the chip 120 and the passive component 140.

[0039] An insulating protective cover 160 is provided with a receiving groove 170 on the side facing the substrate 110. The insulating protective cover 160 is fixed to the edge area of ​​the substrate 110, so that a closed space is formed between the receiving groove 170 and the substrate 110. A plurality of passive components 140 are placed in the closed space.

[0040] The chip packaging structure of this disclosure protects passive components by providing an insulating protective cover. A receiving groove is provided on the side of the insulating protective cover facing the substrate. The insulating protective cover is fixed to the edge area of ​​the substrate, forming a closed space between the receiving groove and the substrate. Multiple passive components are housed within this closed space. The insulating protective cover uses insulating material that does not interfere with the electrical signal transmission of the passive components. Multiple passive components are completely housed within the closed receiving groove, avoiding voids and providing comprehensive protection for the passive components. This prevents molten metal from splashing from the heat dissipation metal layer during high-temperature reflow from falling onto the passive components and causing short circuits, increasing the long-term reliability of the chip packaging structure. The size of the insulating protective cover can be set according to the size of the passive components, saving packaging space and meeting the packaging requirements of small packaging structures. Only a pick-and-place process is needed to mount the insulating protective cover onto the substrate, eliminating the need for additional packaging processes, saving process costs, and avoiding risks caused by thermal / mechanical stress.

[0041] For example, in the embodiments, such as Figure 2 and Figure 3As shown, the insulating protective cover 160 is integrally molded. That is to say, the insulating protective cover 160 is pre-fabricated according to the size of the passive component 140. When mounting the insulating protective cover 160, it can be mounted on the substrate by pick-up process only, without the need for additional packaging processes, simplifying the mounting steps, eliminating the need for additional packaging equipment, saving process costs, and avoiding the risks caused by thermal / mechanical stress.

[0042] For example, in this embodiment, the insulating protective cover 160 can withstand a temperature of at least 300°C and can withstand the high temperature of solder ball reflow soldering without causing the insulating protective cover 160 to fail, thereby improving the reliability of the passive component 140 and thus improving the reliability of the entire chip packaging structure.

[0043] For example, such as Figure 1 As shown, there is a preset gap between the insulating protective cover 160 and the passive component 140. Compared with protective coatings and capacitor covers, the insulating protective cover 160 does not need to contact the passive component 140, thus avoiding damage to the passive component 140 and improving the reliability of the passive component 140.

[0044] like Figure 2 As shown, in this embodiment, the insulating protective cover 160 is a rectangular ring and includes four interconnected parts. Each part is provided with a receiving groove 170. The receiving grooves 170 of each part are connected and can cover the passive components 140 distributed around the chip 120.

[0045] For example, such as Figure 3 As shown, the receiving tank 170 is provided with a first sidewall 171 and a second sidewall 172 that are relatively distributed, and a top wall 173 that is connected to the top of the first sidewall 171 and the second sidewall 172 respectively. Specifically, the top of the first sidewall 171 and the second sidewall 172 is connected to the top wall 173, and the bottom of the first sidewall 171 and the second sidewall 172 is connected to the substrate 110, so that a closed space is formed between the receiving tank 170 and the substrate 110.

[0046] The first sidewall 171 is disposed between the passive element 140 and the chip 120; the second sidewall 172 is disposed on the outside of the passive element 140; and the top wall 173 covers the passive element 140.

[0047] For example, in this embodiment, the top wall 173 can be made of polyimide material, which can withstand the temperature of solder ball reflow soldering and protect the top of the passive component 140. The first side wall 171 and the second side wall 172 can both be made of silicone material, which can ensure that they can withstand the temperature of solder ball reflow soldering while supporting the top wall 173, thereby protecting the side walls of the passive component 140.

[0048] For example, in this embodiment, the thickness of the first sidewall 171 and the second sidewall 172 ranges from 100 μm to 3000 μm, which can adapt to the needs of different protection strengths. The distance between the first sidewall 171 and the second sidewall 172 is at least 600 μm to ensure coverage of the effective area of ​​the passive element 140.

[0049] It should be noted that the thickness of the first sidewall 171 and the second sidewall 172, as well as the distance between the first sidewall 171 and the second sidewall 172, are not specifically limited and can be selected according to the size of the passive element 140 that needs to be protected.

[0050] In this embodiment, the thickness of the sidewalls and top wall of the receiving tank and the distance between the two sidewalls can be set according to the size of the passive component, saving packaging space and meeting the packaging requirements of small packaging structures.

[0051] For example, in this embodiment, the thickness of the top wall 173 ranges from 50μm to 75μm, which can provide protection for the top of the passive component 140. It should be noted that this embodiment does not specifically limit the thickness of the top wall 173, and it can be selected according to actual needs.

[0052] For example, the chip package structure 100 also includes an adhesive layer; the insulating protective cover 160 is fixed to the edge region of the substrate 110 by the adhesive layer. The mounting process of the insulating protective cover 160 is simple, requiring no additional processes and saving process costs.

[0053] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the embodiments of this disclosure, and the embodiments of this disclosure are not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of this disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of this disclosure.

Claims

1. A chip package structure, characterized by, include: substrate; The chip is disposed in the central region of the substrate; A heat dissipation metal layer is disposed on the side of the chip away from the substrate; Multiple passive components are disposed around the outer side of the chip in the edge region of the substrate; A heat sink is fixed to the edge region of the substrate and connected to the side of the heat dissipation metal layer opposite to the chip. The heat sink and the substrate together define a cavity for accommodating the chip and the passive component. An insulating protective cover has a receiving groove on one side facing the substrate. The insulating protective cover is fixed to the edge area of ​​the substrate so that a closed space is formed between the receiving groove and the substrate. The closed space contains a plurality of the passive elements. The insulating protective cover is integrally molded; The insulating protective cover and the passive component have a preset gap, so that the insulating protective cover does not need to contact the passive component, thus avoiding damage to the passive component.

2. The chip package structure of claim 1, wherein, The insulating protective cover is capable of withstanding temperatures of at least 300°C.

3. The chip package structure of claim 1, wherein, The receiving tank is provided with a first sidewall and a second sidewall that are relatively distributed, and a top wall that is connected to the top of the first sidewall and the second sidewall respectively. The first sidewall is disposed between the passive component and the chip; The second sidewall is disposed on the outside of the passive element; The top wall is positioned above the passive element.

4. The chip package structure of claim 3, wherein, The top wall is made of polyimide material.

5. The chip package structure of claim 3, wherein, Both the first sidewall and the second sidewall are made of silicone material.

6. The chip packaging structure according to claim 3, characterized in that, The thickness of the first sidewall and the second sidewall ranges from 100 μm to 3000 μm; The distance between the first sidewall and the second sidewall is at least 600 μm.

7. The chip package structure of claim 3, wherein, The thickness of the top wall ranges from 50 μm to 75 μm.

8. The chip packaging structure according to any one of claims 1 to 7, characterized in that, It also includes the adhesive layer; The insulating protective cover is fixed to the edge region of the substrate by the adhesive layer.

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