Semiconductor structure, semiconductor device and electronic device

Abstract

The present disclosure relates to a semiconductor structure, a semiconductor device and an electronic device, the semiconductor structure comprising a chip assembly and an intermediate connection plate. The chip assembly comprises a computing chip and a storage chip located laterally to the computing chip, the storage chip comprising stacked cache units and main memory units. The computing chip and the cache units are connected to the intermediate connection plate by hybrid bonding structures. The semiconductor structure connects the computing chip and the storage chip to the intermediate connection plate by the hybrid bonding structures, thereby improving the IO density and having better thermal performance.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, semiconductor device, and electronic device. Background Technology

[0002] In 3.5D packaging technology, multiple chips are connected to a circuit board through an intermediary connection board. The chips include computing chips, I / O chips (interface chips), and memory chips with multiple 3D stacked memory cells. The multiple chips are electrically connected to the intermediary connection board through microbumps, which limits the I / O density. In addition, to protect the microbumps, material needs to be filled between the chips and the intermediary connection board, which affects the overall heat dissipation. Utility Model Content

[0003] The purpose of this disclosure is to provide a semiconductor structure, semiconductor device, and electronic device that improves I / O density and provides better thermal performance by connecting a computing chip to an interposer and a memory chip to an interposer via hybrid bonding.

[0004] To achieve the above objectives, according to a first aspect of this disclosure, this disclosure provides a semiconductor structure including a chip assembly and an interposer; the chip assembly includes a computing chip and a memory chip located sideways to the computing chip, the memory chip including stacked cache units and main memory units; The computing chip and the cache unit are respectively connected to the intermediate connection board via a hybrid bonding structure.

[0005] Optionally, the semiconductor structure further includes an interface chip located on the side of the computing chip, the interface chip being connected to the interfacing board via a hybrid bonding structure.

[0006] Optionally, the interface chip and the storage chip are located on opposite sides of the computing chip.

[0007] Optionally, the semiconductor structure further includes an encapsulation material layer that surrounds the circumference of the chip assembly and encapsulates the chip assembly and the interposer.

[0008] Optionally, the main memory unit and the cache unit are connected by a hybrid bonding connection.

[0009] Optionally, the hybrid bonding structure includes a first bonding layer located on the computing chip and the cache unit, respectively, and a second bonding layer located on the interposer, wherein the first bonding layer and the second bonding layer are connected by hybrid bonding.

[0010] Optionally, both the first bonding layer and the second bonding layer include a dielectric material portion and a metal portion.

[0011] Optionally, the computing chip includes an HPC chip, a GPU chip, or a SOC chip.

[0012] According to a second aspect of this disclosure, a semiconductor device is provided, comprising the semiconductor structure described above.

[0013] According to a third aspect of this disclosure, an electronic device is provided, comprising the semiconductor structure described above or comprising the semiconductor device described above.

[0014] The semiconductor structure disclosed herein, based on the aforementioned technical solution, includes a computing chip and a memory chip located to the side of the computing chip. The memory chip includes stacked cache units and main memory units. The computing chip and the cache units of the memory chip are electrically connected to an interposer via a hybrid bonding structure. This hybrid bonding connection provides higher I / O density between the computing chip and the interposer, and between the memory chip and the interposer. Furthermore, compared to related technologies, there is no need to add filler material between the chip and the interposer, resulting in better thermal performance of the semiconductor structure.

[0015] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 It is a structural diagram of a semiconductor structure in related technologies; Figure 2 These are structural diagrams of semiconductor structures provided in some embodiments of this disclosure; Figure 3 This is a flowchart of a method for fabricating a semiconductor structure provided in some embodiments of this disclosure; Figure 4 This is a schematic diagram of the formation of a first bonding layer in a computing chip, a memory chip, and an interface chip in some embodiments of this disclosure; Figure 5 This is a schematic diagram of a second bonding layer formed in an intermediate bonding plate in some embodiments of this disclosure.

[0017] Explanation of reference numerals in the attached figures 110 - Computing chip; 120 - Storage chip; 121 - Cache unit; 122 - Main memory unit; 130 - Interface chip; 140 - Packaging material layer; 200-Intermediate Connector Plate; 300 - Microbumps; 310 - Filler material; 400 - Hybrid bonding structure; 410 - First bonding layer; 420 - Second bonding layer; 411 - First dielectric material portion; 412 - First metal portion; 421 - Second dielectric material portion; 422 - Second metal portion. Detailed Implementation

[0018] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0019] In this disclosure, unless otherwise stated, directional terms such as "upper," "lower," "left," and "right" generally refer to upper, lower, left, and right relative to the figures; "inner" and "outer" refer to the inside and outside of the outline of the corresponding component; and "far" and "near" refer to the corresponding structure or component being away from or near another structure or component. Furthermore, the terms "first," "second," etc., used in this disclosure are for distinguishing one element from another and do not have sequential or importance implications. In addition, in the following description, when referring to the figures, unless otherwise explained, the same reference numerals in different figures denote the same or similar elements. The above definitions are for explanation and illustration only and should not be construed as limiting this disclosure.

[0020] In current CoWoS (Chip-on-Wafer-on-Substrate) packaging, especially in 3.5D packaging structures, the top chips, such as HPC (High-Performance Computing Chip 110), SRAM+DRAM (Cache + Main Memory), and IO Die (Interface Chip 130), are all connected to the top of the interposer 200 via microbumps 300. With the development of technology and the demand for smaller semiconductor sizes, the IO (Input / Output) density is limited, and the filling material 310 between the chip and the interposer 200 is also not conducive to heat dissipation.

[0021] The purpose of this disclosure is to provide a semiconductor structure, a method for fabricating the same, and an electronic device. This semiconductor structure provides higher I / O density and better thermal performance by connecting the computing chip 110 to the interposer 200 and the memory chip 120 to the interposer 200 via hybrid bonding.

[0022] To achieve the above objectives, such as Figures 2 to 5As shown, according to a first aspect of this disclosure, this disclosure provides a semiconductor structure including a chip assembly and an interposer 200; the chip assembly includes a computing chip 110 and a memory chip 120 located laterally to the computing chip 110, the memory chip 120 including stacked cache units 121 and main memory units 122; the computing chip 110 and the cache units 121 are respectively connected to the interposer 200 through a hybrid bonding structure 400.

[0023] The semiconductor structure disclosed herein, based on the above technical solution, includes a computing chip 110 and a memory chip 120 located to the side of the computing chip 110. The memory chip 120 includes stacked cache units 121 and main memory units 122. The computing chip 110 and the cache units 121 of the memory chip 120 are electrically connected to the interposer 200 via a hybrid bonding structure 400. In this 3.5D packaged semiconductor structure, the hybrid bonding connection provides higher I / O density between the computing chip 110 and the interposer 200, and between the memory chip 120 and the interposer 200. Furthermore, compared to related technologies, there is no need to add filler material 310 between the chip and the interposer 200, resulting in better thermal performance of the semiconductor structure.

[0024] It should be noted that the computing chip 110 can be HPC (High Performance Computing), which is a technology that uses supercomputers or computer clusters to solve complex scientific, engineering, and commercial problems. The memory chip 120 adopts a 3D stacked structure, including cache units 121 and main memory units 122 stacked on top of them, such as SRAM and DRAM.

[0025] The computing chip 110 and the intermediate connection board 200 are connected by a hybrid bonding structure 400, which enables high-speed data transmission and power supply between the computing chip 110 and the intermediate connection board 200. Of course, the intermediate connection board 200 can also be further connected to other chips or external circuits to build complex chip systems.

[0026] The hybrid bonding structure 400 replaces the microbumps 300 in related technologies, enabling high-density interconnects and allowing more connection points to be placed in a smaller area, significantly increasing the data communication bandwidth between chips. Furthermore, the direct copper-to-copper connection of hybrid bonding has lower resistance, reducing energy loss during signal transmission and minimizing signal propagation time delay. Hybrid bonding offers better heat dissipation performance; its compact structure and direct conductive path help improve thermal management and reduce heat generation. Hybrid bonding enables chips to be vertically stacked, significantly reducing the size of the final product and improving overall system performance.

[0027] like Figure 2 As shown, in some embodiments, the semiconductor structure further includes an interface chip 130 located on the side of the computing chip 110. The interface chip 130 is connected to the intermediate connection plate 200 via a hybrid bonding structure 400. The interface chip 130 and the memory chip 120 can be located on opposite sides of the computing chip 110, i.e., the interface chip can be located on one side of the computing chip 110, while the memory chip 120 can be located on the opposite side of the computing chip 110. This facilitates better connection between the two and the computing chip 110 and results in a relatively short connection path. For example, the cache unit 121 and main memory unit 122 of the memory chip 120 are 3D stacked on the right side of the computing chip 110, while the interface chip 130 is located on the left side of the computing chip 110. Both are electrically connected to the bottom intermediate connection plate 200 via a hybrid bonding structure 400. It should be noted that the terms "left" and "right" here are merely for ease of description, indicating that the memory chip 120 and the interface chip 130 are located on opposite sides of the computing chip 110. The left and right sides can be interchanged depending on the viewing angle, and this limitation does not constitute a restriction on the semiconductor structure. It is understood that the memory chip 120 and the interface chip 130 could also be located on the same side of the computing chip 110 or on opposite sides perpendicular to each other, as long as they can facilitate connection and communication with the computing chip 110.

[0028] The semiconductor structure also includes an interface chip 130, which is located laterally to the computing chip 110. The interface chip 130 can also be connected to the interposer 200 via a hybrid bonding structure 400. This hybrid bonding structure 400 enables high-density interconnection between the interface chip 130 and the interposer 200, thereby improving the integration and performance of the entire semiconductor structure. The hybrid bonding structure 400 may include direct copper-to-copper bonding, as well as additional heat treatment to enhance bond strength and electrical performance, ensuring a stable and reliable connection between the interface chip 130 and the interposer 200. The interface chip 130 can be used to realize data transmission and communication between the computing chip 110 and external devices. Connecting it to the interposer 200 via the hybrid bonding structure 400 reduces signal transmission delay and power consumption, and increases data transmission bandwidth and speed. Furthermore, the hybrid bonding connection between the interface chip 130 and the interposer 200 also improves the heat dissipation performance of the entire semiconductor structure, ensuring stability and reliability during high-power operation.

[0029] like Figure 2 As shown, optionally, the semiconductor structure also includes a packaging material layer 140, which surrounds the chip assembly circumferentially and encapsulates the chip assembly and the interposer 200.

[0030] In a semiconductor structure, the packaging material layer 140 is an indispensable and important component, which tightly wraps the chip components and the interposer 200 to form a complete protective shell.

[0031] In some embodiments, the encapsulation material layer 140 can encapsulate the computing chip 110, the memory chip 120 (including cache unit 121 and main memory unit 122), and the interface chip 130 on the upper surface of the interposer 200, forming a unified encapsulation structure. The encapsulation material layer 140 is typically composed of multiple layers of materials, including but not limited to molding compounds, ceramics, and metals. Through its dense structure and excellent insulation properties, the encapsulation material layer 140 can prevent the intrusion of moisture and gas, avoiding problems such as short circuits or corrosion caused by moisture. Simultaneously, the hardness and strength of the encapsulation material layer 140 are sufficient to withstand physical impacts and mechanical vibrations, reducing the risk of chip damage due to external forces during use. Furthermore, the encapsulation material layer 140 can also shield against external electromagnetic interference, ensuring stable and reliable electrical signal transmission within the chip, thereby improving the performance and reliability of the entire semiconductor structure.

[0032] The main memory unit 122 and the cache unit 121 can be 3D stacked in any suitable manner to form the memory chip 120. In some embodiments, the main memory unit 122 and the cache unit 121 are connected by hybrid bonding.

[0033] The main memory unit 122 and the cache unit 121 are connected using advanced hybrid bonding technology. Specifically, hybrid bonding technology replaces traditional bump or solder ball interconnects with a direct copper-to-copper connection, enabling ultra-fine pitch stacking and packaging of the main memory unit 122 and the cache unit 121 within a very small space. This connection method not only significantly improves the efficiency and stability of data transmission but also effectively reduces energy loss and time delay during signal transmission. Furthermore, the application of hybrid bonding technology makes the interconnection between the main memory unit 122 and the cache unit 121 tighter and more reliable, thereby improving overall system performance while also enhancing system stability and durability.

[0034] It should be noted that the main memory unit 122 (RAM) may also include multiple storage modules stacked in sequence for storing data. The cache unit 121 is connected below the multiple storage modules and continuously provides the computing chip 110 with the data that needs to be read.

[0035] like Figure 4 As shown, the hybrid bonding structure 400 includes a first bonding layer 410 located on the computing chip 110 and the cache unit 121, respectively, and a second bonding layer 420 located on the intermediate connection board 200. The first bonding layer 410 and the second bonding layer 420 are connected by hybrid bonding.

[0036] The computing chip 110 has a first bonding layer 410, and the cache unit 121 of the memory chip 120 also has a first bonding layer 410. The metal portion 412 density of the first bonding layer 410 on the two chips can be different. The interposer 200 has two second bonding layers 420 respectively corresponding to the first bonding layer 410 of the computing chip 110 and the first bonding layer 410 of the cache unit 121. The first bonding layer 410 of the computing chip 110 is mixed-bonded with the corresponding second bonding layer 420 on the interposer 200, and the first bonding layer 410 of the cache unit 121 is mixed-bonded with the corresponding second bonding layer 420 on the interposer 200. This allows the computing chip 110 and the memory chip 120 to be electrically connected to the interposer 200 using a mixed bonding structure 400, thereby improving I / O density and thermal performance.

[0037] like Figure 4 and Figure 5 As shown, in some embodiments, both the first bonding layer 410 and the second bonding layer 420 include a dielectric material portion and a metal portion. The first bonding may include a first dielectric material portion 411 and a first metal portion 412. The first metal portion 412 may be copper, aluminum, or other suitable conductive material for transmitting electrical signals; the first dielectric material portion 411 serves for insulation and protection, preventing signal interference and short circuits. For example, the first dielectric material portion 411 may be made of a non-conductive material such as silicon dioxide.

[0038] Similarly, the second bonding layer 420 may also include a second dielectric material portion 421 and a second metal portion 422, corresponding respectively to the first dielectric material portion 411 and the first metal portion 412 on the chip. The second metal portion 422 may be copper, aluminum, or other suitable conductive material for transmitting electrical signals; the second dielectric material portion 421 serves as insulation and protection, preventing signal interference and short circuits. For example, the second dielectric material portion 421 may be made of a non-conductive material such as silicon dioxide.

[0039] The bonding connection between the first bonding layer 410 and the second bonding layer 420 is the core component of the hybrid bonding structure 400, and its quality and performance directly affect the reliability and electrical performance of the entire chip package. Bonding connections are typically achieved through processes such as thermocompression bonding, ultrasonic bonding, or direct metal bonding. In thermocompression bonding, appropriate temperature and pressure are applied to induce atomic diffusion between the metal layers, forming a strong bond. Ultrasonic bonding utilizes ultrasonic energy to activate the metal surface, promoting bonding between metals. Direct metal bonding, under specific conditions, allows the metal layers to directly form chemical or metallic bonds.

[0040] The embodiments of this disclosure combine hybrid bonding structure 400 technology with 3.5D packaging technology. The chip is connected to the intermediate interconnect 200 via the hybrid bonding structure 400, thereby increasing input / output density and achieving high system integration and miniaturization.

[0041] It should be noted that the computing chip 110 in this embodiment may include an HPC chip (High-Performance Computing Chip), a GPU chip (Graphics Processing Unit), or a SOC chip (System on Chip). Of course, it can also be other chips capable of computing, such as a CPU chip (Central Processing Unit).

[0042] like Figure 3 As shown, this disclosure also provides a method for fabricating a semiconductor structure, the method comprising steps S100 to S300.

[0043] In step S100, a first bonding layer 410 is formed in the cache unit 121 of the computing chip 110 and the storage chip 120, respectively. The storage chip 120 includes stacked cache units 121 and main memory units 122.

[0044] In step S200, a second bonding layer 420 corresponding to the first bonding layer 410 is formed on the intermediate connection plate 200.

[0045] In step S300, the first bonding layer 410 of the computing chip 110 and the first bonding layer 410 of the storage chip 120 are respectively bonded together with the second bonding layer 420 of the intermediate connection plate 200.

[0046] The memory chip 120 includes a cache unit 121 and a main memory unit 122 3D stacked thereon. First bonding layers 410 are formed on the cache units 121 of both the computing chip 110 and the memory chip 120. Second bonding layers 420, corresponding to the two first bonding layers 410, are formed on the interposer 200. A hybrid bonding structure 400 is formed by connecting the two first bonding layers 410 and the second bonding layers 420 to electrically connect the computing chip 110 and the memory chip 120 of the chip assembly to the interposer 200. Compared with the microbump 300 connection method in related technologies, the hybrid bonding connection enables high-density interconnection between the chip and the interposer 200, allowing more connection points to be arranged within a limited chip area. This improves the chip's integration and functional complexity, providing strong support for the design and manufacturing of high-performance chips and meeting the requirements of modern electronic devices for chip performance and miniaturization. It also enhances the mechanical stability between the chip and the interposer 200. Meanwhile, hybrid bonding helps improve the chip's heat dissipation performance. Because the bonding layer material has good thermal conductivity, it can effectively conduct the heat generated by the chip to the interposer 200 and external heat dissipation structure, reducing the chip's operating temperature, improving its stability and lifespan, and ensuring its reliability under high-power operating conditions.

[0047] like Figure 4 As shown, a first bonding layer 410 is formed on the chip of the chip assembly. Specific operations may include: firstly, cleaning and pre-treating the surfaces of the computing chip 110 and the cache unit 121 of the memory chip 120 to remove impurities and oxides to ensure good adhesion of the bonding layer. Then, using processes such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), a first dielectric material portion 411 and a first metal portion 412 (such as copper, gold, etc.) are deposited to form a first bonding layer 410 of uniform thickness. The thickness of this bonding layer should be controlled within the micrometer range to ensure the strength and electrical performance of subsequent bonding.

[0048] like Figure 5 As shown, similarly, two second bonding layers 420 corresponding to the computing chip 110 and the memory chip 120 are formed on the interposer 200. The specific operation may include: first, cleaning and pre-treating the surface of the interposer 200. Then, using a deposition process similar to that on the chip, a second dielectric material portion 421 and a second metal portion 422 are deposited to form the second bonding layer 420. The thickness of this bonding layer should also be controlled within the micrometer range, and its material and thickness should match those of the first bonding layer 410 to ensure good bonding compatibility.

[0049] The metal part is used to realize signal connection, and its material can be copper, gold, etc.; the dielectric material part is used for isolation and insulation, and its material can be SiO2, etc.

[0050] After both the first bonding layer 410 and the second bonding layer 420 are prepared, the first bonding layer 410 of the chip and the second bonding layer 420 of the intermediate interconnect 200 are mixed-bonded together. This bonding process is usually carried out under high temperature and high pressure. Through techniques such as thermosetting bonding, atoms in the first bonding layer 410 and the second bonding layer 420 diffuse and fuse with each other to form a strong chemical bond. After the mixed-bonding connection, a highly reliable physical and electrical connection is achieved between the chip and the intermediate interconnect 200. From a physical connection perspective, the two are tightly bonded together, forming a stable integral structure with good mechanical strength, which can effectively resist various external impacts that may be encountered during chip use, ensuring the structural stability of the chip assembly.

[0051] In some embodiments, to connect the interface chip 130 to the interposer 200, the method further includes: forming a first bonding layer 410 on the interface chip 130; forming a second bonding layer 420 corresponding to the first bonding layer 410 on the interposer 200; and hybrid bonding the first bonding layer 410 of the interface chip 130 and the second bonding layer 420 of the interposer 200. Similarly, using the above method, a first bonding layer 410 is formed on the interface chip 130, and a second bonding layer 420 corresponding to the first bonding layer 410 of the interface chip 130 is formed on the interposer 200. By hybrid bonding the first bonding layer 410 of the interface chip 130 and the second bonding layer 420 of the interposer 200, the interface chip 130 is also electrically connected through the hybrid bonding structure 400. This increases the I / O density between the interface chip 130 and the interposer 200, and also improves the thermal performance between them.

[0052] In some embodiments, the method further includes encapsulating the computing chip 110, the memory chip 120, and the interface chip 130 with the interfacing board 200 using an encapsulation material layer 140. By encapsulating the chips (including the computing chip 110, the memory chip 120, and the interface chip 130) and the interfacing board 200 with the encapsulation material layer 140, good physical protection can be provided for the chip assembly, effectively preventing external environmental factors such as dust, moisture, and mechanical shock from eroding and damaging the chips inside the encapsulation structure, thereby significantly improving the reliability and stability of the chipset. The encapsulated chipset can better adapt to various complex application scenarios, extend its service life, and provide strong support for the stable operation of electronic devices.

[0053] According to a second aspect of this disclosure, a semiconductor device is provided, comprising the semiconductor structure described above. Therefore, this semiconductor device also possesses all the advantages of the semiconductor structure. The semiconductor device further includes a packaging substrate, wherein an intermediate connection plate 200 is electrically connected to the packaging substrate on the side opposite to the chip assembly to enable signal or power transmission.

[0054] According to a third aspect of this disclosure, an electronic device is also provided, which includes the aforementioned semiconductor structure or semiconductor device, and therefore also possesses all the advantages of the aforementioned semiconductor structure and semiconductor device. It should be noted that this electronic device includes, but is not limited to, mobile phones, electronic watches, tablet computers, laptops, microcontrollers, servers, etc.

[0055] In summary, the semiconductor structure, semiconductor device, and electronic device disclosed herein have a 3.5D package structure, comprising a computing chip 110, a memory chip 120 located to the side of the computing chip 110, and an interface chip 130. The memory chip 120 includes stacked cache units 121 and main memory units 122. The computing chip 110, the interface chip 130, and the cache units 121 of the memory chip 120 are electrically connected to an interposer 200 via a hybrid bonding structure 400. This hybrid bonding connection provides higher I / O density between the computing chip 110 and the interposer 200, the interface chip 130 and the interposer 200, and the memory chip 120 and the interposer 200. Furthermore, compared to related technologies, there is no need to add filler material 310 between the chip and the interposer 200, resulting in better thermal performance of the semiconductor structure.

[0056] The hybrid bonding structure 400 achieves efficient electrical interconnection and mechanical support between the chip and the interposer 200 through the bonding connection of the first bonding layer 410 and the second bonding layer 420. It has advantages such as high density, low resistance, low latency and good heat dissipation performance, and is suitable for various high-performance chip and advanced packaging technology application scenarios.

[0057] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0058] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0059] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A semiconductor structure, characterized by, It includes a chip assembly and an interfacing board; the chip assembly includes a computing chip and a memory chip located to the side of the computing chip, the memory chip including stacked cache units and main memory units; The computing chip and the cache unit are respectively connected to the intermediate connection board via a hybrid bonding structure.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure also includes an interface chip located on the side of the computing chip, and the interface chip is connected to the intermediate connection board through a hybrid bonding structure.

3. The semiconductor structure of claim 2, wherein, The interface chip and the storage chip are located on opposite sides of the computing chip.

4. The semiconductor structure of claim 1, wherein, The semiconductor structure further includes an encapsulation material layer that surrounds the circumference of the chip assembly and encapsulates the chip assembly and the interposer.

5. The semiconductor structure of claim 1, wherein, The main memory unit and the cache unit are connected by a hybrid bonding connection.

6. The semiconductor structure of any of claims 1-5, wherein, The hybrid bonding structure includes a first bonding layer located on the computing chip and the cache unit, respectively, and a second bonding layer located on the interposer board, wherein the first bonding layer and the second bonding layer are connected by hybrid bonding.

7. The semiconductor structure of claim 6, wherein, Both the first bonding layer and the second bonding layer include a dielectric material portion and a metal portion.

8. The semiconductor structure of claim 1, wherein, The computing chip includes an HPC chip, a GPU chip, or a SOC chip.

9. A semiconductor device, characterized by comprising: Includes the semiconductor structure described in any one of claims 1-8.

10. An electronic device, comprising: It includes the semiconductor structure described in any one of claims 1-8 or the semiconductor device described in claim 9.

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