Package substrate

Abstract

The packaging carrier includes a packaging substrate, at least one limiting column, a chip and a packaging layer. The packaging substrate includes an insulating layer and a circuit layer, the circuit layer is embedded in the insulating layer, at least one first recess is formed in the insulating layer; the limiting column is located in the first recess and protrudes from the insulating layer; the chip is located on the surface of the insulating layer provided with the limiting column, the chip is electrically connected with the circuit layer; the packaging layer covers the chip and the limiting column. The limiting column is arranged in the packaging carrier, the interaction force between the packaging layer and the packaging substrate is increased, thereby improving the connection reliability of the packaging layer and the packaging substrate, so that the packaging carrier can resist external force impact, vibration and the like, thereby improving the problem of mutual separation of the packaging substrate and the packaging layer; in addition, the limiting column is beneficial to dispersing the stress generated during the use of the packaging carrier, avoiding the problem of cracking of the packaging layer caused by stress concentration.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and in particular to a packaging substrate. Background Technology

[0002] Molding is a process in which encapsulating resin is injected into a mold under high temperature and pressure and cured to form a shape that covers the chip and adheres to the encapsulation substrate. With the continuous development of the semiconductor industry, chip integration is becoming increasingly sophisticated, requiring more reliable encapsulation within a smaller space. However, the reduction in space dimensions increases the difficulty of molding, making it prone to delamination between the encapsulation substrate and the encapsulation resin due to interfacial stress or decreased adhesive strength. Utility Model Content

[0003] Therefore, it is necessary to provide a packaging carrier board with high connection reliability.

[0004] The packaging substrate includes a packaging substrate, at least one positioning post, a chip, and a packaging layer. The packaging substrate includes an insulating layer and a circuit layer, the circuit layer being embedded in the insulating layer, and at least one first groove being formed in the insulating layer; the positioning post is located in the first groove and protrudes from the insulating layer; the chip is located on the surface of the insulating layer where the positioning post is provided, and the chip is electrically connected to the circuit layer; the packaging layer covers the chip and the positioning post.

[0005] A limiting post is provided in the packaging carrier, with part of the limiting post located in the packaging substrate and another part embedded in the packaging layer. This increases the interaction force between the packaging layer and the packaging substrate, thereby improving the connection reliability between the packaging layer and the packaging substrate. This allows the packaging carrier to resist external impacts and vibrations, thus improving the problem of separation between the packaging substrate and the packaging layer. In addition, the limiting post in the packaging carrier helps to disperse the stress generated during the use of the packaging carrier, avoiding stress concentration that could lead to cracking of the packaging layer or failure at the connection between the packaging layer and the packaging substrate. For example, when the material expands and contracts due to temperature changes, the limiting post can share some of the stress. Attached Figure Description

[0006] Figure 1 This is a cross-sectional schematic diagram of the packaging carrier provided in some embodiments of this application.

[0007] Figure 2 This is a top view of the packaging carrier provided in an embodiment of this application.

[0008] Figure 3 This is a cross-sectional flow diagram illustrating the formation of the limiting post on the encapsulation carrier plate according to some embodiments of this application.

[0009] Figure 4 A cross-sectional schematic diagram of the packaging carrier provided for other embodiments of this application.

[0010] Figure 5 This is a cross-sectional flow diagram illustrating the formation of the limiting post on the encapsulation carrier plate, as provided in some other embodiments of this application.

[0011] Explanation of main component symbols The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0012] To better understand the above-mentioned objectives, features, and advantages of this application, the application will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Many specific details are set forth in the following description to provide a thorough understanding of this application; the described embodiments are merely some, not all, of the embodiments described in this application.

[0013] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The term "and / or" as used herein includes all and any combination of one or more of the associated listed items.

[0014] In the various embodiments of this application, for ease of description and not limitation, the term "connection" used in the patent application specification and claims is not limited to physical or mechanical connections, whether direct or indirect. Terms such as "upper," "lower," "above," "below," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship also changes accordingly.

[0015] Please see Figure 1 , Figure 1 This is a cross-sectional schematic diagram of a packaging carrier 100 provided in some embodiments of this application. The packaging carrier 100 may include a packaging substrate 10, at least one limiting post 20, a chip 30, and a packaging layer 40. Part of the limiting post 20 is located in the packaging substrate 10, and another part protrudes from the packaging substrate 10. The chip 30 is located on the surface of the packaging substrate 10 and is located on the same side of the packaging substrate 10 as the limiting post 20. The packaging layer 40 covers the chip 30 and the limiting post 20 protruding from the packaging substrate 10.

[0016] A limiting post 20 is provided in the packaging carrier 100. Part of the limiting post 20 is located in the packaging substrate 10, and another part is embedded in the packaging layer 40. This increases the interaction force between the packaging layer 40 and the packaging substrate 10, thereby improving the connection reliability between the packaging layer 40 and the packaging substrate 10. This allows the packaging carrier 100 to resist external impacts and vibrations, thus improving the problem of separation between the packaging substrate 10 and the packaging layer 40. In addition, the limiting post 20 in the packaging carrier 100 helps to disperse the stress generated in the packaging carrier 100 during use, avoiding stress concentration that could cause the packaging layer 40 to crack or the connection between the packaging layer 40 and the packaging substrate 10 to fail. For example, when the material expands and contracts due to temperature changes, the limiting post 20 can share some of the stress.

[0017] The packaging substrate 10 may include an insulating layer 11 and a circuit layer 12, wherein the circuit layer 12 is embedded in the insulating layer 11. The insulating layer 11 may include a dielectric layer 111 and a solder resist layer 112, and the circuit layer 12 may include one or more layers. The circuit layer 12 is located in the gaps between the dielectric layers 111; the solder resist layer 112 is used to cover the circuit layer 12 and the dielectric layers 111. When the circuit layer 12 has multiple layers, the packaging substrate 10 may also include an adhesive layer (not shown), which can be used to bond two adjacent dielectric layers 111.

[0018] The encapsulation substrate 10 can be a flexible board or a rigid board. The material of the dielectric layer 111 can be selected from flexible materials such as polyimide (PI), liquid crystal polymer (LCP), and modified polyimide (MPI), or it can be selected from rigid materials such as polypropylene (PP) and polytetrafluoroethylene (PTFE).

[0019] A first groove 113 is formed on the insulating layer 11, and the surface of the circuit layer 12 is exposed to the first groove 113. The number of first grooves 113 can be one or more; when there are multiple first grooves 113, they are arranged in a ring. (See also...) Figure 2 , Figure 2 This is a top view of the encapsulation carrier 100 provided in an embodiment of this application. The first groove 113 is formed on the solder resist layer 112. There are four first grooves 113, which are spaced apart, and the line connecting the four first grooves 113 is rectangular.

[0020] The limiting post 20 is located in the first groove 113 and protrudes from the insulating layer 11. The number of limiting posts 20 can be one or more, and the number of first grooves 113 is the same as the number of limiting posts 20. When there are multiple limiting posts 20, they are arranged in a ring. Providing multiple limiting posts 20 in the encapsulation carrier 100 can further enhance the interaction force between the encapsulation layer 40 and the encapsulation substrate 10, and further improve the connection reliability between the encapsulation layer 40 and the encapsulation substrate 10; furthermore, the ring arrangement of the multiple limiting posts 20 helps to improve the uniformity of the interaction force.

[0021] Please continue reading. Figure 1 Each of the limiting posts 20 may include a rod portion 21 and a protrusion portion 22. The rod portion 21 is generally cylindrical, one end of the rod portion 21 is embedded and fixed in the first groove 113, and the portion of the rod portion 21 embedded in the first groove 113 is connected to the surface of the circuit layer 12; the other end of the rod portion 21 protrudes from the surface of the insulating layer 11 opposite to the surface of the circuit layer 12. The protruding portion 22 and the rod portion 21 are connected at the ends opposite to the encapsulation substrate 10. The protruding portion 22 is spaced apart from the surface of the insulating layer 11. The cross-sectional dimension of the protruding portion 22 is larger than the cross-sectional dimension of the rod portion 21, that is, the width of the protruding portion 22 is larger than the width of the rod portion 21. The limiting post 20 is approximately mushroom-shaped. On the one hand, this can increase the connection area between the limiting post 20 and the encapsulation layer 40, thereby increasing the interaction force between the limiting post 20 and the encapsulation layer 40. On the other hand, by providing the protruding portion 22 with a larger cross-sectional dimension, the pull-out force between the limiting post 20 and the encapsulation layer 40 is improved, thereby further increasing the interaction force between the limiting post 20 and the encapsulation layer 40.

[0022] The limiting post 20 can be made of metal or metal alloy, such as copper. The limiting post 20 can be formed by electroplating. In this case, the limiting post 20 is equivalent to growing on the surface of the circuit layer 12. The connection force between the limiting post 20 and the circuit layer 12 is strong, which can enhance the interaction force between the limiting post 20 and the packaging substrate 10.

[0023] The chip 30 may include a body 31 and pins 32, with the pins 32 located on the surface of the body 31 facing the packaging substrate 10. A second groove 114 is also formed on the insulating layer 11, and the circuit layer 12 is exposed in the second groove 114. The packaging carrier 100 also includes a conductor 33 located in the second groove 114, and the conductor 33 is connected to the pins 32 to achieve electrical connection between the chip 30 and the packaging substrate 10.

[0024] The packaging carrier 100 may further include a filler adhesive 50, which is located between the body 31 and the packaging substrate 10 and bonds the body 31 and the packaging substrate 10. The filler adhesive 50 also surrounds the pins 32 to improve the connection reliability between the chip 30 and the packaging substrate 10. In this embodiment, the conductor 33 is located in the second groove 114 and protrudes from the packaging substrate 10, and the filler adhesive 50 may also surround the conductor 33 protruding from the packaging substrate 10.

[0025] The encapsulation layer 40 covers the portion of the body 31 and the limiting post 20 that protrudes from the encapsulation substrate 10. The encapsulation layer 40 also covers the filler adhesive 50, thereby connecting the encapsulation substrate 10, the limiting post 20, and the chip 30 into a whole. The encapsulation layer 40 can be made of resin, such as epoxy resin.

[0026] The encapsulation carrier 100 may further include an encapsulation shell 60, which covers the encapsulation layer 40. The end of the encapsulation shell 60 may be connected to the encapsulation substrate 10. The hardness of the encapsulation shell 60 is greater than that of the encapsulation layer 40, which can protect the encapsulation layer 40.

[0027] Please see Figure 3 Forming the limiting post 20 on the packaging substrate 10 may include the following steps: Step S11: Provide the packaging substrate 10, the packaging substrate 10 includes a first groove 113, the circuit layer 12 of the packaging substrate 10 is exposed in the first groove 113, a dry film 70 is covered on the packaging substrate 10, and the dry film 70 is exposed and developed to expose the first groove 113.

[0028] The packaging substrate 10 includes a second recess 114, through which the circuit layer 12 of the packaging substrate 10 is exposed. After the dry film 70 is applied to the packaging substrate 10, the dry film 70 also fills the second recess 114.

[0029] Step S12: Electroplating is performed on the packaging substrate 10 to form the limiting post 20.

[0030] During the electroplating process, the circuit layer 12 exposed to the first groove 113 comes into contact with the electroplating solution, and a plating layer can be formed on the surface of the circuit layer 12. As the electroplating time is increased, the plating layer gradually deposits in the first groove 113 and onto the surface of the dry film 70, thereby forming a mushroom-shaped retaining post 20.

[0031] Step S13: Remove the dry film 70, exposing the surface of the limiting post 20. The length of the rod portion 21 of the limiting post 20 protruding from the packaging substrate 10 is equal to the thickness of the dry film 70.

[0032] Please see Figure 4 , Figure 4 This is a cross-sectional schematic diagram of the packaging carrier 100a provided in some other embodiments of this application. Unlike the previous embodiment, the packaging carrier 100a in this embodiment further includes a lead layer 80a. The lead layer 80a is located on the inner wall of the first groove 113 and connected to the circuit layer 12. A portion of the rod 21 is located within the lead layer 80a, and the lead layer 80a covers the rod 21 located in the first groove 113. The lead layer 80a is made of metal or a metal alloy. The lead layer 80a, disposed in the groove, can, to some extent, increase the connection reliability between the limiting post 20 and the circuit board.

[0033] Please see Figure 5 , Figure 5 Provided for the embodiments of this application Figure 4 Forming the limiting post 20 on the packaging substrate 10 shown may include the following steps: Step S21: Provide the packaging substrate 10, the packaging substrate 10 including a first groove 113, and perform sputtering processing on the packaging substrate 10 to form a sputtering layer 81a, the sputtering layer 81a covering the insulating layer 11 of the packaging substrate 10 and also covering the inner wall of the first groove 113.

[0034] Step S22: Cover the packaging substrate 10 with a dry film 70, expose and develop the dry film 70 to expose the sputtering layer 81a located in the first groove 113.

[0035] Step S23: Using the sputtered layer 81a as an electroplating lead, electroplating is performed on the packaging substrate 10 to form the limiting post 20.

[0036] Step S24: Remove the dry film 70 and the sputtered layer 81a located outside the first groove 113. The remaining sputtered layer 81a forms the lead layer 80a. After the dry film 70 and the sputtered layer 81a are removed, the surface of the limiting post 20 is exposed. The length of the rod portion 21 of the limiting post 20 protruding from the packaging substrate 10 is equal to the thickness of the dry film 70.

[0037] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the above preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application should not depart from the scope of the technical solutions of this application.

Claims

1. A package substrate, characterized by, include: A packaging substrate includes an insulating layer and a circuit layer, wherein the circuit layer is embedded in the insulating layer, and at least one first groove is formed on the insulating layer; At least one limiting post is located in the first groove and protrudes from the insulating layer; A chip is located on the surface of the insulating layer where the limiting post is provided, and the chip is electrically connected to the circuit layer; as well as An encapsulation layer covers the chip and the limiting post.

2. The package board according to claim 1, wherein The limiting post includes a rod and a protrusion. One end of the rod is embedded and fixed in the first groove, and the other end of the rod protrudes from the surface of the insulating layer away from the circuit layer. The protrusion and the end of the rod away from the packaging substrate are connected. The protrusion is spaced apart from the surface of the insulating layer, and the cross-sectional dimension of the protrusion is larger than the cross-sectional dimension of the rod.

3. The package board according to claim 2, wherein The circuit layer is exposed in the first groove, and the rod is connected to the circuit layer.

4. The package board according to any one of claims 1 to 2, wherein The packaging substrate may further include a lead layer, which is located on the inner wall of the first groove and connected to the circuit layer, with a portion of the rod located in the lead layer, and the lead layer covering the rod located in the first groove.

5. The package board according to claim 4, wherein The insulating layer is further provided with a second groove, and the circuit layer is also exposed in the second groove; the packaging substrate also includes a conductor, which is located in the second groove and connected to the chip.

6. The package board according to claim 5, wherein The chip includes a body and pins, the pins being located on the surface of the body facing the packaging substrate, and the pins being connected to the conductor.

7. The package board according to claim 6, wherein The packaging carrier also includes a filler adhesive located between the body and the packaging substrate, which bonds the body and the packaging substrate together, and the filler adhesive also surrounds the pins.

8. The package board according to any one of claims 1 to 3, 5 to 7, wherein The packaging substrate includes a plurality of limiting posts, which are spaced apart and surround the chip.

9. The package board according to any one of claims 1 to 3, 5 to 7, wherein The packaging carrier also includes a packaging shell, which covers the packaging layer, and the end of the packaging shell is connected to the packaging substrate.

10. The package board according to any one of claims 1 to 3, 5 to 7, wherein The packaging substrate is made of copper, and the packaging layer is made of resin.

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