An electric pump control circuit based on multi-stage gear position feedback

Abstract

The utility model discloses a kind of electric pump control circuit based on multistage gear position feedback, including gear phase mapping circuit, dynamic load balancing circuit, collaborative drive circuit and system power supply.Gear phase mapping circuit realizes the accurate mapping of mechanical phase and electrical signal by processing multistage gear position information, dynamic load balancing circuit optimizes transmission efficiency according to the dynamic adjustment power distribution of load variation, collaborative drive circuit ensures the efficient matching of motor output and multistage gear transmission requirement, and system power supply provides stable energy supply for each module.The scheme realizes the accurate synchronous control of multistage gear transmission mechanism by hardware level integration, significantly improves the operating stability, response speed and service life of electric pump.

Description

Technical Field

[0001] This utility model belongs to the field of power electronic control technology, and relates to an electric pump control circuit based on multi-stage gear position feedback. Background Technology

[0002] In traditional electric pump control systems, the control of multi-stage gear transmission mechanisms typically relies on simple motor speed regulation or microprocessor-based software algorithms. These methods have significant limitations.

[0003] First, the lack of a direct hardware-level correlation between the physical meshing state of mechanical gears and the electrical drive signal of the motor leads to low transmission efficiency and slow response. Second, the system cannot sense the precise phase position of multi-stage gears in real time, making true synchronous control difficult. Furthermore, traditional drive circuits lack dynamic load adaptability for the characteristics of multi-stage gear transmissions, making them prone to shocks and vibrations during gear switching and load changes.

[0004] Furthermore, existing back EMF detection methods have limited accuracy and cannot provide accurate phase feedback for complex multi-stage gear systems. These factors collectively limit the performance of electric pumps in precision control applications, thus necessitating an integrated solution that deeply integrates mechanical transmission characteristics with electrical control. Utility Model Content

[0005] To address the problems existing in the background technology, this utility model proposes an electric pump control circuit based on multi-stage gear position feedback.

[0006] To achieve the above objectives, the technical solution adopted by this utility model is as follows: an electric pump control circuit based on multi-stage gear position feedback, comprising: a gear phase mapping circuit, a dynamic load balancing circuit, a cooperative drive circuit, and a system power supply;

[0007] The gear phase mapping circuit is connected to the dynamic load balancing circuit and the cooperative drive circuit, and the dynamic load balancing circuit is connected to the cooperative drive circuit.

[0008] The power supply terminals of the gear phase mapping circuit, the dynamic load balancing circuit, and the cooperative drive circuit are all connected to the positive terminal of the system power supply, while the ground terminals of the gear phase mapping circuit, the dynamic load balancing circuit, and the cooperative drive circuit are all connected to the negative terminal of the system power supply.

[0009] Specifically, the gear phase mapping circuit includes: a multi-channel gear position encoder EN1, a first analog switch array U1, a second analog switch array U2, a third analog switch array U3, a back EMF sampling circuit, a programmable resistor network RP1, a first voltage comparator CP1, a second voltage comparator CP2, a phase-locked loop PLL1, and a reference voltage source.

[0010] The first set of binary output terminals of the multi-channel gear position encoder EN1 is connected to the address input terminal of the first analog switch array U1, the second set of binary output terminals of the multi-channel gear position encoder EN1 is connected to the address input terminal of the second analog switch array U2, and the third set of binary output terminals of the multi-channel gear position encoder EN1 is connected to the address input terminal of the third analog switch array U3.

[0011] The common output terminal of the first analog switch array U1 is connected to the first port of the programmable resistor network RP1, the common output terminal of the second analog switch array U2 is connected to the second port of the programmable resistor network RP1, and the programmable resistor network RP1 is connected to the non-inverting input terminal of the first voltage comparator CP1 and the non-inverting input terminal of the second voltage comparator CP2 respectively.

[0012] The inverting input of the first voltage comparator CP1 is connected to the first reference voltage output of the reference voltage source, the inverting input of the second voltage comparator CP2 is connected to the second reference voltage output of the reference voltage source, the output of the first voltage comparator CP1 is connected to the reference signal input of the phase-locked loop PLL1, and the output of the second voltage comparator CP2 is connected to the dynamic load balancing circuit.

[0013] The common output terminal of the third analog switch array U3 is connected to the feedback input terminal of the phase-locked loop PLL1, the output terminal of the back EMF sampling circuit is connected to multiple input channels of the third analog switch array U3, and the input terminal of the back EMF sampling circuit is connected to the cooperative drive circuit.

[0014] The output of the phase-locked loop (PLL1) is connected to the dynamic load balancing circuit and the collaborative drive circuit.

[0015] Specifically, the dynamic load balancing circuit includes: transconductance amplifier Gm1, integrating capacitor C1, voltage-controlled oscillator VCO1, current mirror source M1, current mirror source M2, current mirror source M3, resistor R1, and proportional control circuit.

[0016] The non-inverting input of transconductance amplifier Gm1 is connected to the output of phase-locked loop PLL1, the inverting input of transconductance amplifier Gm1 is connected to the cooperative drive circuit, the output of transconductance amplifier Gm1 is connected to the first pin of integrating capacitor C1, and the second pin of integrating capacitor C1 is connected to ground.

[0017] The first pin of the integrating capacitor C1 is connected to the control input terminal of the voltage-controlled oscillator VCO1. The output terminal of the voltage-controlled oscillator VCO1 is connected to the gate of the current mirror source M1, the gate of the current mirror source M2, and the gate of the current mirror source M3, respectively. The output terminal of the second voltage comparator CP2 is connected to the proportional control terminal of the current mirror source M2 and the current mirror source M3, respectively, through the proportional control circuit. The source of the current mirror source M1, the source of the current mirror source M2, and the source of the current mirror source M3 are connected to the positive terminal of the system power supply. The drain of the current mirror source M1 is connected to ground through the series resistor R1.

[0018] Specifically, the dynamic load balancing circuit also includes: resistor R2, capacitor C2, and resistor R3;

[0019] The drain of the mirror current source M2 is connected to the cooperative drive circuit through a series resistor R2, and the capacitor C2 is connected in parallel across the resistor R2. The drain of the mirror current source M3 is connected to the cooperative drive circuit through a series resistor R3.

[0020] Specifically, the collaborative drive circuit includes: dead-time control trigger FF1, dead-time resistor R4, dead-time resistor R5, drive resistor R6, drive resistor R7, resistor R8, power MOSFET Q1, power MOSFET Q2, power MOSFET Q3, power MOSFET Q4, motor, and differential current detection amplifier IA1.

[0021] The positive output terminal of the dead-time control flip-flop FF1 is connected to the gate of the power MOSFET Q1 through a series dead-time resistor R4, and the negative output terminal of the dead-time control flip-flop FF1 is connected to the gate of the power MOSFET Q2 through a series dead-time resistor R5.

[0022] The drains of power MOSFETs Q1 and Q2 are connected to the positive terminal of the system power supply. The source of power MOSFET Q1 is connected to the first terminal of the motor and the drain of power MOSFET Q3. The source of power MOSFET Q2 is connected to the second terminal of the motor and the drain of power MOSFET Q4. The second pin of resistor R2 is connected to the gate of power MOSFET Q3 through a series drive resistor R6. The second pin of resistor R3 is connected to the gate of power MOSFET Q4 through a series drive resistor R7. The sources of power MOSFETs Q3 and Q4 are connected to the first pin of resistor R8. The second pin of resistor R8 is connected to ground.

[0023] The positive input terminal of the differential current sense amplifier IA1 is connected to the first pin of resistor R8, the negative input terminal of the differential current sense amplifier IA1 is connected to the second pin of resistor R8, and the output terminal of the differential current sense amplifier IA1 is connected to the inverting input terminal of transconductance amplifier Gm1.

[0024] Specifically, the collaborative drive circuit also includes: a first voltage conversion circuit and a second voltage conversion circuit;

[0025] The set terminal of the dead-time control trigger FF1 is connected to the second pin of resistor R2 in the dynamic load balancing circuit through the first voltage conversion circuit. The reset terminal of the dead-time control trigger FF1 is connected to the second pin of resistor R3 in the dynamic load balancing circuit through the second voltage conversion circuit. The set terminal of the dead-time control trigger FF1 is connected to the drain of the mirror current source M2 through the first voltage conversion circuit. The reset terminal of the dead-time control trigger FF1 is connected to the drain of the mirror current source M3 through the second voltage conversion circuit.

[0026] The clock terminal of the dead-time control trigger FF1 is connected to the output terminal of the phase-locked loop PLL1, and the power supply terminal of the dead-time control trigger FF1 is connected to the positive terminal of the system power supply.

[0027] Specifically, the collaborative drive circuit also includes: Zener diode D1 and Zener diode D2;

[0028] The cathode of Zener diode D1 is connected to the first terminal of the motor, and the anode of Zener diode D1 is connected to ground. The cathode of Zener diode D2 is connected to the second terminal of the motor, and the anode of Zener diode D2 is connected to ground.

[0029] Specifically, the programmable resistor network RP1 includes: precision resistor R9, precision resistor R10, precision resistor R11, and a compensation switch;

[0030] The common output terminal of the first analog switch array U1 is connected to the first pin of resistor R9. The second pin of resistor R9 is connected to the first pin of resistor R10. The second pin of resistor R10 is connected to the first pin of resistor R11. The second pin of resistor R11 is connected to the common output terminal of the second analog switch array U2. The second pin of resistor R9 is connected to the non-inverting input terminal of the first voltage comparator CP1 and the non-inverting input terminal of the second voltage comparator CP2, respectively. The compensation switch is connected in parallel across resistor R10. The control terminal of the compensation switch is connected to the output terminal of the second voltage comparator CP2.

[0031] Compared with existing technologies, this invention has the following advantages: Through the coordinated operation of the gear phase mapping circuit, dynamic load balancing circuit, and collaborative drive circuit, a deep hardware-level coupling between the multi-stage gear transmission mechanism and the motor drive control is achieved. A direct mapping relationship between the mechanical gear meshing position and the electrical control signal is established through pure hardware circuitry, achieving precise synchronization between gear phase and drive timing. The dynamic load balancing mechanism automatically adapts to load changes in the multi-stage gear transmission, significantly improving transmission efficiency and control accuracy. The entire system has a fast response speed and strong anti-interference capability, effectively reducing impact and vibration during gear transmission, and improving the working stability and service life of the electric pump. Attached Figure Description

[0032] Figure 1 This is a circuit block diagram of an electric pump control circuit based on multi-stage gear position feedback according to this utility model;

[0033] Figure 2 This is the connection diagram of the gear phase mapping circuit of this utility model;

[0034] Figure 3 This is the connection diagram of the dynamic load balancing circuit of this utility model;

[0035] Figure 4 This is a connection diagram of the collaborative drive circuit of this utility model;

[0036] Figure 5 This is a circuit connection diagram of the programmable resistor network of this utility model. Detailed Implementation

[0037] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0038] like Figures 1-5 As shown, the technical solution adopted by this utility model is as follows: an electric pump control circuit based on multi-stage gear position feedback, including: a gear phase mapping circuit, a dynamic load balancing circuit, a cooperative drive circuit, and a system power supply.

[0039] The gear phase mapping circuit is connected to the dynamic load balancing circuit and the cooperative drive circuit, and the dynamic load balancing circuit is connected to the cooperative drive circuit.

[0040] The power supply terminals of the gear phase mapping circuit, the dynamic load balancing circuit, and the cooperative drive circuit are all connected to the positive terminal of the system power supply, while the ground terminals of the gear phase mapping circuit, the dynamic load balancing circuit, and the cooperative drive circuit are all connected to the negative terminal of the system power supply.

[0041] Furthermore, the signal output terminal of the gear phase mapping circuit is connected to the controlled terminal of the dynamic load balancing circuit, and the feedback terminal of the dynamic load balancing circuit is connected to the compensation terminal of the gear phase mapping circuit, forming a first closed loop.

[0042] The drive signal output terminal of the dynamic load balancing circuit is connected to the input terminal of the cooperative drive circuit, and the current sampling terminal of the cooperative drive circuit is connected to the current monitoring terminal of the dynamic load balancing circuit, forming a second closed loop.

[0043] This technical solution achieves precise control of the electric pump through cooperation with a multi-stage gear transmission mechanism. The gear phase mapping circuit is specifically designed to handle the phase relationship of the multi-stage gear transmission chain, the dynamic load balancing circuit dynamically adjusts the drive power according to the load characteristics of the multi-stage gears, and the coordinated drive circuit ensures precise matching between the motor output and the gear transmission requirements. The system power supply provides a stable energy supply to the entire control circuit, ensuring coordinated operation between the multi-stage gear transmission and the motor drive.

[0044] Specifically, the gear phase mapping circuit includes: a multi-channel gear position encoder EN1, a first analog switch array U1, a second analog switch array U2, a third analog switch array U3, a back EMF sampling circuit, a programmable resistor network RP1, a first voltage comparator CP1, a second voltage comparator CP2, a phase-locked loop PLL1, and a reference voltage source.

[0045] The first set of binary output terminals of the multi-channel gear position encoder EN1 is connected to the address input terminal of the first analog switch array U1, the second set of binary output terminals of the multi-channel gear position encoder EN1 is connected to the address input terminal of the second analog switch array U2, and the third set of binary output terminals of the multi-channel gear position encoder EN1 is connected to the address input terminal of the third analog switch array U3.

[0046] The common output terminal of the first analog switch array U1 is connected to the first port of the programmable resistor network RP1, and the common output terminal of the second analog switch array U2 is connected to the second port of the programmable resistor network RP1. The programmable resistor network RP1 is connected to the non-inverting input terminal of the first voltage comparator CP1 and the non-inverting input terminal of the second voltage comparator CP2, respectively.

[0047] The inverting input of the first voltage comparator CP1 is connected to the first reference voltage output of the reference voltage source, the inverting input of the second voltage comparator CP2 is connected to the second reference voltage output of the reference voltage source, the output of the first voltage comparator CP1 is connected to the reference signal input of the phase-locked loop PLL1, and the output of the second voltage comparator CP2 is connected to the dynamic load balancing circuit.

[0048] The common output terminal of the third analog switch array U3 is connected to the feedback input terminal of the phase-locked loop PLL1. The output terminal of the back EMF sampling circuit is connected to multiple input channels of the third analog switch array U3. The input terminal of the back EMF sampling circuit is connected to the cooperative drive circuit.

[0049] The output of the phase-locked loop (PLL1) is connected to the dynamic load balancing circuit and the collaborative drive circuit.

[0050] The gear phase mapping circuit handles the complex positional relationships of multi-stage gear transmission mechanisms. The multi-channel gear position encoder EN1 uses the AS5048A high-precision magnetic encoder, which is installed on the three-stage transmission gears to detect the precise meshing position of each gear in real time.

[0051] The first analog switch array U1, the second analog switch array U2, and the third analog switch array U3 employ a CD4051BE eight-channel analog multiplexer to select and process the position signals of the three-stage gears. The back EMF sampling circuit indirectly reflects the load characteristics of the multi-stage gear transmission by monitoring the motor's operating status. The impedance characteristics of the programmable resistor network RP1 are adaptively adjusted according to the transmission ratio of the multi-stage gears. The first voltage comparator CP1 and the second voltage comparator CP2 use LM311D high-speed voltage comparators to perform threshold judgment on the gear position signals. The phase-locked loop PLL1 uses a CD4046B chip to ensure that the electrical control signal remains synchronized with the rotational phase of the mechanical gears. A reference voltage source provides a stable reference signal to ensure the accuracy of multi-stage gear position detection.

[0052] Specifically, the dynamic load balancing circuit includes: transconductance amplifier Gm1, integrating capacitor C1, voltage-controlled oscillator VCO1, current mirror source M1, current mirror source M2, current mirror source M3, resistor R1, and proportional control circuit.

[0053] The non-inverting input of transconductance amplifier Gm1 is connected to the output of phase-locked loop PLL1, the inverting input of transconductance amplifier Gm1 is connected to the cooperative drive circuit, the output of transconductance amplifier Gm1 is connected to the first pin of integrating capacitor C1, and the second pin of integrating capacitor C1 is connected to ground.

[0054] The first pin of the integrating capacitor C1 is connected to the control input terminal of the voltage-controlled oscillator VCO1. The output terminal of the voltage-controlled oscillator VCO1 is connected to the gate of the current mirror source M1, the gate of the current mirror source M2, and the gate of the current mirror source M3, respectively. The output terminal of the second voltage comparator CP2 is connected to the proportional control terminal of the current mirror source M2 and the current mirror source M3, respectively, through the proportional control circuit. The source of the current mirror source M1, the source of the current mirror source M2, and the source of the current mirror source M3 are connected to the positive terminal of the system power supply. The drain of the current mirror source M1 is connected to ground through the series resistor R1.

[0055] A dynamic load balancing circuit is used to optimize the design for the load characteristics of multi-stage gear transmissions. The transconductance amplifier Gm1 uses an LM13700N dual operational transconductance amplifier to convert the gear phase signal into a current control signal. The integrating capacitor C1 uses a 100nF / 50V X7R dielectric ceramic capacitor to smooth speed fluctuations during multi-stage gear transmission. The voltage-controlled oscillator VCO1 generates a drive signal of the corresponding frequency according to the speed requirements of the multi-stage gears. The mirror current sources M1, M2, and M3 use matched 2N7002 MOSFETs to provide precise current distribution for different gear transmission stages. Resistor R1 sets the reference current value to ensure reasonable power distribution in the multi-stage gear transmission mechanism. The proportional control circuit dynamically adjusts the current ratio according to the gear meshing state to adapt to the torque requirements of the multi-stage transmission.

[0056] Specifically, the dynamic load balancing circuit also includes: resistor R2, capacitor C2, and resistor R3.

[0057] The drain of the mirror current source M2 is connected to the cooperative drive circuit through a series resistor R2, and the capacitor C2 is connected in parallel across the resistor R2. The drain of the mirror current source M3 is connected to the cooperative drive circuit through a series resistor R3.

[0058] The drain current of current mirror source M2 flows through resistor R2, generating a first drive control voltage signal across resistor R2. The drain current of current mirror source M3 flows through resistor R3, generating a second drive control voltage signal across resistor R3. Capacitor C2 is connected in parallel across resistor R2 to filter out high-frequency noise.

[0059] The first drive control voltage signal and the second drive control voltage signal are sent to the co-drive circuit. The first drive control voltage signal is used to control the gate of the power MOSFET Q3 and set the set terminal of the flip-flop FF1. The second drive control voltage signal is used to control the gate of the power MOSFET Q4 and set the reset terminal of the flip-flop FF1.

[0060] Resistor R2, capacitor C2, and resistor R3 are used to optimize the drive characteristics of the multi-stage gear transmission mechanism. Resistors R2 and R3 act as degradation resistors in the current output stage, effectively suppressing current surges generated during multi-stage gear switching. Capacitor C2 provides high-frequency noise filtering, filtering out electrical noise generated during gear meshing to ensure the purity and stability of the drive signal under multi-stage gear transmission conditions.

[0061] Specifically, the collaborative drive circuit includes: dead-time control trigger FF1, dead-time resistor R4, dead-time resistor R5, drive resistor R6, drive resistor R7, resistor R8, power MOSFET Q1, power MOSFET Q2, power MOSFET Q3, power MOSFET Q4, motor, and differential current detection amplifier IA1.

[0062] The positive output terminal of the dead-time control flip-flop FF1 is connected to the gate of the power MOSFET Q1 through a series dead-time resistor R4, and the negative output terminal of the dead-time control flip-flop FF1 is connected to the gate of the power MOSFET Q2 through a series dead-time resistor R5.

[0063] The drains of power MOSFETs Q1 and Q2 are connected to the positive terminal of the system power supply. The source of power MOSFET Q1 is connected to the first terminal of the motor and the drain of power MOSFET Q3, respectively. The source of power MOSFET Q2 is connected to the second terminal of the motor and the drain of power MOSFET Q4, respectively. The second pin of resistor R2 is connected to the gate of power MOSFET Q3 through a series drive resistor R6. The second pin of resistor R3 is connected to the gate of power MOSFET Q4 through a series drive resistor R7. The sources of power MOSFETs Q3 and Q4 are connected to the first pin of resistor R8. The second pin of resistor R8 is connected to ground.

[0064] The positive input terminal of the differential current sense amplifier IA1 is connected to the first pin of resistor R8, the negative input terminal of the differential current sense amplifier IA1 is connected to the second pin of resistor R8, and the output terminal of the differential current sense amplifier IA1 is connected to the inverting input terminal of transconductance amplifier Gm1.

[0065] The cooperative drive circuit is used to coordinate the motor drive with the multi-stage gear transmission. The dead-time control trigger FF1 uses a CD4013BE dual D trigger to generate complementary drive signals suitable for the multi-stage gear transmission. Dead-time resistors R4 and R5 limit the charging current of the gates of power MOSFETs Q1 and Q2 to prevent current overshoot during gear switching.

[0066] Drive resistors R6 and R7 provide appropriate drive capability to ensure the power MOSFET's rapid response during multi-stage gear transmission. Resistor R8 monitors the motor current in real time, reflecting the load status of the multi-stage gear transmission.

[0067] Power MOSFETs Q1, Q2, Q3, and Q4, all using the IRF540N designation, provide drive power to the motor to adapt to the multi-stage gear transmission characteristics. The motor drives the water pump through this multi-stage gear transmission mechanism, achieving precise control of flow rate and head. The differential current sensing amplifier IA1, using the INA282AIDR designation, monitors the load changes of the multi-stage gear transmission mechanism in real time.

[0068] Specifically, the collaborative drive circuit also includes: a first voltage conversion circuit and a second voltage conversion circuit;

[0069] The set terminal of the dead-time control trigger FF1 is connected to the second pin of resistor R2 in the dynamic load balancing circuit through the first voltage conversion circuit. The reset terminal of the dead-time control trigger FF1 is connected to the second pin of resistor R3 in the dynamic load balancing circuit through the second voltage conversion circuit. The set terminal of the dead-time control trigger FF1 is connected to the drain of the mirror current source M2 through the first voltage conversion circuit. The reset terminal of the dead-time control trigger FF1 is connected to the drain of the mirror current source M3 through the second voltage conversion circuit.

[0070] The clock terminal of the dead-time control trigger FF1 is connected to the output terminal of the phase-locked loop PLL1, and the power supply terminal of the dead-time control trigger FF1 is connected to the positive terminal of the system power supply.

[0071] The first drive control voltage signal from the dynamic load balancing circuit is level-shaped by the first voltage conversion circuit and then connected to the set terminal of the dead-time control trigger FF1. The second drive control voltage signal is level-shaped by the second voltage conversion circuit and then connected to the reset terminal of the dead-time control trigger FF1.

[0072] The first and second voltage conversion circuits are used to handle the signal conversion requirements of the multi-stage gear transmission mechanism. They convert the output signal of the mirror current source into a level suitable for digital processing, ensuring accurate conversion and reliable transmission between mechanical position signals and electrical control signals during multi-stage gear transmission.

[0073] Specifically, the collaborative drive circuit also includes: Zener diode D1 and Zener diode D2;

[0074] The cathode of Zener diode D1 is connected to the first terminal of the motor, and the anode of Zener diode D1 is connected to ground. The cathode of Zener diode D2 is connected to the second terminal of the motor, and the anode of Zener diode D2 is connected to ground.

[0075] Zener diodes D1 and D2 are selected as 1N4742A 12V / 1W Zener diodes, providing reliable overvoltage protection for multi-stage gear transmission mechanisms. They absorb voltage spikes generated during gear switching and motor commutation, protecting the power devices for safe operation under multi-stage gear transmission conditions.

[0076] Specifically, the programmable resistor network RP1 includes: precision resistor R9, precision resistor R10, precision resistor R11, and a compensation switch.

[0077] The common output terminal of the first analog switch array U1 is connected to the first pin of resistor R9, the second pin of resistor R9 is connected to the first pin of resistor R10, the second pin of resistor R10 is connected to the first pin of resistor R11, and the second pin of resistor R11 is connected to the common output terminal of the second analog switch array U2.

[0078] The second pin of resistor R9 serves as a key output node of the programmable resistor network RP1, connected to the non-inverting input of the first voltage comparator CP1 and the non-inverting input of the second voltage comparator CP2. The voltage value of this node is determined by the output voltages of the first analog switch array U1 and the second analog switch array U2, and is precisely set through a series network composed of R9, R10, and R11.

[0079] A compensation switch is connected in parallel across resistor R10, and its control terminal is connected to the output terminal of the second voltage comparator CP2. When the output state of the second voltage comparator CP2 changes, it controls the opening and closing of this compensation switch, thereby dynamically changing the voltage division ratio of the programmable resistor network RP1 and realizing real-time compensation for phase changes in multi-stage gear transmission.

[0080] The programmable resistor network RP1 is optimized based on the transmission characteristics of multi-stage gears. The voltage divider network composed of precision resistors R9, R10, and R11 adapts to the impedance matching requirements of different gear transmission ratios. The compensation switch dynamically adjusts the network parameters according to the gear meshing state, ensuring the stability and adaptability of the circuit performance during multi-stage gear transmission.

[0081] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An electric pump control circuit based on multi-stage gear position feedback, characterized in that, It includes: gear phase mapping circuit, dynamic load balancing circuit, cooperative drive circuit, and system power supply; The gear phase mapping circuit is connected to the dynamic load balancing circuit and the cooperative drive circuit, and the dynamic load balancing circuit is connected to the cooperative drive circuit. The power supply terminals of the gear phase mapping circuit, the dynamic load balancing circuit, and the cooperative drive circuit are all connected to the positive terminal of the system power supply, while the ground terminals of the gear phase mapping circuit, the dynamic load balancing circuit, and the cooperative drive circuit are all connected to the negative terminal of the system power supply.

2. The electric pump control circuit based on multi-stage gear position feedback according to claim 1, characterized in that, The gear phase mapping circuit includes: a multi-channel gear position encoder EN1, a first analog switch array U1, a second analog switch array U2, a third analog switch array U3, a back EMF sampling circuit, a programmable resistor network RP1, a first voltage comparator CP1, a second voltage comparator CP2, a phase-locked loop PLL1, and a reference voltage source. The first set of binary output terminals of the multi-channel gear position encoder EN1 is connected to the address input terminal of the first analog switch array U1, the second set of binary output terminals of the multi-channel gear position encoder EN1 is connected to the address input terminal of the second analog switch array U2, and the third set of binary output terminals of the multi-channel gear position encoder EN1 is connected to the address input terminal of the third analog switch array U3. The common output terminal of the first analog switch array U1 is connected to the first port of the programmable resistor network RP1, the common output terminal of the second analog switch array U2 is connected to the second port of the programmable resistor network RP1, and the programmable resistor network RP1 is connected to the non-inverting input terminal of the first voltage comparator CP1 and the non-inverting input terminal of the second voltage comparator CP2 respectively. The inverting input of the first voltage comparator CP1 is connected to the first reference voltage output of the reference voltage source, the inverting input of the second voltage comparator CP2 is connected to the second reference voltage output of the reference voltage source, the output of the first voltage comparator CP1 is connected to the reference signal input of the phase-locked loop PLL1, and the output of the second voltage comparator CP2 is connected to the dynamic load balancing circuit. The common output terminal of the third analog switch array U3 is connected to the feedback input terminal of the phase-locked loop PLL1, the output terminal of the back EMF sampling circuit is connected to multiple input channels of the third analog switch array U3, and the input terminal of the back EMF sampling circuit is connected to the cooperative drive circuit. The output of the phase-locked loop (PLL1) is connected to the dynamic load balancing circuit and the collaborative drive circuit.

3. The electric pump control circuit based on multi-stage gear position feedback according to claim 2, characterized in that, The dynamic load balancing circuit includes: transconductance amplifier Gm1, integrating capacitor C1, voltage-controlled oscillator VCO1, current mirror M1, current mirror M2, current mirror M3, resistor R1, and proportional control circuit. The non-inverting input of transconductance amplifier Gm1 is connected to the output of phase-locked loop PLL1, the inverting input of transconductance amplifier Gm1 is connected to the cooperative drive circuit, the output of transconductance amplifier Gm1 is connected to the first pin of integrating capacitor C1, and the second pin of integrating capacitor C1 is connected to ground. The first pin of the integrating capacitor C1 is connected to the control input terminal of the voltage-controlled oscillator VCO1. The output terminal of the voltage-controlled oscillator VCO1 is connected to the gate of the current mirror source M1, the gate of the current mirror source M2, and the gate of the current mirror source M3, respectively. The output terminal of the second voltage comparator CP2 is connected to the proportional control terminal of the current mirror source M2 and the proportional control terminal of the current mirror source M3, respectively, through the proportional control circuit. The source of the current mirror source M1, the source of the current mirror source M2, and the source of the current mirror source M3 are connected to the positive terminal of the system power supply. The drain of the current mirror source M1 is connected to ground through the series resistor R1.

4. The electric pump control circuit based on multi-stage gear position feedback according to claim 3, characterized in that, The dynamic load balancing circuit also includes: resistor R2, capacitor C2, and resistor R3; The drain of the mirror current source M2 is connected to the cooperative drive circuit through a series resistor R2, and the capacitor C2 is connected in parallel across the resistor R2. The drain of the mirror current source M3 is connected to the cooperative drive circuit through a series resistor R3.

5. The electric pump control circuit based on multi-stage gear position feedback according to claim 3, characterized in that, The collaborative drive circuit includes: dead-time control trigger FF1, dead-time resistor R4, dead-time resistor R5, drive resistor R6, drive resistor R7, resistor R8, power MOSFET Q1, power MOSFET Q2, power MOSFET Q3, power MOSFET Q4, motor, and differential current detection amplifier IA1. The positive output terminal of the dead-time control flip-flop FF1 is connected to the gate of the power MOSFET Q1 through a series dead-time resistor R4, and the negative output terminal of the dead-time control flip-flop FF1 is connected to the gate of the power MOSFET Q2 through a series dead-time resistor R5. The drains of power MOSFETs Q1 and Q2 are connected to the positive terminal of the system power supply. The source of power MOSFET Q1 is connected to the first terminal of the motor and the drain of power MOSFET Q3. The source of power MOSFET Q2 is connected to the second terminal of the motor and the drain of power MOSFET Q4. The second pin of resistor R2 is connected to the gate of power MOSFET Q3 through a series drive resistor R6. The second pin of resistor R3 is connected to the gate of power MOSFET Q4 through a series drive resistor R7. The sources of power MOSFETs Q3 and Q4 are connected to the first pin of resistor R8. The second pin of resistor R8 is connected to ground. The positive input terminal of the differential current sense amplifier IA1 is connected to the first pin of resistor R8, the negative input terminal of the differential current sense amplifier IA1 is connected to the second pin of resistor R8, and the output terminal of the differential current sense amplifier IA1 is connected to the inverting input terminal of transconductance amplifier Gm1.

6. The electric pump control circuit based on multi-stage gear position feedback according to claim 5, characterized in that, The collaborative drive circuit also includes: a first voltage conversion circuit and a second voltage conversion circuit; The set terminal of the dead-time control trigger FF1 is connected to the second pin of resistor R2 in the dynamic load balancing circuit through the first voltage conversion circuit. The reset terminal of the dead-time control trigger FF1 is connected to the second pin of resistor R3 in the dynamic load balancing circuit through the second voltage conversion circuit. The set terminal of the dead-time control trigger FF1 is connected to the drain of the mirror current source M2 through the first voltage conversion circuit. The reset terminal of the dead-time control trigger FF1 is connected to the drain of the mirror current source M3 through the second voltage conversion circuit. The clock terminal of the dead-time control trigger FF1 is connected to the output terminal of the phase-locked loop PLL1, and the power supply terminal of the dead-time control trigger FF1 is connected to the positive terminal of the system power supply.

7. The electric pump control circuit based on multi-stage gear position feedback according to claim 5, characterized in that, The collaborative drive circuit also includes: Zener diode D1 and Zener diode D2; The cathode of Zener diode D1 is connected to the first terminal of the motor, and the anode of Zener diode D1 is connected to ground. The cathode of Zener diode D2 is connected to the second terminal of the motor, and the anode of Zener diode D2 is connected to ground.

8. The electric pump control circuit based on multi-stage gear position feedback according to claim 2, characterized in that, The programmable resistor network RP1 includes: precision resistor R9, precision resistor R10, precision resistor R11, and a compensation switch; The common output terminal of the first analog switch array U1 is connected to the first pin of resistor R9. The second pin of resistor R9 is connected to the first pin of resistor R10. The second pin of resistor R10 is connected to the first pin of resistor R11. The second pin of resistor R11 is connected to the common output terminal of the second analog switch array U2. The second pin of resistor R9 is connected to the non-inverting input terminal of the first voltage comparator CP1 and the non-inverting input terminal of the second voltage comparator CP2, respectively. The compensation switch is connected in parallel across resistor R10. The control terminal of the compensation switch is connected to the output terminal of the second voltage comparator CP2.

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