A test system supporting dual HDMI output interface with the same screen and different displays

Abstract

The utility model relates to chip test technical field provides a kind of test system of supporting dual HDMI output interface same screen different display, including core board, TS3DV642 multiplexer, HDMI display screen and control unit;Core board includes dual HDMI output interface, the first channel input end of TS3DV642 multiplexer is connected with the first road HDMI output interface of core board, the second channel input end of TS3DV642 multiplexer is connected with the second road HDMI output interface of core board;HDMI display screen is connected with the output end of TS3DV642 multiplexer;Control unit is connected with the selection control pin of TS3DV642 multiplexer by control signal line, for switching the input channel of TS3DV642 multiplexer.The utility model significantly reduces the number of test equipment under the premise of guaranteeing signal transmission quality, simplifies the complexity of test wiring, and effectively reduces test cost by the same screen time-sharing different display mode, so as to greatly improve the test efficiency of dual HDMI output interface and the convenience of test process.

Description

Technical Field

[0001] This utility model relates to the field of chip testing technology, and in particular to a testing system that supports simultaneous display of two HDMI output interfaces. Background Technology

[0002] In the development and testing of modern electronic devices, the testing and verification of multi-signal output interfaces is a crucial step in ensuring product performance. Especially in the field of high-definition video transmission, HDMI, as the mainstream digital audio and video transmission interface, is widely used in various electronic devices. With technological advancements, many core boards and chip designs integrate dual or multiple HDMI output interfaces to meet the application requirements of multi-screen displays and signal distribution. Traditional dual-HDMI output testing solutions typically require a separate display device for each HDMI interface, which presents significant technical limitations.

[0003] Chinese patent CN118465518A discloses a method for testing dual-channel high-speed operational amplifier chips using independent equipment. This method comprises a test system consisting of an independent power supply, a PC, a high-frequency signal generator, a dual-channel test board, and a high-bandwidth oscilloscope, primarily targeting the electrical parameters of the operational amplifier chip. However, this test system, specifically designed for testing the electrical characteristics of operational amplifiers and employing relay switches to switch between different test circuits, is unsuitable for testing HDMI video signals and fails to address the issues of equipment redundancy and complex wiring in dual-channel HDMI output testing. Utility Model Content

[0004] In view of this, this utility model proposes a test system that supports simultaneous display of dual HDMI output interfaces, in order to solve the problem that the existing test system uses relay switches to switch different test circuits when testing the electrical characteristic parameters of operational amplifiers. This method is not suitable for the display test requirements of HDMI video signals and cannot solve the problems of equipment redundancy and complicated wiring in dual HDMI output testing.

[0005] The technical solution of this utility model is implemented as follows: a test system that supports simultaneous display of dual HDMI output interfaces, the system including a core board, a TS3DV642 multiplexer, an HDMI display screen and a control unit; The core board includes dual HDMI output interfaces. The first channel input of the TS3DV642 multiplexer is connected to the first HDMI output interface of the core board, and the second channel input of the TS3DV642 multiplexer is connected to the second HDMI output interface of the core board. The HDMI display is connected to the output of the TS3DV642 multiplexer. The control unit is connected to the selection control pin of the TS3DV642 multiplexer via a control signal line, and is used to switch the input channels of the TS3DV642 multiplexer.

[0006] Based on the above technical solutions, preferably, the TS3DV642 multiplexer includes two selection control pins SEL1 and SEL2. The control unit outputs different high and low level combinations to the selection control pins SEL1 and SEL2 respectively, thereby controlling the switching of the input channels.

[0007] Based on the above technical solutions, preferably, the switching control of the input channel includes: When the selection control pin SEL1 is high and the selection control pin SEL2 is low, the first channel of the TS3DV642 multiplexer is enabled, and the second channel of the TS3DV642 multiplexer is in a high-impedance state. When both the selection control pin SEL1 and the selection control pin SEL2 are high, the second channel of the TS3DV642 multiplexer is enabled, and the first channel of the TS3DV642 multiplexer is in a high-impedance state.

[0008] Based on the above technical solutions, preferably, the system further includes an enable control unit, which is connected to the enable pin of the TS3DV642 multiplexer via an enable signal line, for controlling the overall enable state of the TS3DV642 multiplexer.

[0009] Based on the above technical solutions, preferably, the first HDMI output interface and the second HDMI output interface of the core board include differential data signal lines, clock signal lines, control signal lines and power signal lines respectively. The differential data signal lines, clock signal lines and control signal lines are connected to the HDMI display screen through the TS3DV642 multiplexer, and the power signal line is connected to the HDMI display screen.

[0010] Based on the above technical solutions, preferably, the control signal line includes an I2C communication line and a consumer electronics control line, used for communication and control functions between HDMI devices.

[0011] Based on the above technical solutions, preferably, the system further includes an impedance matching unit, which includes multiple resistors connected in series on the differential signal lines between the core board and the TS3DV642 multiplexer to ensure impedance matching of signal transmission.

[0012] Based on the above technical solutions, preferably, the system further includes a signal conditioning unit, which includes multiple field-effect transistors (FETs). The multiple FETs are respectively connected to the signal lines between the core board and the TS3DV642 multiplexer for conditioning and buffering HDMI signals.

[0013] Based on the above technical solutions, preferably, the HDMI display screen is connected to the output of the TS3DV642 multiplexer through a standard HDMI Type-A interface. The HDMI Type-A interface includes differential data transmission pins, clock transmission pins, control signal pins, and power supply pins, which are used to transmit RGB video data, pixel clock signals, device communication control signals, and power supply, respectively.

[0014] Based on the above technical solutions, preferably, the system further includes a power management unit, which is used to supply power to the TS3DV642 multiplexer and filter out power ripple through a filter capacitor.

[0015] This utility model provides a testing system that supports simultaneous display of dual HDMI output interfaces on the same screen, which has the following advantages compared to the prior art: By integrating and connecting the core board, TS3DV642 multiplexer, HDMI display, and control unit, dual HDMI output signals can be quickly switched and displayed in a unified manner. This significantly reduces the number of test devices while ensuring signal transmission quality, simplifies the complexity of test wiring, and effectively reduces test costs through time-sharing display on the same screen. As a result, the test efficiency and convenience of the test process for dual HDMI output interfaces are greatly improved. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a test system that supports simultaneous display of dual HDMI output interfaces according to this utility model; Figure 2 This is the first circuit wiring diagram of a test system that supports simultaneous display of dual HDMI output interfaces according to this utility model. Figure 3 This is the second circuit wiring diagram of a test system that supports simultaneous display of dual HDMI output interfaces according to this utility model; Figure 4 This is the wiring diagram of the third circuit of a test system that supports simultaneous display of dual HDMI output interfaces according to this utility model. Detailed Implementation

[0018] The technical solutions of this utility model will be clearly and completely described below with reference to the embodiments of this utility model. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this utility model.

[0019] Please see Figure 1 This utility model provides a test system that supports simultaneous display of dual HDMI output interfaces. The system includes a core board, a TS3DV642 multiplexer, an HDMI display screen, and a control unit. The core board includes dual HDMI output interfaces. The first channel input of the TS3DV642 multiplexer is connected to the first HDMI output interface of the core board, and the second channel input of the TS3DV642 multiplexer is connected to the second HDMI output interface of the core board. The HDMI display is connected to the output of the TS3DV642 multiplexer. The control unit is connected to the selection control pin of the TS3DV642 multiplexer via a control signal line, and is used to switch the input channels of the TS3DV642 multiplexer.

[0020] Specifically, this embodiment integrates and connects the core board, TS3DV642 multiplexer, HDMI display screen, and control unit to quickly switch and display dual HDMI output signals in a unified manner. While ensuring signal transmission quality, it significantly reduces the number of test devices, simplifies the complexity of test wiring, and effectively reduces test costs through time-sharing display on the same screen. This greatly improves the test efficiency and convenience of the test process for dual HDMI output interfaces.

[0021] like Figure 2As shown, the TS3DV642 multiplexer is a 12-channel 1:2 or 2:1 bidirectional multiplexer, including two selection control pins SEL1 and SEL2. The control unit outputs different high and low level combinations to the selection control pins SEL1 and SEL2 respectively, thereby controlling the switching of the input channels.

[0022] The switching control of the input channel includes: When the selection control pin SEL1 is high and the selection control pin SEL2 is low, the first channel of the TS3DV642 multiplexer is enabled, and the second channel of the TS3DV642 multiplexer is in a high-impedance state. When both the selection control pin SEL1 and the selection control pin SEL2 are high, the second channel of the TS3DV642 multiplexer is enabled, and the first channel of the TS3DV642 multiplexer is in a high-impedance state.

[0023] Specifically, this embodiment uses a 12-channel bidirectional multiplexer TS3DV642 and dual-pin control logic to achieve precise switching control of dual HDMI signals, ensuring that only one signal is active and the other is in a high-impedance state at any given time, thereby avoiding signal conflicts and interference and ensuring the stability of the switching process.

[0024] like Figure 2 As shown, the system also includes an enable control unit, which is connected to the enable pin of the TS3DV642 multiplexer via the TS3DV_EN signal line, and is used to control the overall enable state of the TS3DV642 multiplexer.

[0025] Specifically, this embodiment achieves unified management and control of the entire TS3DV642 multiplexer's operating state by setting an independent enable control unit. It can quickly shut down the signal path in the case of system standby or abnormality, effectively reducing system power consumption and providing comprehensive protection functions.

[0026] like Figure 2 and Figure 3As shown, the first HDMI output interface and the second HDMI output interface of the core board respectively include differential data signal lines, clock signal lines, control signal lines and power signal lines. The differential data signal lines, clock signal lines and control signal lines are connected to the HDMI display screen through the TS3DV642 multiplexer. The power signal line is connected to the HDMI display screen. The differential data signal lines include HDMI0_TX0P_PORT, HDMI0_TX0N_PORT, HDMI0_TX1P_PORT, HDMI0_TX1N_PORT, HDMI0_TX2P_PORT, HDMI0_TX2N_PORT, HDMI0_TX3P_PORT and HDMI0_TX3N_PORT.

[0027] like Figure 2 and Figure 3 As shown, the control signal lines include I2C communication lines HDMI_TX_SCL_PORT and HDMI_TX_SDA_PORT, as well as consumer electronics control line HDMI_TX_CEC_PORT, used for communication and control functions between HDMI devices.

[0028] Specifically, this embodiment achieves reasonable allocation and efficient transmission of HDMI signals by clearly distinguishing the transmission paths of differential data signals, clock signals, control signals, and power signals. Key signals are switched using a TS3DV642 multiplexer, while power signals are directly connected, ensuring both switching functionality and continuous power supply. By integrating I2C communication lines and CEC control lines, standardized communication protocol support between HDMI devices is achieved, ensuring that display devices can correctly identify and configure signal source parameters, thus improving system compatibility and display consistency.

[0029] like Figure 4 As shown, the system also includes an impedance matching unit, which includes multiple 499Ω / 1% precision resistors connected in series on the differential signal lines between the core board and the TS3DV642 multiplexer to ensure impedance matching for signal transmission.

[0030] Specifically, this embodiment effectively eliminates reflections and distortions during signal transmission by connecting a precision impedance matching resistor in series on the differential signal line, ensuring the integrity and transmission quality of the high-frequency HDMI signal and improving the display quality.

[0031] like Figure 4As shown, the system also includes a signal conditioning unit, which includes multiple field-effect transistors (FETs). The FETs are connected to the signal lines between the core board and the TS3DV642 multiplexer, and are used to condition and buffer the HDMI signal.

[0032] Specifically, this embodiment achieves effective buffering and drive enhancement of HDMI signals by configuring a field-effect transistor signal conditioning unit, thereby improving the signal driving capability and anti-interference performance and ensuring signal quality during long-distance transmission and multi-load connections.

[0033] like Figure 3 As shown, the HDMI display is connected to the output of the TS3DV642 multiplexer via a standard HDMI Type-A interface. The HDMI Type-A interface includes differential data transmission pins, clock transmission pins, control signal pins, and power supply pins, which are used to transmit RGB video data, pixel clock signals, device communication control signals, and power supply, respectively.

[0034] Specifically, this embodiment adopts a standard HDMI Type-A interface design, which ensures broad compatibility with various display devices, realizes unified transmission of RGB video data, clock signals, control signals and power, and simplifies interface design.

[0035] like Figure 2 As shown, the system also includes a power management unit, which provides VDD_HDMI_SWITCH power to the TS3DV642 multiplexer and filters out power ripple through a filter capacitor to ensure the stable operation of the multiplexer.

[0036] Specifically, this embodiment achieves stable power supply and effective suppression of power ripple for the TS3DV642 multiplexer by configuring a power management unit and a filter capacitor, ensuring the electrical performance stability of the system under various operating conditions.

[0037] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A testing system supporting simultaneous display of dual HDMI output interfaces, characterized in that, The system includes a core board, a TS3DV642 multiplexer, an HDMI display, and a control unit; The core board includes dual HDMI output interfaces. The first channel input of the TS3DV642 multiplexer is connected to the first HDMI output interface of the core board, and the second channel input of the TS3DV642 multiplexer is connected to the second HDMI output interface of the core board. The HDMI display is connected to the output of the TS3DV642 multiplexer. The control unit is connected to the selection control pin of the TS3DV642 multiplexer via a control signal line, and is used to switch the input channels of the TS3DV642 multiplexer.

2. The test system supporting simultaneous display of dual HDMI output interfaces as described in claim 1, characterized in that, The TS3DV642 multiplexer includes two selection control pins, SEL1 and SEL2. The control unit outputs different high and low level combinations to the selection control pins SEL1 and SEL2 respectively, thereby controlling the switching of the input channels.

3. The test system supporting simultaneous display of dual HDMI output interfaces as described in claim 2, characterized in that, The switching control of the input channel includes: When the selection control pin SEL1 is high and the selection control pin SEL2 is low, the first channel of the TS3DV642 multiplexer is enabled, and the second channel of the TS3DV642 multiplexer is in a high-impedance state. When both the selection control pin SEL1 and the selection control pin SEL2 are high, the second channel of the TS3DV642 multiplexer is enabled, and the first channel of the TS3DV642 multiplexer is in a high-impedance state.

4. The test system supporting simultaneous display of dual HDMI output interfaces as described in claim 1, characterized in that, The system also includes an enable control unit, which is connected to the enable pin of the TS3DV642 multiplexer via an enable signal line, and is used to control the overall enable state of the TS3DV642 multiplexer.

5. A test system supporting simultaneous display of dual HDMI output interfaces as described in claim 1, characterized in that, The first HDMI output interface and the second HDMI output interface of the core board include differential data signal lines, clock signal lines, control signal lines and power signal lines, respectively. The differential data signal lines, clock signal lines and control signal lines are connected to the HDMI display screen through the TS3DV642 multiplexer, and the power signal line is connected to the HDMI display screen.

6. A test system supporting simultaneous display of dual HDMI output interfaces as described in claim 5, characterized in that, The control signal lines include I2C communication lines and consumer electronics control lines, used for communication and control functions between HDMI devices.

7. A test system supporting simultaneous display of dual HDMI output interfaces as described in claim 1, characterized in that, The system also includes an impedance matching unit, which includes multiple resistors connected in series on the differential signal lines between the core board and the TS3DV642 multiplexer to ensure impedance matching for signal transmission.

8. A test system supporting simultaneous display of dual HDMI output interfaces as described in claim 1, characterized in that, The system also includes a signal conditioning unit, which includes multiple field-effect transistors (FETs). The FETs are connected to the signal lines between the core board and the TS3DV642 multiplexer, and are used to condition and buffer the HDMI signal.

9. A test system supporting simultaneous display of dual HDMI output interfaces as described in claim 1, characterized in that, The HDMI display is connected to the output of the TS3DV642 multiplexer via a standard HDMI Type-A interface. The HDMI Type-A interface includes differential data transmission pins, clock transmission pins, control signal pins, and power supply pins, which are used to transmit RGB video data, pixel clock signals, device communication control signals, and power supply, respectively.

10. A test system supporting simultaneous display of dual HDMI output interfaces as described in claim 1, characterized in that, The system also includes a power management unit, which supplies power to the TS3DV642 multiplexer and filters out power ripple through a filter capacitor.

Images