Test circuit and test module for parameter verification of half-bridge driving chip

Abstract

The utility model relates to half bridge drive chip test field especially, it relates to a kind of test circuit and test module for half bridge drive chip parameter verification.Test circuit: test chip interface is electrically connected with first switch, second switch, main control unit, third switch, fourth switch respectively;First switch and the high side output end electrically connected to main control unit of test chip interface;Second switch and the low side output end electrically connected to main control unit of test chip interface;Third switch and the high side output end electrically connected to main control unit of test chip interface;Fourth switch and the low side output end electrically connected to main control unit of test chip interface;Main control unit and key unit, display unit electrically connected, to this realizes a kind of convenient and fast and applicable to the performance parameter verification test technical scheme of half bridge drive chip.

Description

Technical Field

[0001] This utility model relates to the field of half-bridge driver chip testing, and in particular to a test circuit and test module for verifying the parameters of a half-bridge driver chip. Background Technology

[0002] A half-bridge driver chip is an integrated circuit chip used to enhance the gate control signal of a controller. It achieves power conversion by controlling the conduction and cutoff of power semiconductor devices. Its typical applications include motor drives, inverters, and switching power supplies.

[0003] Testing half-bridge driver chips is a crucial step in product development and mass production. However, professional half-bridge driver chip testing equipment is expensive. Currently, apart from half-bridge driver chip manufacturers, most users lack professional testing equipment and a convenient and quick way to verify the performance parameters of half-bridge driver chips. This causes significant inconvenience for users in confirming component parameters during product development and in incoming material inspection during mass production.

[0004] Therefore, there is a need for a convenient and quick performance parameter verification and testing technology solution suitable for half-bridge driver chips. Utility Model Content

[0005] To solve the above-mentioned technical problems, this utility model provides a test circuit and test module for verifying the parameters of a half-bridge driver chip.

[0006] This utility model provides a test circuit for verifying the parameters of a half-bridge driver chip, including a test chip interface, a first switch, a second switch, a third switch, a fourth switch, a first resistor, a second resistor, a third resistor, a fourth resistor, a main control unit, a display unit, and a button unit;

[0007] The test chip interface is used to connect to the half-bridge driver chip under test. Its power supply voltage terminal is electrically connected to its absolute voltage terminal, the first terminal of the first switch, and the first terminal of the second switch, and is used to connect to the first working voltage. Its high-side input terminal and low-side input terminal are electrically connected to the PWM output terminal group of the main control unit. Its ground terminal is electrically grounded. Its high-side output terminal is electrically connected to the first terminal of the first resistor and the first terminal of the second resistor, respectively. Its offset voltage terminal is electrically connected to the first terminal of the third switch and the first terminal of the fourth switch, respectively, and grounded. Its low-side output terminal is electrically connected to the first terminal of the third resistor and the first terminal of the fourth resistor, respectively.

[0008] The second terminal of the first switch is electrically connected to the second terminal of the first resistor, and is electrically connected to the upper bridge current-pull signal terminal group of the main control unit via the high-side output terminal;

[0009] The second terminal of the second switch is electrically connected to the second terminal of the third resistor, and is electrically connected to the low-side output terminal to the lower bridge pull-up current signal terminal group of the main control unit;

[0010] The second terminal of the third switch is electrically connected to the second terminal of the second resistor, and is electrically connected to the upper bridge sink current signal terminal group of the main control unit via the high-side output terminal.

[0011] The second terminal of the fourth switch is electrically connected to the second terminal of the fourth resistor, and is electrically connected to the lower bridge sink current signal terminal group of the main control unit via the low-side output terminal.

[0012] The first signal receiving end of the main control unit is electrically connected to the output end of the button unit, and its communication end is electrically connected to the communication end of the display unit.

[0013] In one possible implementation, a switching unit is also included;

[0014] The output terminal of the switching unit is used to provide the first operating voltage, its control terminal is electrically connected to the control terminal of the main control unit, and its input terminal is used to connect the initial operating voltage.

[0015] In one possible implementation, the switching unit includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first NPN transistor, and a first PMOS transistor;

[0016] The first end of the fifth resistor serves as the control end of the switching unit, and its second end is electrically connected to the first end of the sixth resistor and the base of the first NPN transistor.

[0017] The second terminal of the sixth resistor is electrically connected to the emitter of the NPN transistor and grounded;

[0018] The first end of the seventh resistor is electrically connected to the collector of the NPN transistor, and its second end is electrically connected to the first end of the eighth resistor and the gate of the first PMOS transistor.

[0019] The second end of the eighth resistor is electrically connected to the source of the PMOS transistor as the input terminal of the switching unit.

[0020] The drain of the PMOS transistor serves as the output terminal of the switching unit.

[0021] In one possible implementation, the button unit includes a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, and a sixteenth resistor;

[0022] The first end of the fifth switch is electrically connected to the first end of the sixth switch, the first end of the seventh switch, and the first end of the eighth switch and grounded, respectively; its second end is electrically connected to the first end of the ninth resistor and the first end of the tenth resistor, respectively.

[0023] The second terminal of the sixth switch is electrically connected to the first terminal of the eleventh resistor and the first terminal of the twelfth resistor, respectively.

[0024] The second terminal of the seventh switch is electrically connected to the first terminal of the thirteenth resistor and the first terminal of the fourteenth resistor, respectively.

[0025] The second terminal of the eighth switch is electrically connected to the first terminal of the fifteenth resistor and the first terminal of the sixteenth resistor, respectively.

[0026] The second end of the ninth resistor, the second end of the eleventh resistor, the second end of the thirteenth resistor, and the second end of the fifteenth resistor are combined to serve as the output terminal of the button unit;

[0027] The second end of the tenth resistor is electrically connected to the second ends of the twelfth resistor, the fourteenth resistor, and the sixteenth resistor, respectively, and is used to connect to the second operating voltage.

[0028] In one possible implementation, the button unit further includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor;

[0029] The first terminal of the first capacitor, the first terminal of the second capacitor, the first terminal of the third capacitor, and the first terminal of the fourth capacitor are respectively electrically connected to the second terminal of the ninth resistor, the second terminal of the eleventh resistor, the second terminal of the thirteenth resistor, and the second terminal of the fifteenth resistor;

[0030] The second terminal of the first capacitor is electrically connected to the second terminal of the second capacitor, the second terminal of the third capacitor, and the second terminal of the fourth capacitor, and is grounded.

[0031] In one possible implementation, a power supply unit is also included;

[0032] The input terminal of the power supply unit is used to connect to an external power source, its first voltage terminal is used to provide the initial operating voltage, and its second voltage terminal is used to provide the second operating voltage.

[0033] In one possible implementation, the power supply unit is built based on a power chip and a voltage regulator.

[0034] In one possible implementation, a zero-resistance interface is provided between the lines containing the high-side input and the low-side input of the test chip interface.

[0035] In one possible implementation, a first zero-resistance is connected in series on the grounding line where the first terminal of the third switch is located;

[0036] A first energy storage capacitor bank is connected in parallel across the first zero resistance;

[0037] A second zero-resistance is connected in series on the grounding line where the first terminal of the fourth switch is located;

[0038] A second energy storage capacitor bank is connected in parallel across the second zero resistance.

[0039] This utility model also provides a test module for verifying the parameters of a half-bridge driver chip, including a PCB board and the test circuit described above.

[0040] The test circuit is mounted on the PCB board.

[0041] The technical solution provided by this utility model has at least the following beneficial effects:

[0042] By configuring the main control unit, button unit, first switch, second switch, third switch, and fourth switch, the main control unit can adjust the PWM signal used to drive the half-bridge driver chip under test, and the button unit, first switch, second switch, third switch, and fourth switch can be used to manually adjust the test mode of the half-bridge driver chip under test, reducing labor and time costs and facilitating testing. Simultaneously, by setting up a display unit, relevant test information can be displayed in a timely manner, allowing for more intuitive observation and speed adjustment. Attached Figure Description

[0043] Figure 1 A schematic diagram of a first test circuit for verifying the parameters of a half-bridge driver chip provided in an embodiment of this utility model;

[0044] Figure 2 A schematic diagram of a second test circuit for verifying the parameters of a half-bridge driver chip provided in an embodiment of this utility model;

[0045] Figure 3 The circuit diagram of the switching unit provided in the embodiment of this utility model;

[0046] Figure 4 A circuit diagram of the button unit provided in an embodiment of this utility model;

[0047] Figure 5 A schematic diagram of a partial test circuit including a power supply unit provided for an embodiment of this utility model;

[0048] Figure 6This is a partial circuit diagram of a test circuit for verifying the parameters of a half-bridge driver chip, provided as an embodiment of the present invention. Detailed Implementation

[0049] To enhance understanding of this utility model, it will be described in further detail below with reference to the accompanying drawings and embodiments. These embodiments are only used to explain this utility model and do not limit the scope of protection of this utility model.

[0050] Please refer to Figures 1 to 6 The present invention provides a test circuit for verifying the parameters of a half-bridge driver chip, including a test chip interface JP0, a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a main control unit, a display unit, and a button unit.

[0051] The test chip interface JP0 is used to connect to the half-bridge driver chip U0 under test. Its power supply voltage terminal VCC is electrically connected to its absolute voltage terminal VB, the first terminal of the first switch SW1, and the first terminal of the second switch SW2, and is used to connect to the first working voltage VCC1. Its high-side input terminal HIN and low-side input terminal LIN are electrically connected to the PWM output terminal group of the main control unit. Its ground terminal COM is electrically grounded. Its high-side output terminal HO is electrically connected to the first terminal of the first resistor R1 and the first terminal of the second resistor R2, respectively. Its offset voltage terminal VS is electrically connected to the first terminal of the third switch SW3 and the first terminal of the fourth switch SW4, respectively, and grounded. Its low-side output terminal LO is electrically connected to the first terminal of the third resistor R3 and the first terminal of the fourth resistor R4, respectively.

[0052] The second terminal of the first switch SW1 is electrically connected to the second terminal of the first resistor R1, and is electrically connected to the upper bridge current pulling signal terminal group of the main control unit via the high-side output terminal HO.

[0053] The second terminal of the second switch SW2 is electrically connected to the second terminal of the third resistor R3, and is electrically connected to the low-side output terminal LO of the main control unit's lower bridge pull-up current signal terminal group.

[0054] The second terminal of the third switch SW3 is electrically connected to the second terminal of the second resistor R2, and is electrically connected to the upper bridge sink current signal terminal group of the main control unit via the high-side output terminal HO.

[0055] The second terminal of the fourth switch SW4 is electrically connected to the second terminal of the fourth resistor R4, and is electrically connected to the lower bridge sink current signal terminal group of the main control unit via the low-side output terminal LO.

[0056] The first signal receiving end of the main control unit is electrically connected to the output end of the button unit, and its communication end is electrically connected to the communication end of the display unit.

[0057] In this embodiment, the test chip interface JP0 can be a conventional chip interface used to connect to the test chip interface JP0. Figure 6This is a partial circuit schematic diagram showing the connection of the half-bridge driver chip U0 under test to the test chip interface JP0. The half-bridge driver chip U0 is a conventional half-bridge driver chip. The first switch SW1, second switch SW2, third switch SW3, and fourth switch SW4 can be conventional self-locking switches. The first resistor R1, second resistor R2, third resistor R3, and fourth resistor R4 can be conventional resistors, such as 3.3Ω surface-mount resistors. R1 is the upper bridge current sourcing sampling resistor. R2 is the upper bridge current sinking sampling resistor. R3 is the lower bridge current sourcing sampling resistor. R4 is the lower bridge current sinking sampling resistor. The main control unit can be implemented based on a conventional microcontroller capable of outputting PWM signals. The display unit can be implemented based on a conventional OLED screen. The button unit can be implemented based on multiple self-locking switches, providing high or low levels to the main control unit for adjusting the test mode and confirmation mode. The first operating voltage VCC1 can be +15V. The PWM output terminal group of the main control unit can consist of two PWM signal output pins (AT, BT). The main control unit and the display unit can establish a communication connection via an I2C bus. The main control unit can send the acquired test data to the display unit. In specific implementation, a test point can be reserved on the line where the high-side output terminal HO is located as the first test point, denoted as HO; a test point can be reserved on the line where the low-side output terminal LO is located as the second test point, denoted as LO; a test point can be reserved on the connection line between the second terminal of the first switch SW1 and the second terminal of the first resistor R1 as the third test point, denoted as HO_L; a test point can be reserved on the connection line between the second terminal of the second switch SW2 and the second terminal of the third resistor R3 as the fourth test point, denoted as LO_L; a test point can be reserved on the connection line between the second terminal of the third switch SW3 and the second terminal of the second resistor R2 as the fifth test point, denoted as HO_H; and a test point can be reserved on the connection line between the second terminal of the fourth switch SW4 and the second terminal of the fourth resistor R4 as the sixth test point, denoted as LO_H. Each of the first, second, third, fourth, fifth, and sixth test points can have a pin soldered to facilitate waveform testing at the corresponding test points using an oscilloscope. The upper bridge current-source signal group of the main control unit consists of two data pins, connected to the lines containing HO_L and HO respectively. The lower bridge current-source signal group of the main control unit consists of two data pins, connected to the lines containing LO_L and LO respectively. The upper bridge current-sinking signal group of the main control unit consists of two data pins, connected to the lines containing HO_H and HO respectively. The lower bridge current-sinking signal group of the main control unit consists of two data pins, connected to the lines containing LO_H and LO respectively. In other words, the line containing HO is simultaneously connected to two data pins of the main control unit, and the line containing LO is simultaneously connected to two data pins of the main control unit.

[0058] In one specific implementation, the required high / low levels of the high-side input HIN and low-side input LIN of the test chip interface JP0 are determined by the specific type of the half-bridge driver chip U0 under test. For example, if the half-bridge driver chip U0 under test is a high-high driver chip (i.e., both the high-side input HIN and the low-side input LIN require a high-level drive), then AT and BT need to output a high level. If the half-bridge driver chip U0 under test is a high-low driver chip (i.e., the high-side input HIN requires a high-level drive, and the low-side input LIN requires a low-level drive), then AT needs to output a high level, and BT needs to output a low level.

[0059] Assuming the half-bridge driver chip U0 under test is a high-low drive chip, under normal circumstances, the AT output of the main control unit is high, and the BT output is low. During testing, the microcontroller in the main control unit can control the on / off state of the half-bridge driver chip U0 by controlling the level of the AT output. When AT is turned on once (i.e., similar to a high-level pulse signal, such as a high-level pulse signal within a 10-second cycle), SW1 is opened and SW3 is closed, allowing the on / off time of the half-bridge driver chip U0 under test to be tested. During the bridge current sourcing and sinking tests: When AT outputs a 10% PWM signal (assuming a period of 10s and a high-level PWM signal percentage of 10%), SW1 is closed and SW3 is open. The bridge sourcing current of the half-bridge driver chip U0 under test is tested. HO_L and HO work together with the internal amplifier of the microcontroller in the main control unit to read the sourcing current magnitude. When AT outputs a 90% PWM signal (assuming a period of 10s and a high-level PWM signal percentage of 90%), SW1 is open and SW3 is closed. The bridge sinking current of the half-bridge driver chip U0 under test is tested. HO and HO_H work together with the internal amplifier of the microcontroller in the main control unit to read the sinking current magnitude. The sourcing and sinking current magnitudes can be displayed on the display unit.

[0060] The lower bridge test is basically the same as the upper bridge test. Assuming the half-bridge driver chip U0 under test is a low-high driver chip, under normal circumstances, the AT output of the main control unit is low, and the BT output is high. During testing, the microcontroller in the main control unit can control the opening and closing of the lower bridge of the half-bridge driver chip U0 under test by controlling the level of the BT output. When BT is turned on once (i.e., similar to a high-level pulse signal, such as a high-level pulse signal within a 10-second cycle), opening SW2 and closing SW4 can test the lower bridge turn-on and turn-off times of the half-bridge driver chip U0 under test. During the lower bridge current sourcing and sinking tests: When BT outputs a 10% PWM signal (assuming a period of 10s and a high-level PWM signal percentage of 10%), SW2 is closed and SW4 is open. The lower bridge sourcing current of the half-bridge driver chip U0 under test is tested. LO_L and LO work together with the internal amplifier of the microcontroller in the main control unit to read the sourcing current magnitude. When BT outputs a 90% PWM signal (assuming a period of 10s and a high-level PWM signal percentage of 90%), SW2 is open and SW4 is closed. The lower bridge sinking current of the half-bridge driver chip U0 under test is tested. LO and LO_H work together with the internal amplifier of the microcontroller in the main control unit to read the sinking current magnitude. The sourcing and sinking current readings can be displayed on the display unit.

[0061] This invention provides a test circuit for verifying the parameters of a half-bridge driver chip. This test circuit can select switch test and pull-in / sink test according to the type of driver chip, adjust the drive mode according to the test items of the driver chip, and add the function of displaying pull-in current and sink current readings, which facilitates user-end test verification.

[0062] In one possible implementation, a switching unit is also included;

[0063] The output terminal of the switching unit is used to provide the first operating voltage VCC1, its control terminal is electrically connected to the control terminal A of the main control unit, and its input terminal is used to connect the initial operating voltage VCC0.

[0064] In this embodiment, the control terminal of the switching unit controls the conduction and cutoff between its input and output terminals based on the high or low level output by the control terminal A of the main control unit. The output level of the control terminal A of the main control unit is triggered by the button unit. In specific implementation, the initial operating voltage VCC0 can be 15V. The initial output of the control terminal A of the main control unit is low, cutting off the input and output terminals of the switching unit, preventing the output terminal of the switching unit from outputting the first operating voltage VCC1, and avoiding damage to the half-bridge driver chip U0 under test upon power-up. After the half-bridge driver chip U0 under test is inserted into the test chip interface JP0, and the microcontroller in the main control unit completes its self-test, the control terminal A of the main control unit can be triggered to output a high level via the button unit, connecting the input and output terminals of the switching unit, and the initial operating voltage VCC0 of 15V outputs as the first operating voltage VCC1 of +15V.

[0065] In one possible implementation, the switching unit includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first NPN transistor Q1, and a first PMOS transistor M1.

[0066] The first end of the fifth resistor R5 serves as the control end of the switching unit, and its second end is electrically connected to the first end of the sixth resistor R6 and the base of the first NPN transistor Q1.

[0067] The second end of the sixth resistor R6 is electrically connected to the emitter of the NPN transistor Q1 and grounded;

[0068] The first end of the seventh resistor R7 is electrically connected to the collector of the NPN transistor Q1, and its second end is electrically connected to the first end of the eighth resistor R8 and the gate of the first PMOS transistor M1.

[0069] The second terminal of the eighth resistor R8 is electrically connected to the source of the PMOS transistor M1 as the input terminal of the switching unit.

[0070] The drain of the PMOS transistor M1 serves as the output terminal of the switching unit.

[0071] In this embodiment, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 are all conventional resistors. The first NPN transistor Q1 is a conventional NPN transistor. The first PMOS transistor M1 is a conventional P-type MOS transistor.

[0072] In one possible implementation, the button unit includes a fifth switch SW5, a sixth switch SW6, a seventh switch SW7, an eighth switch SW8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, and a sixteenth resistor R16.

[0073] The first end of the fifth switch SW5 is electrically connected to and grounded to the first end of the sixth switch SW6, the first end of the seventh switch SW7, and the first end of the eighth switch SW8, respectively, and its second end is electrically connected to the first end of the ninth resistor R9 and the first end of the tenth resistor R10, respectively.

[0074] The second terminal of the sixth switch SW6 is electrically connected to the first terminal of the eleventh resistor R11 and the first terminal of the twelfth resistor R12, respectively.

[0075] The second terminal of the seventh switch SW7 is electrically connected to the first terminal of the thirteenth resistor R13 and the first terminal of the fourteenth resistor R14, respectively.

[0076] The second terminal of the eighth switch SW8 is electrically connected to the first terminal of the fifteenth resistor R15 and the first terminal of the sixteenth resistor R16, respectively.

[0077] The second end of the ninth resistor R9, the second end of the eleventh resistor R11, the second end of the thirteenth resistor R13, and the second end of the fifteenth resistor R15 are combined to serve as the output terminal of the button unit;

[0078] The second terminal of the tenth resistor R10 is electrically connected to the second terminals of the twelfth resistor R12, the fourteenth resistor R14, and the sixteenth resistor R6, respectively, and is used to connect to the second operating voltage VCC2.

[0079] In this embodiment, the fifth switch SW5, the sixth switch SW6, the seventh switch SW7, and the eighth switch SW8 can be conventional self-locking switches. The ninth resistor R9, the tenth resistor R10, the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15, and the sixteenth resistor R16 are all conventional resistors. The output terminal of the button unit consists of four ports: KEY_1, KEY_2, KEY_3, and KEY_4. The first signal receiving terminal of the main control unit consists of four data pins connected to KEY_1, KEY_2, KEY_3, and KEY_4 respectively. The second operating voltage VCC2 can be +5V. In specific implementation, the output level of the PWM output terminal group of the main control unit can be controlled based on the switching combination state of the fifth switch SW5, the sixth switch SW6, and the seventh switch SW7, and the output level of the control terminal A of the main control unit can be controlled based on the switching state of the eighth switch SW8.

[0080] In one possible implementation, the button unit further includes a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4;

[0081] The first terminal of the first capacitor C1, the first terminal of the second capacitor C2, the first terminal of the third capacitor C3, and the first terminal of the fourth capacitor C4 are respectively electrically connected to the second terminal of the ninth resistor R9, the second terminal of the eleventh resistor R11, the second terminal of the thirteenth resistor R13, and the second terminal of the fifteenth resistor R15.

[0082] The second terminal of the first capacitor C1 is electrically connected to the second terminal of the second capacitor C2, the second terminal of the third capacitor C3, and the second terminal of the fourth capacitor C4, and grounded.

[0083] In this embodiment, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 can be conventional capacitors, which can serve as filters.

[0084] In one possible implementation, a power supply unit is also included;

[0085] The input terminal of the power supply unit is used to connect to an external power source, its first voltage terminal is used to provide the initial operating voltage VCC0, and its second voltage terminal is used to provide the second operating voltage VCC2.

[0086] In this embodiment, the external power supply can be 72V DC. The second operating voltage VCC2 can be provided to the main control unit and the display unit as operating voltage, and to the button unit as a high-level input source.

[0087] In one possible implementation, the power supply unit is built based on a power chip and a voltage regulator.

[0088] In this embodiment, both the power supply chip and the voltage regulator can be conventional components. When the external power supply is 72V, the power supply chip can convert the 72V voltage to 15V voltage as the initial operating voltage VCC0, and the voltage regulator can convert the 15V voltage to +5V voltage as the second operating voltage VCC2.

[0089] In one possible implementation, a zero-resistance interface k1 is provided between the high-side input terminal HIN and the low-side input terminal LIN of the test chip interface JP0.

[0090] In this embodiment, the zero-resistance interface k1 is a reserved resistor interface, which can be connected to a zero resistor according to test requirements. In specific implementation, a zero resistor, denoted as b1, can also be connected in series on the line where the high-side input terminal HIN is located, and a zero resistor, denoted as b2, can also be connected in series on the line where the low-side input terminal LIN is located. It should be noted that when AT and BT output high levels simultaneously, the dead time of the half-bridge driver chip U0 under test can be tested. At this time, it is necessary to subtract the start-up time difference inside the microcontroller program in the main control unit. By connecting a zero resistor at the zero-resistance interface k1, it is not necessary to subtract the start-up time difference of the microcontroller in the main control unit when testing the dead time.

[0091] In one possible implementation, a first zero resistance s1 is connected in series on the grounding line where the first terminal of the third switch SW3 is located;

[0092] A first energy storage capacitor bank is connected in parallel across the first zero resistance s1;

[0093] A second zero-resistance s2 is connected in series on the grounding line where the first terminal of the fourth switch SW4 is located.

[0094] A second energy storage capacitor bank is connected in parallel across the two ends of the second zero resistance s2.

[0095] In this embodiment, the first energy storage capacitor bank can be obtained by connecting three capacitors C11, C12, and C13 in parallel. The second energy storage capacitor bank can be obtained by connecting three capacitors C21, C22, and C23 in parallel. The first zero resistance s1 and the second zero resistance s2 are conventional zero resistances and are used as capacitor discharge resistors. Capacitors C11, C12, C13, C21, C22, and C23 are conventional capacitors and are used as energy storage capacitors.

[0096] This utility model also provides a test module for verifying the parameters of a half-bridge driver chip, including a PCB board and the test circuit described above.

[0097] The test circuit is mounted on the PCB board.

[0098] The above embodiments should not limit the present invention in any way. All technical solutions obtained by equivalent substitution or equivalent conversion fall within the protection scope of the present invention.

Claims

1. A test circuit for verifying the parameters of a half-bridge driver chip, characterized in that, It includes a test chip interface, a first switch, a second switch, a third switch, a fourth switch, a first resistor, a second resistor, a third resistor, a fourth resistor, a main control unit, a display unit, and a button unit; The test chip interface is used to connect to the half-bridge driver chip under test. Its power supply voltage terminal is electrically connected to its absolute voltage terminal, the first terminal of the first switch, and the first terminal of the second switch, and is used to connect to the first working voltage. Its high-side input terminal and low-side input terminal are electrically connected to the PWM output terminal group of the main control unit. Its ground terminal is electrically grounded. Its high-side output terminal is electrically connected to the first terminal of the first resistor and the first terminal of the second resistor, respectively. Its offset voltage terminal is electrically connected to the first terminal of the third switch and the first terminal of the fourth switch, respectively, and grounded. Its low-side output terminal is electrically connected to the first terminal of the third resistor and the first terminal of the fourth resistor, respectively. The second terminal of the first switch is electrically connected to the second terminal of the first resistor, and is electrically connected to the upper bridge current-pull signal terminal group of the main control unit via the high-side output terminal; The second terminal of the second switch is electrically connected to the second terminal of the third resistor, and is electrically connected to the low-side output terminal to the lower bridge pull-up current signal terminal group of the main control unit; The second terminal of the third switch is electrically connected to the second terminal of the second resistor, and is electrically connected to the upper bridge sink current signal terminal group of the main control unit via the high-side output terminal. The second terminal of the fourth switch is electrically connected to the second terminal of the fourth resistor, and is electrically connected to the lower bridge sink current signal terminal group of the main control unit via the low-side output terminal. The first signal receiving end of the main control unit is electrically connected to the output end of the button unit, and its communication end is electrically connected to the communication end of the display unit.

2. The test circuit according to claim 1, characterized in that, It also includes a switching unit; The output terminal of the switching unit is used to provide the first operating voltage, its control terminal is electrically connected to the control terminal of the main control unit, and its input terminal is used to connect the initial operating voltage.

3. The test circuit according to claim 2, characterized in that, The switching unit includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first NPN transistor, and a first PMOS transistor; The first end of the fifth resistor serves as the control end of the switching unit, and its second end is electrically connected to the first end of the sixth resistor and the base of the first NPN transistor. The second terminal of the sixth resistor is electrically connected to the emitter of the NPN transistor and grounded; The first end of the seventh resistor is electrically connected to the collector of the NPN transistor, and its second end is electrically connected to the first end of the eighth resistor and the gate of the first PMOS transistor. The second end of the eighth resistor is electrically connected to the source of the PMOS transistor as the input terminal of the switching unit. The drain of the PMOS transistor serves as the output terminal of the switching unit.

4. The test circuit according to claim 2, characterized in that, The button unit includes a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, and a sixteenth resistor; The first end of the fifth switch is electrically connected to the first end of the sixth switch, the first end of the seventh switch, and the first end of the eighth switch and grounded, respectively; its second end is electrically connected to the first end of the ninth resistor and the first end of the tenth resistor, respectively. The second terminal of the sixth switch is electrically connected to the first terminal of the eleventh resistor and the first terminal of the twelfth resistor, respectively. The second terminal of the seventh switch is electrically connected to the first terminal of the thirteenth resistor and the first terminal of the fourteenth resistor, respectively. The second terminal of the eighth switch is electrically connected to the first terminal of the fifteenth resistor and the first terminal of the sixteenth resistor, respectively. The second end of the ninth resistor, the second end of the eleventh resistor, the second end of the thirteenth resistor, and the second end of the fifteenth resistor are combined to serve as the output terminal of the button unit; The second end of the tenth resistor is electrically connected to the second ends of the twelfth resistor, the fourteenth resistor, and the sixteenth resistor, respectively, and is used to connect to the second operating voltage.

5. The test circuit according to claim 4, characterized in that, The button unit also includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; The first terminal of the first capacitor, the first terminal of the second capacitor, the first terminal of the third capacitor, and the first terminal of the fourth capacitor are respectively electrically connected to the second terminal of the ninth resistor, the second terminal of the eleventh resistor, the second terminal of the thirteenth resistor, and the second terminal of the fifteenth resistor; The second terminal of the first capacitor is electrically connected to the second terminal of the second capacitor, the second terminal of the third capacitor, and the second terminal of the fourth capacitor, and is grounded.

6. The test circuit according to claim 4, characterized in that, It also includes a power supply unit; The input terminal of the power supply unit is used to connect to an external power source, its first voltage terminal is used to provide the initial operating voltage, and its second voltage terminal is used to provide the second operating voltage.

7. The test circuit according to claim 6, characterized in that, The power supply unit is built based on a power chip and a voltage regulator.

8. The test circuit according to claim 1, characterized in that, A zero-resistance interface is provided between the high-side input terminal and the low-side input terminal of the test chip interface.

9. The test circuit according to claim 1, characterized in that, A first zero-resistance is connected in series on the grounding line where the first terminal of the third switch is located; A first energy storage capacitor bank is connected in parallel across the first zero resistance; A second zero-resistance is connected in series on the grounding line where the first terminal of the fourth switch is located; A second energy storage capacitor bank is connected in parallel across the second zero resistance.

10. A test module for verifying parameters of a half-bridge driver chip, characterized in that, Includes a PCB board and a test circuit as described in any one of claims 1 to 9; The test circuit is mounted on the PCB board.

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