A detection device for TOLL packaged semiconductor

Abstract

The utility model provides a kind of detection device for TOLL encapsulated semiconductor, it is related to integrated circuit chip packaging technical field, for and the pin contact of TOLL encapsulated semiconductor component and carry out detection, including detection circuit, further include: carrier plate;Test piece, have multiple groups, all be located carrier plate top, each group of test piece includes multiple pairs of test piece, two test pieces in each pair of test piece are spaced apart parallel arrangement, the interval direction of two test pieces in each pair of test piece is parallel to the board surface of carrier plate, the interval direction of each pair of test piece of same group is identical, the projection of multiple pairs of test pieces of same group along the interval direction of this group test piece coincides, test piece upper surface is all coplanar, test piece upper surface is all equipped with golden finger, test piece is electrically connected with detection circuit.

Description

Technical Field

[0001] This application relates to the field of integrated circuit chip packaging technology, specifically to a testing device for TOLL-packaged semiconductors. Background Technology

[0002] After semiconductor products are packaged, their internal structure and electrical properties need to be tested and differentiated. During the testing process, it is essential to ensure that each pin of the semiconductor product makes good contact with the gold fingers of the testing device before proceeding with other functional tests. This is to avoid misjudgments and product damage caused by poor contact. With existing testing devices, when the gold fingers contact and press down on the pins of the semiconductor product, the two gold fingers contacting the same pin are prone to different contact forces and contact areas due to uneven pressure on the pin. This results in significant changes in the resistance of the two gold fingers and a higher probability of poor contact. Utility Model Content

[0003] To address the aforementioned deficiencies in the prior art, this application provides a testing device for TOLL-packaged semiconductors, which can reduce the probability of poor contact during the testing of TOLL-packaged semiconductors and has strong practicality.

[0004] To achieve the above objectives, the present invention employs the following technology: A detection device for TOLL-packaged semiconductors, used for contacting and detecting the pins of TOLL-packaged semiconductor components, includes a detection circuit, characterized in that it further includes: Carrier plate; The test pieces are arranged in multiple sets, all positioned above the carrier plate. Each set of test pieces includes multiple pairs of test pieces. The two test pieces in each pair are arranged parallel to each other with a gap. The gap direction between the two test pieces in each pair is parallel to the surface of the carrier plate. The gap direction of each pair of test pieces in the same set is the same. The projections of multiple pairs of test pieces in the same set along the gap direction of the set of test pieces coincide. The upper surfaces of the test pieces are all coplanar. Each upper surface of the test piece is provided with gold fingers. Each test piece is electrically connected to the detection circuit.

[0005] Furthermore, the carrier plate also includes multiple support blocks, the number of which is equal to the number of test pieces. Each support block corresponds to each test piece group. Each support block is provided with multiple connecting strips. The number of connecting strips on each support block is equal to the number of test pieces in the test piece group corresponding to that support block. One end of the connecting strip is electrically connected to the test piece, and the other end of the connecting strip is electrically connected to the detection circuit.

[0006] Furthermore, a support strip is connected to one of the support blocks, and a contact block is connected to the support strip. The upper surface of the contact block is coplanar with the upper surface of the test piece.

[0007] The beneficial effects of this utility model are as follows: By arranging the two test pieces in each pair of test pieces in parallel with a gap, and ensuring that the projections of the test pieces in the same group coincide along the parallel direction of the gap, when a pin contacts the gold fingers on a pair of test pieces, the gold fingers on the pair of test pieces contact the two sides of the pin respectively. When the TOLL packaged semiconductor component is pressed down to make the gold fingers on the pair of test pieces contact the pin more tightly, the contact force and contact area between the two gold fingers and the pin are always equal, thereby reducing the probability of poor contact. Attached Figure Description

[0008] Figure 1 This is a perspective view of a detection device for TOLL-packaged semiconductors according to an embodiment of this application.

[0009] Figure 2 This is a schematic diagram of the connection of the detection circuit in an embodiment of this application.

[0010] Figure 3 This is a schematic diagram illustrating the interaction between a three-level TOLL packaged semiconductor component product and a testing device according to an embodiment of this application.

[0011] The markings in the diagram are: 1-TOLL packaged semiconductor component, 11-pin, 2-carrier board, 21-support block, 22-connector bar, 23-support bar, 24-contact block, 3-test chip, 31-gold finger. Detailed Implementation

[0012] To make the objectives, technical solutions and advantages of the present utility model clearer, the implementation methods of the present utility model will be described in detail below with reference to the accompanying drawings. However, the embodiments described in the present utility model are only some embodiments of the present utility model, and not all embodiments.

[0013] like Figure 1 As shown, this embodiment provides a testing device for TOLL-packaged semiconductors, used to contact and test the pins of the TOLL-packaged semiconductor component 1. The device includes a testing circuit, a carrier board 2, and a test piece 3. The testing circuit, which is prior art, is used to test the TOLL-packaged semiconductor and is therefore not described in detail here. Figure 1 The diagram shows the connection details and working principle of the detection circuit; please refer to the diagram below. Figure 2 And the relevant paragraphs below regarding the working principle of the device.

[0014] Specifically, such as Figure 1 As shown, the carrier plate 2 is rectangular and is used to support the detection device; Specifically, such as Figure 1As shown, there are multiple sets of test pieces 3. More specifically, the number of test pieces 3 sets is equal to the number of ends of the TOLL-packaged semiconductor component 1 under test with test pins 11. Each set of test pieces 3 corresponds to each end of the TOLL-packaged semiconductor component 1 under test with test pins 11. In this example, the TOLL-packaged semiconductor component 1 has pins 11 at both ends, so there are two sets of test pieces 3. The test pieces 3 are all located above the carrier board 2. Each set of test pieces 3 includes multiple pairs of test pieces 3. More specifically, the number of pairs of test pieces 3 in each set of test pieces 3 is equal to the number of test pins 11 at one end of the TOLL-packaged semiconductor component 1 under test. In this example, the TOLL-packaged semiconductor component 1 under test has eight pins 11 at each end. With two pins 11, the two sets of test pieces 3 respectively include eight pairs of test pieces and two pairs of test pieces; the two test pieces 3 in each pair of test pieces 3 are arranged in parallel with a gap, and the gap direction of the two test pieces 3 in each pair of test pieces 3 is parallel to the surface of the carrier board 2. The gap direction of each pair of test pieces 3 in the same group is the same. The projections of multiple pairs of test pieces 3 in the same group along the gap direction of the test pieces 3 in that group coincide. The upper surfaces of the test pieces 3 are all coplanar. The upper surfaces of the test pieces 3 are provided with gold fingers 31. The test pieces 3 are all electrically connected to the detection circuit. More specifically, the position of each pair of test pieces 3 should correspond to the position of the pin 11 to be tested in the TOLL packaged semiconductor component 1 to be tested, so that the gold fingers 31 on each pair of test pieces 3 can contact the pin 11 to be tested respectively during the test.

[0015] With this design, when one pin 11 contacts the gold fingers 31 on a pair of test pieces 3, the gold fingers 31 on the pair of test pieces 3 contact the two sides of the pin 11 respectively. When the TOLL packaged semiconductor component 1 is pressed down to make the gold fingers 31 on the pair of test pieces 3 contact the pin 11 more tightly, the contact force and contact area between the two gold fingers 31 and the pin 11 are always equal, thereby reducing the probability of poor contact.

[0016] During operation, the TOLL-packaged semiconductor component 1 to be tested is placed on the device and pressed down so that each pin 11 to be tested contacts the corresponding pair of gold fingers 31. At this time, the TOLL-packaged semiconductor component 1 can be tested through the detection circuit.

[0017] like Figure 2 and Figure 3 As shown, taking the testing of a three-level TOLL packaged semiconductor component 1 as an example, Figure 2A schematic diagram of a detection circuit is shown: the positive terminal of the power supply is connected to relay K1; relay K1 is connected to relay K3; relay K3 is connected to the CI terminal of the first pair of gold fingers 31; the CV terminal of the first pair of gold fingers 31 is connected to relay K29; relay K29 is connected to the BV terminal of the second pair of gold fingers 31; the BI terminal of the second pair of gold fingers 31 is connected to relay K57; relay K57 is connected to the EI terminal of the third pair of gold fingers 31; the EV terminal of the third pair of gold fingers is connected to relay K58; relay K58 is connected to the negative terminal of the power supply; the V terminals of the tester are connected to relay K5 and relay K21 respectively; the circuit between relay K3 and the CI terminal of the first pair of gold fingers 31 is connected to relay K5; and the circuit between the EV terminal of the third pair of gold fingers and relay K58 is connected to relay K21.

[0018] The detection principle of this circuit is as follows: The product is placed on the testing device, with the three pins 11 contacting the three pairs of gold fingers 31 respectively. The CV terminal of the first pair of gold fingers 31 is connected to the CI terminal, the BV terminal of the second pair of gold fingers 31 is connected to the BI terminal, and the EV terminal of the third pair of gold fingers 31 is connected to the EI terminal. At this time, the positive terminal of the power supply, relays K1 and K3, the CI terminal of the first pair of gold fingers 31, the CV terminal of the first pair of gold fingers 31, relay K29, the BV terminal of the second pair of gold fingers 31, the BI terminal of the second pair of gold fingers 31, relay K57, the EI terminal of the third pair of gold fingers 31, the EV terminal of the third pair of gold fingers 31, relay K58, and the negative terminal of the power supply are sequentially connected, forming a closed-loop series circuit. When this closed-loop circuit is formed, a tester V is used to measure the voltage across relays K5 and K21, monitoring the effect of the resistance change of the entire circuit on the voltage, i.e., performing the test.

[0019] Preferred, such as Figure 1 As shown, the carrier plate 2 also includes multiple support blocks 21. The number of support blocks 21 is equal to the number of test pieces 3 groups. That is, in this example, there are two support blocks 21. Each support block 21 corresponds to each group of test pieces 3. Each support block 21 is provided with multiple connecting strips 22. The number of connecting strips 22 on each support block 21 is equal to the number of test pieces 3 in the group of test pieces 3 corresponding to that support block 21. That is, in this example, one support block 21 is provided with sixteen connecting strips 22, and the other support block 21 is provided with four connecting strips 22. One end of the connecting strip 22 is electrically connected to the test piece 3, and the other end of the connecting strip 22 is electrically connected to the detection circuit. The connecting strip 22 is used to support the test piece 3 and provides space for the test piece 3 to move downward through its own deformation during the pressing process of the TOLL packaged semiconductor component 1.

[0020] Preferred, such as Figure 1As shown, a support bar 23 is connected to one of the support blocks 21. In this example, two support bars 23 are connected. The support bars 23 are connected to contact blocks 24. The upper surface of the contact block 24 is coplanar with the upper surface of the test piece 3. The contact block 24 is used to contact the lower surface of the TOLL packaged semiconductor component 1 when the pin 11 contacts the gold finger 31, so that the contact between the pin 11 and the gold finger 31 is more stable.

[0021] The above description is only a preferred embodiment of this application and is not intended to limit this application. Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application.

Claims

1. A detection device for a TOLL-packaged semiconductor, for contacting and detecting the pins (11) of a TOLL-packaged semiconductor component (1), comprising a detection circuit, characterized in that, Also includes: Carrier plate (2); There are multiple sets of test pieces (3), all of which are set above the carrier plate (2). Each set of test pieces (3) includes multiple pairs of test pieces (3). The two test pieces (3) in each pair of test pieces (3) are arranged in parallel with each other at intervals. The spacing direction of the two test pieces (3) in each pair of test pieces (3) is parallel to the surface of the carrier plate (2). The spacing direction of each pair of test pieces (3) in the same set is the same. The projections of multiple pairs of test pieces (3) in the same set along the spacing direction of the test pieces (3) in that set coincide. The upper surfaces of the test pieces (3) are all coplanar. The upper surfaces of the test pieces (3) are all provided with gold fingers (31). The test pieces (3) are all electrically connected to the detection circuit.

2. The testing device for TOLL-packaged semiconductors according to claim 1, characterized in that, The carrier plate (2) also includes multiple support blocks (21). The number of support blocks (21) is equal to the number of test pieces (3). Each support block (21) corresponds to each group of test pieces (3). Each support block (21) is provided with multiple connecting strips (22). The number of connecting strips (22) on each support block (21) is equal to the number of test pieces (3) in the group of test pieces (3) corresponding to that support block (21). One end of the connecting strip (22) is electrically connected to the test piece (3), and the other end of the connecting strip (22) is electrically connected to the detection circuit.

3. The testing device for TOLL-packaged semiconductors according to claim 2, characterized in that, One of the support blocks (21) is connected to a support strip (23), and the support strip (23) is connected to a contact block (24). The upper surface of the contact block (24) is coplanar with the upper surface of the test piece (3).

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